JPH03253118A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of unlocking at the time of no signal and to improve the responseness of a loop by providing a phase locked loop circuit with a signal generating means for generating a signal with frequency almost equal to the frequency of an input signal. CONSTITUTION:The frequency of a signal F3 outputted from a reference oscillator 11 is set up to a value almost equal to the reference clock frequency of a digital signal F1. An envelope detector 10 detects a reproduced signal F0 and outputs an envelope waveform as a driving signal S for a change-over switch 13 in the phase locked loop circuit 1. When the signal F0 is not inputted, the level of the driving signal S is in the low level, and the switch 13 is turned to the contact (a) side. In the no signal period, the output F3 of the oscillator 11 is inputted to the reference input terminal of a phase comparator 2. Thereby, the loop responseness and stability of the circuit can be improved without generating unlocking even in the no signal period.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase-locked loop circuit suitably implemented in a digital audio tape playback device or the like.

BACKGROUND ART In devices that reproduce digital signals from recording media, such as digital audio chip playback devices (so-called DAT devices), in order to demodulate digital signals,
It is necessary to extract the clock signal component from the input signal, and for this purpose a phase-locked loop (hereinafter referred to as P
A circuit called LL is often used.

FIG. 3 shows a D
3 is a block diagram showing the configuration of an AT device 30. FIG. Information recorded on the magnetic tape 36 is reproduced by a magnetic head 37, amplified and equalized via an equalizer (signal equalization circuit) 39, a digital signal F31 is derived via a comparator 39, and the data is input to the latch circuit 40. The signal is input to one input terminal of the phase comparator circuit 32 that constitutes the PLL circuit 31.

The phase comparison circuit 32 compares the timing of the level transition point (edge) of the digital signal F31 with the timing of the voltage controlled oscillation circuit (hereinafter referred to as VC○ circuit) 34 which is input to the other input terminal via the feedback line n31. The phase error p is detected by comparing the edge timing of the output signal F32. The phase error p is converted into a DC voltage d by the low-pass filter 33 and applied to the control voltage terminal of the VC○ circuit 34. As a result, the oscillation frequency of the VC◯ circuit 34 changes, and is pulled in to the frequency of the digital signal F31, thereby locking the phase. The output signal F32 of the locked VC0 circuit 34 is applied to the clock input terminal CK of the latch circuit 25 to latch the digital signal F31, and the digital signal F31 is latched.
An output phase synchronized with 31 is led out on line 132.

Problems to be Solved by the Invention However, the rotary head type digital audio device (hereinafter referred to as R-DAT device) is
As shown in the figure, the angle of the tape 36 wound around the drum 41 is set to 90'' and is alternately reproduced by magnetic heads 41a and 741b arranged vertically at 180 degrees, so that the obtained reproduction signal is As shown in FIG. 5, the burst waveform includes a signal pause period Tp between the reproduced signals AB.Therefore, the signal pause period Tp corresponds to the VC○ circuit 3.
The oscillation of 4 becomes a free oscillation state and the target digital signal F
31, the response time until the oscillation frequency is locked by the next reproduction signal B becomes long, and data reading errors occur until the next lock is achieved.

Therefore, in order to eliminate the above-mentioned problems, as shown in FIG. 3, a variable resistor 35 with a semi-fixed resistance value is connected to the VCO circuit 34 in advance, and this variable resistor 35 is adjusted to 34 in a free oscillation state at the clock frequency of the digital signal F31, and the signal stop period Tp
A circuit has been proposed in which oscillation based on the clock frequency continues even when the clock frequency changes.

However, providing such adjustment points requires labor and time for adjustment, and DAT devices and
This complicates the production process of devices incorporating the LL circuit 31 and increases production costs.

It also has the undesirable problem that the frequency fluctuates due to the change in resistance value over time.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a phase-locked loop circuit that has a simple configuration and has good responsiveness to the locked state of the oscillation frequency.

Means for Solving the Problems The present invention provides the first
a first signal generating means for outputting a signal; a phase difference detecting means for detecting a phase difference between an input signal and a first signal from the first signal generating means; forming a closed loop consisting of signal converting means that converts the first signal into a control voltage that changes the first signal so as to reduce the phase difference and supplies it to the first signal generating means, and outputs the first signal that is phase-synchronized with the input signal. A phase-locked loop circuit comprising: signal detection means for detecting the presence or absence of the input signal; second signal generation means for outputting a second signal having a frequency approximately equal to the frequency of the input signal; and an output of the signal detection means. Correspondingly, the phase-locked loop circuit is characterized in that it includes switching means for selecting either the input signal or the output of the second signal generating means and connecting it to the phase difference detecting means.

Operation The phase-locked loop circuit according to the present invention provides a second signal which generates a second signal having a frequency approximately equal to the frequency of the input signal.
The signal generating means is provided, the presence or absence of an input signal is detected by the signal detecting means, and when there is no input signal, the signal input to the phase difference detecting means is switched to the output of the second signal generating means, and when there is no signal, Prevents lock release and improves loop responsiveness.

Embodiment FIG. 1 is a block diagram showing a circuit configuration of a DAT device 15 using a phase-locked loop (hereinafter referred to as PLL) circuit 1 according to the present invention. The PLL circuit 1 according to the present invention includes a phase comparator 2 as a phase difference detection means, a low-pass filter 3 as a signal conversion means, and a voltage controlled oscillation circuit as a first signal generation means (hereinafter referred to as VC○ circuit) 4 and a feedback line 11 form a closed loop, a phase-locked loop, and a reference signal input terminal of the phase comparator 2 receives a digital signal F1 obtained from the tape 5 and a reference oscillator 11 which is a second signal generating means. The second means F which is the output of
3 is selectively inputted via a changeover switch 13 which is a changeover means.

The changeover switch 13 is realized by an electronic switch such as an analog switch, and is switched and driven by the output of the envelope detector 10, which is a signal detection means. The reference oscillator 1] is a crystal oscillator using a crystal oscillator 12, and is set to a frequency equal to the reference clock frequency of the input digital signal F1.
Signal F3 is stable and has high frequency accuracy.

Next, the operation of this embodiment will be explained with reference to FIG. Information recorded as binary data on the magnetic tape 5 is reproduced by the magnetic head 6, and is amplified and equalized via the equalizer (signal equalization circuit) 7, as shown in FIG. 2 (1). The output signal FO from the A channel and the B channel is output to the comparator 8 and the envelope detector 10 provided in the PLL circuit 1.

The reproduced signal FO is converted into a digital signal F by a comparator 8.
1, and is input to the data input terminal of the latch circuit 9 realized as a D-type flip-flop circuit and the contact point of the changeover switch 13. The clock terminal CK of the latch circuit 9 receives the clock output F2 from the PLL circuit 1.
is input, and a desired clock signal can be obtained.

The envelope detector 10 detects the reproduced signal FO shown in FIG. 2(1) and outputs the envelope waveform shown in FIG. 2(2) as the drive signal S for the changeover switch 13. The level of the drive signal S is low when the signal FO is not input, and is high when the signal FO is input. The changeover switch 13 is set to be switched to the contact a side when the level of the drive signal S is low level, and to the contact side when the drive signal S is high level. Therefore, during the no-signal period Tp in FIG. 2(1), the output F3 of the reference oscillator 11 is input to the reference input terminal of the phase comparator 2.

The phase comparator 2 is realized, for example, by a plurality of EX-OR gates, and compares the edge timing of the input signal with the edge timing of the output F2 of the CO circuit 4 inputted via the feedback line 11. , the phase difference error signal P outputting the phase error signal p is converted into a control voltage d by the low-pass filter 3, and is applied to the VCO00 circuit control terminal, thereby locking the output of the VCO 4 to the phase of the input digital signal F1.

As mentioned above, the frequency of the second signal F3 of the reference oscillator 11 is set to be, for example, approximately equal to the reference clock frequency of the digital signal F1, so there is a small phase error between them, and the control input to the VCO00 circuit The voltage d is
It does not change much depending on the presence or absence of the signal FO. Therefore, the PLL circuit 1 according to this embodiment has a quick response to the locked state of the oscillation frequency, and in the no-signal period Tp, V
The CO00 circuit output F2 is locked to the frequency of the oscillation output F3, and when the digital signal F1 is input, it immediately locks to the frequency of the input signal F1, so the VC
Adjustment of the free oscillation frequency of the O circuit becomes unnecessary. Therefore, the time and labor required for this purpose are saved, the production process is simplified, and production costs are significantly reduced.

Although the above embodiment describes the case of an R-DAT device, the present invention is not limited to this, and any clock recovery circuit for a burst input signal may be used.
It goes without saying that the present invention can also be applied to cases other than magnetic recording/reproducing devices.

As described above, the face-lock drawer circuit of the present invention has the following advantages:
A second signal generation means whose oscillation frequency is approximately equal to the reference clock frequency of the input signal is provided, a signal detection means detects a no-signal period of the input signal, and the detected output is switched to the output of the second signal generation means to adjust the oscillation frequency. was made to lock. Therefore, even during a no-signal period, locking does not occur, the loop response and stability are high, and there is no effect of aging, thus improving the reliability of the device.

Although the present invention has a simple additional circuit configuration, parts and adjustment work for adjusting the free oscillation frequency of the phase-locked loop circuit can be omitted, which eliminates the time and labor required in the past and simplifies the production process. The effects are extremely large, including a significant reduction in production costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the PLL circuit of the present invention,
Fig. 2 is a waveform diagram showing the output waveform of the envelope detector of this embodiment, Fig. 3 is a block diagram showing the configuration of a PLL circuit according to the conventional technology, and Fig. 1 is a tape of rotary digital audio tape (RDAT). FIG. 5 is a waveform diagram showing the output waveform.

Claims (1)

[Claims] First signal generating means for outputting a first signal with a frequency corresponding to a given control voltage; detecting a phase difference between an input signal and a first signal from the first signal generating means; and signal converting means that converts the output of the phase difference detection means into a control voltage that changes a first signal so as to reduce the phase difference, and supplies the control voltage to the first signal generation means. A phase-locked loop circuit that forms a closed loop and outputs the first signal in phase synchronization with the input signal, comprising: a signal detection means for detecting the presence or absence of the input signal; and a second signal having a frequency substantially equal to the frequency of the input signal. a second signal generating means for outputting a signal; and switching for selecting either the input signal or the output of the second signal generating means and connecting it to the phase difference detecting means in accordance with the output of the signal detecting means. A phase-locked loop circuit comprising means.