JPH04162263A - Information reproducing device - Google Patents

Abstract

PURPOSE:To prevent the reproduction error rate from increasing by making the responding speed of a PLL faster for a fixed period of time after the leading signal and switching the responding speed of the PLL to a slower speed after the fixed period of time. CONSTITUTION:The first and second charge pumps 2a and 2b are used as the charge pumps constituting a phase-locked loop(PLL) circuit and a monostable multivibrator 8 outputs a high-level signal for a fixed period of time after a lead gate signal rises. During the period when the signal S2 from the monostable multivibrator 8 is high in level, the charge pumps 2a and 2b simultaneously operate and the responding speed of a PLL can be made faster, because the loop gain of the PLL becomes larger. During ordinary time, the output current is reduced by actuating the pump 2a only and the responding speed of the PLL is made slower. Therefore, the occurrence of a reproduction error can be prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a playback device that plays back information recorded on an information recording medium such as a disk, tape, or card, particularly a PL.
The present invention relates to a self-clocking information reproducing device using an L (phase-locked loop) circuit.

(Prior art) Figure 3 shows an example of the sector format of an optical disc.
The figure shows the details of the sector format. In the figure, SM is a sector mark indicating the beginning of a sector, and VFO1 to VFO3 are sections for pulling in (locking) the PLL. In each section of this VFO,
As shown in FIG. 4, a repeating pattern of "100" is usually recorded. The PLL is required to be locked quickly within this interval, otherwise errors will occur in data reproduction. Further, it is desirable to make the VFO section as short as possible in order to effectively utilize the recording area of the disk, but to do so, the loop gain of the PLL must be increased to speed up the PLL pull-in. On the other hand, in the data section, it is desirable that the PLL clock be stable regardless of noise, signal defects, and the like. Therefore, - degree P
Once the LL is locked, it is necessary to slow down the PLL response speed by increasing the time constant of the loop filter.

FIG. 5 is a block diagram of a generally well-known PLL circuit. In the figure, 1 is a phase comparator that compares the phase of an input reproduction signal and a clock, 2 is a charge pump, 3 is a loop filter, and 4 is a VCO (voltage controlled oscillator). In such a PLL circuit,
To reduce the response speed of the PLL so as to stabilize the operation of the loop, there are the following numerical methods.

(1) By lowering the gain constant of phase comparator 1,
Reduce loop gain.

(2) By reducing the output current of charge pump 2, the loop gain is lowered.

(3) Narrow the bandwidth of the loop filter 3 to lower the loop gain.

(4) By increasing the damping factor of the loop filter 3, the loop gain is lowered.

(5) Lower the loop gain by lowering the F-V conversion gain constant of VCO4.

FIG. 6 shows an example of a signal reproducing circuit of a conventional information reproducing device. 5 is a PLL circuit shown in FIG. 5, 6 is a latch, and 7 is a pattern detection circuit. The signal input to the PLL 5 is switched to a reproduced signal and a constant reference clock by a fixed gate signal. The read gate signal is a signal created based on the sector format SM shown in FIG. 3 by a controller (not shown) in the information reproducing device.
This is a signal that rises near the start of VFO and falls near PA. When the read gate signal is not active, a reference constant clock is input, and the PLL 5 locks to the constant clock and outputs a clock of a constant frequency. When the read gate signal becomes active, the input to PLL5 is switched to the playback signal, and PLL5 attempts to synchronize to the playback signal. When the PLL is pulled in and locked, the stable pattern of "100", which is the VFO pattern described above, is reproduced. The pattern detection circuit 7 is
This “100” pattern continues for a certain number of times or more,
When the detection is stable, it is determined that the PLL is locked, and a loop gain switching signal is output to the PLL5. P
The LL5 lowers the loop gain based on the switching signal, thereby slowing down the response speed of the PLL5, thereby stabilizing the loop of the PLL5. To lower this loop gain, for example, the gain constant of the phase comparator is lowered, as described above. In addition to detecting the VFO pattern, the pattern voltage detection circuit 7 may also detect an AM or 5YNC pattern shown in the sector format of FIG. 3 to switch the loop gain.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional information reproducing device, if the quality of the reproduced signal deteriorates, there is a possibility that it will not be possible to detect repetitions of the VFO pattern more than a predetermined number of times. In such a case, the PLL reproduces data in an unstable state, resulting in a high reproduction error rate due to PLL jitter.

The present invention has been made to solve these problems, and its purpose is to provide a highly reliable information reproducing apparatus that prevents the occurrence of reproduction errors as much as possible.

[Means for Solving the Problems] An object of the present invention is to provide an information amphibious device that reproduces information recorded on an information recording medium using a self-clocking method using a phase-locked loop circuit. means for measuring a predetermined fixed time from approximately the leading position of the pattern for a predetermined pattern on a medium; This is achieved by an information reproducing apparatus characterized in that it is provided with means for switching so that the response speed is slower than the response speed.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information reproducing apparatus of the present invention. In FIG. 1, the same parts as those of the conventional device shown in FIGS. 5 and 6 are marked with the same stone ribs.

In FIG. 1, 1 is a phase comparator constituting a PLL circuit, 3 is a loop filter, and 4 is a CO. These are all the same as shown in FIG. In addition, in this embodiment, the first charge pump 2a and the second charge pump 2b are used as charge pumps constituting the PLL circuit.
are using. First and second charge pumps 2a, 2
As b, those having the same characteristics are used. 8 is a monostable multi-by-break (hereinafter abbreviated as mono-multi), which is a circuit that outputs a high level signal for a predetermined period of time from the rise of the read gate signal. mono multi 8
The output signal of is used as a signal to open the gate of AND circuit 9.10. Note that the latch 6 is the same as that shown in FIG.

Next, the operation of this embodiment will be explained with reference to the time chart shown in FIG. FIG. 2(a) shows a reproduction signal reproduced from an information recording medium such as an optical disk (not shown).

Although mark names such as SM and VFOl are shown here, they are actually reproduction signals of each mark pattern. Second
Figure (b) is a read gate signal, which is a signal generated by a controller (not shown) as described above.

This controller uses sector marks (SM) as shown in the figure.
), a read gate signal is generated so that it rises near the start of VFO and falls near PA. The read gate signal is output to the switch element 11 and used as a switching signal for the signal S input to the phase comparator 1. The reproduced signal read from the recording medium and the reference constant clock are input to the phase comparator 1 via a switch element 11, and by switching the switch element 11 with a read gate signal, the signal to the phase comparator 1 is Select input signal. Here, as shown in FIG. 2(C), the switch element 11 is operated to switch to the reproduction signal when the read gate signal is at a high level, and to switch to the constant reference clock when it is at a low level.

On the other hand, the read gate signal is input to the monomulti 8, and in the mono multi 8, as shown in FIG. Output to. The time T of the output of the monomulti 8 is set so that it falls near the end of the VFO. As a result, the gates of the AND circuits 9 and 10 are open during the time period T, and the phase comparator 1
The phase lead signal and phase delay signal from the AND circuit 9.1
It is output to the second charge pump 2b via o. Therefore, the second charge pump 2b becomes active and operates according to the input signal. On the other hand, since the first charge pump 2a is always inputted with phase lead and phase delay signals from the phase comparator 1, during the time T when the signal S2 from the monomulti 8 is at a high level, the first charge pump 2a and the first charge pump 2a The two charge pumps 2a and 2b operate simultaneously.

When the first and second charge pumps 2a and 2b operate in this way, the output current of the charge pumps doubles, so the loop gain of the PLL increases, and the response speed of the PLL can be increased. To reduce the response speed of the PLL, the output current of the charge pump should be reduced as described above, so normally the first charge pump 2
Operate only a to reduce the output current. Then, during the period corresponding to the VFO, the output current is doubled by operating the first and second charge pumps 2a and 2b. Therefore, during the operating period of the first and second charge pumps 2a and 2b, that is, when the output of the monomulti 8 is at a high level, it is possible to increase the response speed of the PLL as shown in FIG. 2(e). can. Therefore, since it is possible to pull in the PLL within a short VFO pattern period, the disk can be used more effectively. Also, V
After passing the FO pattern, the response speed of the PLL is slowed down, so that the data section can output a stable PLL clock.

In addition, in the above embodiment, an example was shown in which the output current of the charge pump was changed in order to change the response speed of the PLL, but the response is not limited to this, and the response can also be changed by lowering the gain constant of the phase comparator as described above. It is possible to reduce the speed. In addition, although we have shown an example of using a monomulti to set a certain period of time after the read gate signal rises, other time measurement means such as a counter that measures time by counting clocks can also be used. There may be. Furthermore, the present invention is not limited to the VFO pattern of the recording medium, but can also be applied to AM patterns, 5YNC patterns, etc.

[Effects of the Invention] As explained above, according to the present invention, for a predetermined pattern of an information recording medium, the PLL is activated for a certain period of time from approximately the beginning of the predetermined pattern.
By increasing the response speed of the PLL, the recording area of the recording medium can be used effectively, for example, in the case of a VFO pattern, the PLL can be pulled in with a short VFO pattern.Also, after a certain period of time, the PLL Since the response speed is switched to be slower, it is possible to output a stable clock in the data section.Furthermore, compared to the conventional method in which the response speed is switched by detecting that the PLL is locked, the present invention reduces the reproduction signal. This eliminates the problem of switching the PLL response speed incorrectly due to noise, defects, etc. Therefore, by reproducing data in an unstable state as in the past, the reproduction error rate due to PLL jitter increases. It is possible to prevent this from happening.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the embodiment of FIG. 1, and FIG. 3 is an explanatory diagram showing an example of the sector format of an optical disc.
FIG. 4 is an explanatory diagram showing details of the sector format shown in FIG. 3, FIG. 5 is a block diagram of a general PLL circuit, and FIG. 6 is a block diagram showing a conventional information reproducing apparatus. l two-phase comparator, 2a: first charge pump, 2b = second charge pump, 3: loop filter, 4: VCO1
6: Latch, 8: Monostable multivibrator,
9.10: AND circuit. Agent Patent Attorney Jo Taira Yamashita Figure 3 Figure 5 Figure 4 IQ, 1llnlli-''m'')

Claims (1)

[Claims] In an information reproducing device that reproduces information recorded on an information recording medium using a self-clocking method using a phase-locked loop circuit, a predetermined period of time is set for a predetermined pattern of the information recording medium from approximately the beginning position of the pattern. and means for switching the response speed of the phase-locked loop circuit to be slower than the response speed up to the predetermined time after the timer measures a predetermined time. Information reproducing device.