JP3342937B2 - Control device of data reproduction PLL circuit and data reproduction system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CD (Compac
t Disc) A data reproduction PLL (Phase Lock) for generating a bit clock for data reproduction in a player.
In particular, the present invention relates to a control device for controlling the phase lock performance to improve the speed of a search operation, and to an improvement of a data reproduction system including the control device .

[0002]

2. Description of the Related Art As is well known, a CD system and a CD-ROM
In a (Read Only Memory) data recording / reproducing system, it is indispensable that a so-called search operation for searching for a desired data portion from data recorded on a disk can be realized. At present, development for further speeding up this search operation is being actively conducted.

For example, in a data recording / reproducing system of a CD system, main data and address data indicating its position are
They are recorded on the disc in different formats. For this reason, the main data and the address data are signal-processed by different systems when the disc is reproduced. That is, the main data is 588 channel bits (136 μs
ec) and recorded on the disc. In this case, the main data is subjected to interleave processing, double error correction processing using P and Q parity, and the like for each frame.

On the other hand, address data is recorded on a disk as sub-code Q data, which is one bit of 8-bit sub-code data included in one frame. This subcode Q data is 1 in 98 frames.
It is configured to be completed as one address information.
In other words, at the time of normal disc reproduction, 98 frames × 136 μs to obtain one completed address information.
It takes a time of ec = 13.3 msec.

However, unlike the main data, the subcode Q data is not subjected to interleave processing, double error correction processing based on P and Q parity, and is checked using a 16-bit CRCC (Cyclic Redundancy Check Code). Only determines whether or not it is OK.

Therefore, in order to speed up the search operation, it is an important issue how quickly the subcode Q data can be read. In order to quickly read the subcode Q data, it is necessary to improve the lock performance so that the data reproduction PLL circuit for generating the data reproduction bit clock quickly enters the phase lock state. It is a necessary condition.

FIG. 7 shows a conventional data reproducing PLL circuit. That is, the optical pickup 1 is rotated from the disk 12 driven by the disk motor 11.
The signal read via 3 is converted by the current-voltage conversion circuit 14 into an RF (Radio Frequency) signal of a voltage change. This RF signal is divided by the data slice circuit 15 into 2
Valued and generally EFM (Eight to Fourteen Modula
) signal is converted into digital data called a signal.

The EFM signal is supplied to a reproduction processing circuit 16 where main data such as audio data is reproduced. The EFM signal output from the data slicing circuit 15 is supplied to a phase comparing circuit 17, and a clock CK generated from a VCO (Voltage Control Oscillator) 18 is frequency-divided by a frequency dividing circuit 19 to generate a phase synchronization signal. The phase is compared with the clock PLCK. Note that this phase synchronization clock PLCK is a bit clock BCK.
And supplied to the reproduction processing circuit 16 for reproduction processing of the main data.

The comparison result of the phase comparison circuit 17 is
LPF (LowPass Filter) circuit 2 via addition circuit 20
After the high frequency components are removed and
O18 is supplied as a control signal of the oscillation frequency.
Therefore, in the normal reproduction state of the disk 12, the data reproduction PLL circuit determines, based on the output of the phase comparison circuit 17, the phase difference between the EFM signal output from the data slice circuit 15 and the phase synchronization clock PLCK by a predetermined value. The oscillation frequency of the VCO 18 is controlled so as to fall within the capture range of, and a stable phase locked state is achieved.

By the way, the CD-type disc 12 includes:
Data is recorded in a CLV (Constant Linear Velocity) system. Therefore, the optical pickup 13 is
When a search operation is performed by moving the disk 12 from the inner peripheral side to the outer peripheral side or from the outer peripheral side to the inner peripheral side at a high speed, the rotation speed of the disk 12 corresponds to the position of the optical pickup 13. Until the steady value is settled, the frequency rate of the reproduced EFM signal greatly changes.

On the other hand, the above-mentioned phase comparison circuit 17, VCO
The PLL circuit for data reproduction comprising the frequency divider 18, the frequency divider 19 and the LPF circuit 21 generally has a narrow capture range that can be pulled into the phase locked state. For example, the EFM signal output from the data slice circuit 15 and the phase synchronous clock The phase locked state can be maintained only when the relative phase difference from the PLCK is within ± 5%.

On the other hand, the oscillation frequency of the VCO 18 is
To follow the wide rotational deviation of the disk 12 which definitive in high-speed search operation, ± 30 to 40% ones variable width is secured. Therefore, in the above-described PLL circuit for reproducing data having a narrow capture range, the subcode Q data is read unless the rotation speed of the disk 12 is settled to a steady value corresponding to the position of the optical pickup 13 during the search operation. This makes it difficult to perform the search operation at high speed.

Therefore, conventionally, the oscillation frequency of the VCO 18 is adjusted so that the phase difference between the EFM signal output from the data slice circuit 15 during the search operation and the phase synchronization clock PLCK falls within the narrow capture range. By actively driving in, the search operation is speeded up. That is, in FIG.
The clock CK output from the CO 18 is supplied to the frequency detection circuit 22.

The frequency detecting circuit 22 detects a frame synchronization pattern of the EFM signal output from the data slicing circuit 15 at the beginning of each frame. In this frame synchronization pattern, the period of the phase synchronization clock PLCK at the time of normal reproduction is set to T (1/4.
3218 MHz), it has a maximum polarity inversion interval of 11T in the EFM signal. Therefore, the frequency detection circuit 22 counts the clock CK output from the VCO 18 and determines whether a polarity inversion interval corresponding to 11 cycles of the phase synchronization clock PLCK exists in the input EFM signal at a predetermined cycle. Is determined.

When the polarity inversion interval corresponding to 11 cycles of the phase synchronization clock PLCK exists at a predetermined cycle in the input EFM signal, the frequency detection circuit 22 outputs the data from the data slice circuit 15. It is determined that the phase difference between the EFM signal and the phase-locked clock PLCK falls within the above-described narrow capture range, and its output is set to HiZ (high impedance) so as not to be involved in the operation of the data reproducing PLL circuit. Works like that.

The frequency detection circuit 22 determines that the polarity inversion interval of the input EFM signal is equal to the phase synchronization clock PLCK.
If the period is less than the 11 periods, an H (High) level is output to the addition circuit 20 to operate to increase the oscillation frequency of the VCO 18. Further, when the polarity inversion interval of the input EFM signal is equal to or longer than 11 cycles of the phase-locked clock PLCK, the frequency detection circuit 22 outputs the L (Low) level to the addition circuit 20 to change the oscillation frequency of the VCO 18. Works to lower.

The frequency of the operation clock of the frequency detection circuit 22 is 2 / T (8.64 MH) when the operation clock frequency is high and the disk 12 is in a normal reproduction state.
z) is appropriate. That is, this is the frequency dividing circuit 19
Of the frequency detection circuit 22 at this time is 0.5T width. Specifically, as shown in FIG. 8B, the frequency detection circuit 22 includes a phase synchronization clock PLC in the input EFM signal.
When the polarity inversion interval corresponding to 11T ± 0.5T of K exists at a predetermined cycle, the output thereof becomes the HiZ state.

The output of the frequency detection circuit 22 is HiZ
As shown in FIG. 8A, the period of the condition for the state becomes the phase comparison circuit 17, the VCO 18, the frequency divider 19, and the LPF.
This is a capture range in which the data reproduction PLL circuit including the circuit 21 can perform phase lock.

Further, the frequency detection circuit 22 determines that the polarity inversion interval of the input EFM signal is equal to the phase synchronization clock PLCK.
If the time is less than 11T-0.5T (this corresponds to a case where a search operation is performed from the inner circumference to the outer circumference of the disk 12), an H level is output to increase the oscillation frequency of the VCO 18. Operate. Further, the frequency detection circuit 2
2 indicates that the polarity inversion interval of the input EFM signal is equal to or more than 11T + 0.5T of the phase synchronization clock PLCK (this corresponds to a case where a search operation is performed from the outer circumference to the inner circumference of the disk 12). Output L level and VC
It operates so as to lower the oscillation frequency of O18.

Incidentally, the frequency detection circuit 22 described above
Detects the component having the maximum length corresponding to 11T of the phase synchronization clock PLCK from the EFM signal output from the data slice circuit 15.
In the FM signal, the polarity inversion interval is the phase synchronization clock P
A component shorter than 11T of the LCK, that is, a component corresponding to 10T of the phase synchronous clock PLCK, a component corresponding to 9T of the phase synchronous clock PLCK,..., A component corresponding to 3T of the phase synchronous clock PLCK ( (A component having the minimum polarity reversal interval).

Therefore, the frequency detection circuit 22
8 while controlling to increase the oscillation frequency of
Determination when switching to the iZ state, that is, VCO 18
Of the data slice circuit 15
From the polarity inversion interval of the EFM signal obtained from the phase synchronization clock PLCK for 11T-0.5T, and the frequency detection circuit 22 The determination when switching from the state in which the oscillation frequency is controlled to be lowered to the HiZ state, that is, the oscillation frequency of the VCO 18 is sequentially reduced, and the determination is made during the polarity inversion interval of the EFM signal obtained from the data slice circuit 15. In addition, there is a problem that the probability that an error occurs in determining that 11T + 0.5T of the phase synchronous clock PLCK has entered is not equal.

That is, in the EFM signal, the polarity inversion interval is changed from the maximum length component corresponding to 11T of the phase synchronization clock PLCK to the polarity inversion interval of the phase synchronization clock PCK.
There are nine types of components up to the minimum length component corresponding to 3T of LCK. Then, as shown in FIG. 9, the frequency of occurrence of each component is the largest for the component corresponding to 3T, and then decreases in the order of the components corresponding to 4T,..., 9T, 10T, and 11T. .

Here, ideally speaking, the EFM signal output from the data slice circuit 15 should contain only each of the nine types of components as shown by the dotted lines in FIG. Actually, the frequency of occurrence of each component is distributed in a skirt shape as shown by a solid curve in FIG. Therefore, a component corresponding to 10T of the phase synchronous clock PLCK and the phase synchronous clock PLCK
Both components are mixed with the component corresponding to 11T.

That is, by sequentially increasing the oscillation frequency of the VCO 18, 11T-0.5T of the phase synchronization clock PLCK is included in the polarity inversion interval of the EFM signal obtained from the data slice circuit 15. When the frequency detection circuit 22 drives the phase synchronization clock P
A component corresponding to 11T of LCK is erroneously determined to be a component corresponding to 10T of phase-locked clock PLCK, and FIG.
As shown by the diagonal lines in (c), the HiZ state may occur before entering the capture range shown in FIG.

Thus, the data reproducing PLL circuit is
If a user enters a dead zone which is not controlled by any of the phase comparison circuit 17 and the frequency detection circuit 22, the data cannot be removed unless there is disturbance such as uneven rotation of the disk 12 or noise mixed in the PLL system. It takes a long time for the circuit to be in the phase locked state, which hinders a high-speed search operation.

On the other hand, by sequentially lowering the oscillation frequency of the VCO 18, the phase synchronization clock P is set within the polarity inversion interval of the EFM signal obtained from the data slice circuit 15.
If the LCK is driven so as to include 11T + 0.5T, there is no component corresponding to 12T or more of the phase synchronization clock PLCK in the polarity inversion interval of the EFM signal, so that no erroneous judgment occurs. The state is switched to the HiZ state at substantially the same timing as the ideal state shown in FIG. 8B, and the PLL circuit for data reproduction is not controlled by any of the phase comparison circuit 17 and the frequency detection circuit 22.

[0027]

As described above, in the conventional data reproducing PLL circuit, V is determined based on the frequency detection result.
If the frequency of the CO is sequentially increased to drive into the capture range in the phase locked state based only on the phase comparison result, there is a dead zone that is not controlled by either the phase comparison result or the frequency detection result. However, there is a problem that it is difficult to escape when entering the dead zone, which hinders a high-speed search operation.

Therefore, the present invention has been made in view of the above circumstances, and contributes to speeding up the search operation by controlling so as not to enter a dead zone which is not controlled by any of the phase comparison result and the frequency detection result. Very good data reproduction PLL circuit control device and data reproduction
It aims to provide a raw system .

[0029]

A controller for a data reproducing PLL circuit according to the present invention compares the phase of digital data read from a recording medium with an oscillation signal output from an oscillating means, and compares the phase comparison result. And a phase comparator for generating a first control signal for controlling the oscillation frequency of the oscillator based on the phase difference between the digital data and the oscillation signal is out of a range where the phase can be compared by the phase comparator. Detecting a correspondence between a maximum polarity inversion period of digital data read from a recording medium and a count number of an oscillation signal obtained during the period, and controlling an oscillation frequency of an oscillation unit based on the detection result. (2) a detecting means for generating the control signal of (2), and a control means for controlling the oscillation frequency of the oscillating means to increase in accordance with the second control signal output from the detecting means. Control means for continuing the control of the oscillation frequency of the oscillating means by the second control signal, even if the phase difference between the total data and the oscillation signal is within a range in which the phase comparison means can compare the phases. It is configured to obtain a reference signal for performing digital data reproduction processing.

A data reproducing PLL according to the present invention
The circuit control device compares the phase of the digital data read from the recording medium with the oscillation signal output from the oscillation unit, and controls the oscillation frequency of the oscillation unit based on the phase comparison result. A phase comparison unit for generating a signal, and a minimum polarity inversion period of the digital data read from the recording medium in a state where the phase difference between the digital data and the oscillation signal is out of a range in which the phase comparison unit can compare the phases. Detecting means for detecting a correspondence relationship between the obtained oscillation signal and the count number, generating a second control signal for controlling the oscillation frequency of the oscillation means based on the detection result, and output from the detection means. The phase difference between the digital data and the oscillation signal can be compared by the phase comparison means in a state in which the oscillation frequency of the oscillation means is controlled to decrease based on the second control signal. Be within the range, and a control means for continuing the control of the oscillation frequency of the oscillation means according to a second control signal, and configured to obtain a reference signal for reproduction processing of the digital data from the oscillation means Tei You. Sa
Further, a control device for a data reproducing PLL circuit according to the present invention is provided.
The device is connected to digital data read from a recording
Comparing the phase with the oscillation signal output from the means.
Control the oscillation frequency of the oscillation means based on the comparison result
Phase comparing means for generating a first control signal, a digital
Phase difference between data and oscillation signal is compared by phase comparison means
The data read from the recording medium is out of the possible range.
The inversion period of digital data is measured with an oscillation signal, and the measurement result
For controlling the oscillation frequency of the oscillation means based on the result.
And a detecting means for generating a second control signal, the detection hand
Based on the second control signal output from the stage.
With the oscillation frequency controlled, digital data and
The phase difference between the oscillation signal and the phase
The oscillation means is activated by the second control signal even if it is within the box.
Control of the vibration frequency, and then the measurement result
The oscillation frequency of the oscillating means by the second control signal
It is configured to stop the control of the wave number. Also,
The data reproduction system according to the invention of
A pickup means for reading the data, the
Converts an output signal from the pickup means into an RF signal
Voltage conversion means and RF output from the voltage conversion means
A data slurry that generates digital data by binarizing a signal
A chair unit, a synchronous clock on the basis of the digital data
Oscillation means for generating, digital data and oscillation means
Phase comparison with the oscillation signal output from the
For controlling the oscillation frequency of the oscillation means based on the result.
Phase comparing means for generating a first control signal, the digital data
The phase difference between the data and the oscillation signal can be compared with the phase comparison means.
Digital data read from a recording medium while the
The inversion period of the data is measured by the oscillation signal, and the
A second means for controlling the oscillation frequency of the oscillation means based on
Detecting means for generating a control signal .
Oscillation of the oscillating means based on the second control signal output from the
Digital data and oscillation while the frequency is controlled
The phase difference with the signal is within the range where the phase can be compared by the phase comparison means.
However, the oscillation cycle of the oscillation means by the second control signal
Continue to control the wave number, and then the measurement result reaches the specified value
The oscillation frequency of the oscillating means by the second control signal
Is stopped.

[0031]

According to the above arrangement, the digital data and the oscillation signal are controlled in a state where the oscillation frequency of the oscillation means is controlled to increase or decrease based on the second control signal output from the detection means. Even if the phase difference between the data and the input signal falls within the range where the phase can be compared by the phase comparing means, the control of the oscillation frequency of the oscillating means by the second control signal is continued. There is no dead zone where the circuit is not controlled by either the phase comparing means or the detecting means, and the speed of the search operation can be increased.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a frequency detection circuit described in this embodiment. That is, the EFM signal output from the data slice circuit 15 is supplied to the counter 24 via the input terminal 23. The clock CK output from the VCO 18 is supplied to the counter 24 via an input terminal 25. The counter 24 counts the clock CK input between the time when the polarity of the EFM signal is inverted and the time when the next polarity is inverted.
The count value A output from the counter 24 is supplied to one input terminal of a comparison circuit 26.

The other input terminal of the comparison circuit 26 is supplied with the numerical value B output from the maximum length register 27. The comparison circuit 26 compares the count value A output from the counter 24 with the numerical value B output from the maximum length register 27, and outputs “1” when A> B.
When ≤B, "0" is output. The output of the comparison circuit 26 is added to the numerical value B output from the maximum length register 27 by the addition circuit 28 and set in the maximum length register 27. When a reset pulse RS is supplied to the input terminal 29, the output value B of the maximum length register 27 is reset to “0”.

Therefore, with the output value B of the maximum length register 27 reset to "0", the counter 23 outputs EF.
When the M signal and the clock CK are given, the maximum length register 2
The output numerical value B of 7 is sequentially incremented, becomes a value corresponding to the maximum polarity inversion interval of the EFM signal, and calms down.

The value B output from the maximum length register 27 is supplied to the window comparison circuit 30. The window comparison circuit 30 is configured as shown in FIG. That is, the numerical value B output from the maximum length register 27 is supplied to the comparison circuits 32 and 33 via the input terminal 31. The numerical value “21” and the numerical value “22” are supplied to the comparison circuit 32 through the input terminal 34, respectively. These numerical values “21”, “22”
Since the frequency dividing circuit 19 performs 1/2 frequency dividing,
When converted into the count value of the clock CK, the values correspond to the lengths of 11T-0.5T and 11T of the phase synchronous clock PLCK, respectively.

The comparison circuit 32 outputs its output for one detection time (the value B output from the maximum length register 27 is EFM).
When the output P of the delay circuit 35 for delaying (whenever the signal reaches the value corresponding to the maximum polarity inversion interval of the signal) is at the L level, the numerical value B output from the maximum length register 27 is compared with the numerical value "21", and B is compared. H level is output when ≦ 21, and B>
At the time of 21, the L level is output. The comparison circuit 3
2 compares the numerical value B output from the maximum length register 27 with the numerical value “22” when the output P of the delay circuit 35 is at the H level, outputs the H level when B ≦ 22, and outputs B> 2
When it is 2, the L level is output.

Therefore, when the numerical value B output from the maximum length register 27 is equal to or less than "21" as shown in FIG. 3A, that is, during the polarity inversion interval of the EFM signal, the phase synchronization clock PLCK When 11T-0.5T does not enter, both the outputs of the comparison circuit 32 and the delay circuit 35 become H level, so that the comparison circuit 32 keeps outputting H level until the numerical value B becomes "22". Will be. At this time, the H level output of the comparison circuit 32 controls the switch 37 to the ON state via the drive circuit 36, whereby an H level output is generated from the output terminal 38,
The CO 18 is controlled to increase its oscillation frequency.

That is, in the frequency detection circuit described in this embodiment, the value B output from the maximum length register 27 exceeds "21", and the capture range is controlled only by the phase comparison circuit 17 shown in FIG. (C), the control for increasing the oscillation frequency of the VCO 18 is continuously performed, and when the value B becomes "23", the comparison circuit 32 inverts to L level and the switch 37 Is turned off, and the control for increasing the oscillation frequency of the VCO 18 is stopped. Since the output of the comparison circuit 32 is inverted to the L level, the output P of the delay circuit 35 is at the L level in the next comparison operation of the comparison circuit 32. 21 ".

On the other hand, the comparison circuit 33 has an input terminal 3
The number "23" is supplied via 9. This value "23" is a value corresponding to the length of 11T + 0.5T of the phase synchronous clock PLCK when converted to the count value of the clock CK since the frequency dividing circuit 19 performs the 周 frequency division. ing. The comparison circuit 33 compares the numerical value B output from the maximum length register 27 with the numerical value “23”, outputs an H level when B ≧ 23, and outputs B <23.
In this case, the L level is output.

Therefore, when the value B output from the maximum length register 27 is "23" or more as shown in FIG. 3A, that is, during the polarity inversion interval of the EFM signal, the phase synchronization clock PLCK In the state where 11T + 0.5T or more is present, the output of the comparison circuit 33 becomes H level. Therefore, the comparison circuit 33 operates until the numerical value B becomes “23” as shown in FIG. H level output will be continued. The H level output of the comparison circuit 33 at this time controls the switch 41 to the on state via the drive circuit 40,
As a result, an L-level output is generated from the output terminal 38, and the VCO 18 is controlled to lower its oscillation frequency. Then, when the numerical value B becomes "23", the comparison circuit 32 inverts to the L level, turns off the switch 41, and operates to stop the control for lowering the oscillation frequency of the VCO 18.

Therefore, according to the configuration as in the above embodiment, by sequentially increasing the oscillation frequency of the VCO 18,
During the polarity inversion interval of the EFM signal obtained from the data slice circuit 15, the phase synchronization clock PLCK 11
If you drive in so that there is T-0.5T,
The control for increasing the oscillation frequency of the VCO 18 is continuously performed even if the value is within the capture range controlled by only the phase comparison circuit 17 shown in FIG.
Phase synchronization clock PLC during polarity inversion interval of FM signal
When 11T + 0.5T of K comes in, V
Since the control for increasing the oscillation frequency of the CO 18 is stopped, there is no dead zone where the data reproducing PLL circuit is not controlled by any of the phase comparison circuit 17 and the frequency detection circuit 22 as in the related art. Can be speeded up.

In the above-described embodiment, the 11T + of the phase synchronization clock PLCK is set during the polarity inversion interval of the EFM signal.
The control for increasing the oscillating frequency of the VCO 18 is stopped when the time of 0.5 T has entered.
The timing at which the control for increasing the oscillation frequency of the control signal 18 is stopped is, for example, when the value B becomes “22”, that is, when EF
Phase synchronization clock PLCK during the polarity inversion interval of M signal
The dead zone can be eliminated and the same effect as described above can be obtained even if the setting is made when 11T is inserted.

In short, in a state where the oscillation frequency of the VCO 18 is controlled to be sequentially increased, the numerical value B becomes "21".
That is, 11T-0.5T of the phase synchronization clock PLCK is included in the polarity inversion interval of the EFM signal, and the capture range is controlled only by the phase comparison circuit 17 shown in FIG. Even inside, VCO1
The control for increasing the oscillation frequency of No. 8 is continuously performed, and the value B
If the control for increasing the oscillation frequency of the VCO 18 is stopped when the value becomes equal to or more than "22", the dead zone can be eliminated.

Next, in the frequency detection circuit described in the above embodiment, the oscillation frequency of the VCO 18 is adjusted so that 11T ± 0.5T of the phase synchronization clock PLCK is inserted within the maximum polarity inversion interval of the EFM signal. The description has been given of the case in which the PLL circuit for data reproduction is quickly brought into the phase locked state by controlling. However, the present invention is not limited to this, and 3T ± of the phase synchronization clock PLCK is set within the minimum polarity inversion interval of the EFM signal.
Even if the oscillation frequency of the VCO 18 is controlled so that 0.5 T is inserted, the data reproduction PLL circuit can be quickly brought into the phase locked state.

In the frequency detection circuit of the type in which the minimum polarity inversion interval of the EFM signal is detected and the oscillation frequency of the VCO 18 is controlled, the oscillation frequency of the VCO 18 is sequentially lowered to obtain the data from the data slice circuit 15. When 3T + 0.5T of the phase synchronization clock PLCK is inserted into the polarity inversion interval of the EFM signal, the dead zone is set before the phase shift circuit 17 enters the capture range controlled by the phase comparison circuit 17 alone. Will exist.

FIG. 4 shows EF based on the above idea.
Second Embodiment A second embodiment in which the present invention is applied to a frequency detection circuit for detecting the minimum polarity inversion interval of the M signal is shown. That is, the EFM signal output from the data slice circuit 15 is supplied to the counter 43 via the input terminal 42.
Supplied to This counter 43 is supplied with a clock CK output from the VCO 18 via an input terminal 44. The counter 43 counts the clock CK input between the time when the polarity of the EFM signal is inverted and the time when the next polarity is inverted. The count value C output from the counter 43 is supplied to one input terminal of the comparison circuit 45.

A numerical value D output from the minimum length register 46 is supplied to the other input terminal of the comparison circuit 45. The comparison circuit 45 compares the count value C output from the counter 43 with the numerical value D output from the minimum length register 46, and outputs “−1” when C> D,
When C ≦ D, “0” is output. The output of the comparison circuit 45 is added to the numerical value D output from the minimum length register 46 by the addition circuit 47 and set in the minimum length register 46. When the preset pulse PR is supplied to the input terminal 48, the output value D of the minimum length register 46 is preset to "22" (the number of clocks CK corresponding to the maximum polarity inversion interval of the EFM signal).

Therefore, when the output value D of the minimum length register 46 is preset to "22" and the EFM signal and the clock CK are applied to the counter 43, the output value D of the minimum length register 46 is sequentially decremented. EFM
A value corresponding to the minimum polarity inversion interval of the signal is settled.

Then, the numerical value D output from the minimum length register 46 is supplied to the window comparison circuit 49. This window comparison circuit 49 is configured as shown in FIG. That is, the numerical value D output from the minimum length register 46 is supplied to the comparison circuits 51 and 52 via the input terminal 50, respectively. The numerical value “6” and the numerical value “7” are supplied to the comparison circuit 52 via the input terminal 53, respectively. These numerical values “6” and “7” are converted to the count value of the clock CK, since the frequency dividing circuit 19 performs the frequency division by ２, so that the phase synchronous clock PL
The values correspond to the length of 3T of CK and the length of 3T + 0.5T, respectively.

The comparison circuit 52 outputs the output for one detection time (the numerical value D output from the minimum length register 46 is EFM).
When the output Q of the delay circuit 54 for delaying (whenever the signal reaches the value corresponding to the minimum polarity inversion interval of the signal) is at the L level, the numerical value D output from the minimum length register 27 is compared with the numerical value "7", and An H level is output when ≧ 7, and an L level is output when D <7. When the output Q of the delay circuit 54 is at the H level, the comparison circuit 52
Compare the numerical value D output from 6 with the numerical value “6” in magnitude,
An H level is output when D ≧ 6, and an L level is output when D <6.

For this reason, when the numerical value D output from the minimum length register 46 is "7" or more as shown in FIG. 6A, that is, during the polarity inversion interval of the EFM signal, the phase synchronization clock PLCK When 3T + 0.5T or more is in the state, the outputs of the comparison circuit 52 and the delay circuit 54 both become H level, so that the comparison circuit 52 continues to output H level until the numerical value D becomes “6”. Will be.
At this time, the H level output of the comparison circuit 52 is
5, the switch 56 is controlled to the ON state, whereby an L-level output is generated from the output terminal 57 and the VCO
Reference numeral 18 is controlled so as to lower the oscillation frequency.

That is, in the frequency detection circuit described in the second embodiment, the numerical value D output from the minimum length register 46 becomes "7", and the phase comparison circuit 1 shown in FIG.
Even if you are within the capture range with only 7 controls,
As shown in FIG. 3C, the control for lowering the oscillation frequency of the VCO 18 is continuously performed, and when the numerical value D becomes "5", the comparison circuit 52 inverts to the L level to turn off the switch 56, It operates to stop the control for lowering the oscillation frequency of the VCO 18. Since the output of the delay circuit 54 is at the L level in the next comparison operation of the comparison circuit 52 due to the inversion of the output of the comparison circuit 52 to the L level, the comparison circuit 52 outputs the numerical value D and the numerical value “ 7 "will be compared in magnitude.

On the other hand, the comparison circuit 51 has an input terminal 5
The numerical value “5” is supplied via 8. The value "5" is a value corresponding to the length of 3T-0.5T of the phase synchronous clock PLCK when converted to the count value of the clock CK since the frequency dividing circuit 19 performs the 1/2 frequency division. It has become. The comparison circuit 51 compares the numerical value D output from the minimum length register 46 with the numerical value “5”, and outputs an H level when D <5, and outputs an L level when D ≧ 5.

Therefore, when the numerical value D output from the minimum length register 46 is less than "5" as shown in FIG. 6A, that is, during the polarity inversion interval of the EFM signal, the phase synchronization clock PLCK When 3T-0.5T is not entered, the output of the comparison circuit 51 goes to the H level, so that the comparison circuit 51 keeps the H level until the numerical value D becomes "5" as shown in FIG. Level output will be continued.
At this time, the H level output of the comparison circuit 51 is
9 to control the switch 60 to an on state, whereby an H-level output is generated from the output terminal 57 and the VCO
18 is controlled so as to increase its oscillation frequency. Then, when the numerical value D becomes "5", the output of the comparison circuit 51 is inverted to L level to turn off the switch 60,
The operation for increasing the oscillation frequency of the CO 18 is stopped.

Therefore, according to the configuration of the second embodiment, the EFM obtained from the data slice circuit 15 is obtained by sequentially lowering the oscillation frequency of the VCO 18.
In the signal polarity inversion interval, the phase synchronization clock PLCK
6T, the control for lowering the oscillating frequency of the VCO 18 is continuously performed even if it is within the capture range controlled by only the phase comparison circuit 17 shown in FIG. 6B. When the value D is "5", that is, during the polarity inversion interval of the EFM signal, the phase synchronization clock PL
When 3T-0.5T of CK comes in, V
Since the control for lowering the oscillation frequency of the CO 18 is stopped, there is no dead zone where the data reproducing PLL circuit is not controlled by any of the phase comparison circuit 17 and the frequency detection circuit 22 as in the related art. Can be speeded up.

In the second embodiment, the 3T of the phase synchronous clock PLCK is included in the polarity inversion interval of the EFM signal.
When −0.5T is inserted, the control for lowering the oscillation frequency of the VCO 18 is stopped.
The timing for stopping the control for lowering the oscillation frequency of the CO 18 is, for example, when the value D becomes “6”, that is, during the polarity inversion interval of the EFM signal.
Even if you set it when 3T of CK comes in,
The dead zone can be eliminated, and the same effect as described above can be obtained.

In short, even when the numerical value D becomes "7" in a state where the oscillation frequency of the VCO 18 is controlled to be sequentially lowered, that is, during the polarity inversion interval of the EFM signal, 3T + 0. 6T, the control for lowering the oscillating frequency of the VCO 18 is continued even if the value falls within the capture range controlled by only the phase comparator 17 shown in FIG. When the control for lowering the oscillation frequency of the VCO 18 is stopped when the voltage becomes 6 "or less, the dead zone can be eliminated. It should be noted that the present invention is not limited to the above embodiments, and can be variously modified and implemented without departing from the scope of the invention.

[0058]

As described in detail above, according to the present invention,
An extremely good data reproduction PLL circuit control device and data reproduction system that controls so as not to enter a dead zone that is not controlled by either the phase comparison result or the frequency detection result, thereby contributing to speeding up the search operation. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a window comparison circuit in the embodiment.

FIG. 3 is a view for explaining the operation of the embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing details of a window comparison circuit in the second embodiment.

FIG. 6 is a view for explaining the operation of the second embodiment.

FIG. 7 is a block diagram showing a conventional data reproducing PLL circuit.

FIG. 8 is a diagram shown to explain the operation of the conventional circuit.

FIG. 9 is a distribution diagram showing a relationship between a data length and an output frequency of an EFM signal.

[Explanation of symbols]

11 disk motor, 12 disk, 13 optical pickup, 14 current-voltage conversion circuit, 15 data slice circuit, 16 reproduction processing circuit, 17 phase comparison circuit, 18 VCO, 19 frequency divider circuit, 20 ... addition circuit,
21 LPF circuit, 22 frequency detection circuit, 23 input terminal, 24 counter, 25 input terminal, 26 comparison circuit, 27 maximum length register, 28 addition circuit, 29 input terminal, 30 window comparison Circuit, 31 input terminals, 3
2, 33: comparison circuit, 34: input terminal, 35: delay circuit, 36: drive circuit, 37: switch, 38: output terminal, 39: input terminal, 40: drive circuit, 41: switch, 42: input terminal, 43 counter, 44 input terminal, 45 comparison circuit, 46 minimum length register, 47 addition circuit, 48 input terminal, 49 window comparison circuit, 5
0 ... input terminal, 51, 52 ... comparison circuit, 53 ... input terminal, 54 ... delay circuit, 55 ... drive circuit, 56 ... switch, 57 ... output terminal, 58 ... input terminal, 59 ... drive circuit, 60 ... switch.

Claims (4)

(57) [Claims] 1. A phase comparison between digital data read from a recording medium and an oscillation signal output from an oscillating means,
A phase comparison means for generating a first control signal for controlling an oscillation frequency of the oscillation means based on the phase comparison result; and a phase difference between the digital data and the oscillation signal can be compared by the phase comparison means. In a state outside the range, the correspondence between the maximum polarity inversion period of the digital data read from the recording medium and the count number of the oscillation signal obtained within the period is detected, and the oscillation is performed based on the detection result. Detecting means for generating a second control signal for controlling the oscillating frequency of the means; and controlling the oscillating means to increase the oscillating frequency based on the second control signal output from the detecting means. In this state, even if the phase difference between the digital data and the oscillation signal falls within a range in which the phase can be compared by the phase comparison means, the oscillation frequency of the oscillation means by the second control signal is high. Control means for continuing the control of the number, and a control signal for a PLL circuit for data reproduction characterized by obtaining a reference signal for performing reproduction processing of the digital data from the oscillation means. . 2. A phase comparison between digital data read from a recording medium and an oscillation signal output from an oscillating means,
A phase comparison means for generating a first control signal for controlling an oscillation frequency of the oscillation means based on the phase comparison result; and a phase difference between the digital data and the oscillation signal can be compared by the phase comparison means. In a state outside the above range, the correspondence between the minimum polarity inversion period of the digital data read from the recording medium and the count number of the oscillation signal obtained within the period is detected, and the oscillation is performed based on the detection result. Detecting means for generating a second control signal for controlling the oscillating frequency of the means; and controlling the oscillating means to lower the oscillating frequency based on the second control signal output from the detecting means. In this state, even if the phase difference between the digital data and the oscillation signal falls within a range in which the phase can be compared by the phase comparison means, the oscillation frequency of the oscillation means by the second control signal is high. Control means for continuing the control of the number, and a control signal for a PLL circuit for data reproduction characterized by obtaining a reference signal for performing reproduction processing of the digital data from the oscillation means. . 3. Digital data read from a recording medium.
Phase comparison between the oscillator and the oscillation signal output from the oscillation means,
The oscillating frequency of the oscillating means is determined based on the phase comparison result.
Phase comparison means for generating a first control signal for controlling
And the phase difference between the digital data and the oscillation signal is the phase ratio
In a state where the phase is outside the range in which the phase
The inversion period of the digital data read from the medium is generated as described above.
Vibration signal, and based on the measurement result,
Generate a second control signal for controlling the oscillation frequency
Detecting means , based on a second control signal output from the detecting means.
In the state where the oscillation frequency of the oscillation means is controlled,
The phase difference between the digital data and the oscillation signal is
The second means, even though the phase
Continue to control the oscillation frequency of the oscillation means by the control signal
Then, when the measurement result reaches a predetermined value,
The oscillation frequency of the oscillation means is controlled by the second control signal.
PLL for data reproduction characterized by stopping control
Road control device. 4. Reading data recorded on a recording medium.
Means for converting the output signal from the pickup means into an RF signal
Voltage converting means, and an output from the voltage converting means.
Data that generates digital data by binarizing RF signals
Slicing means for generating a synchronous clock based on the digital data
Means for oscillating, and an oscillating signal output from the digital data and oscillating means
Are compared with each other, and based on the result of the phase comparison, the oscillation
Generates the first control signal for controlling the oscillation frequency of the stage
Phase comparing means, and the phase difference between the digital data and the oscillation signal is the phase ratio.
In a state where the phase is outside the range in which the phase
The inversion period of the digital data read from the medium is generated as described above.
Vibration signal, and based on the measurement result,
Generate a second control signal for controlling the oscillation frequency
Detecting means , based on a second control signal output from the detecting means.
In a state where the oscillation frequency of said oscillating means is controlled, before
The phase difference between the digital data and the oscillation signal is
The second means, even though the phase
Continue to control the oscillation frequency of the oscillation means by the control signal
Then, when the measurement result reaches a predetermined value,
The oscillation frequency of the oscillation means is controlled by the second control signal.
A data reproduction system characterized by stopping control.