JPH07111048A - Digital disk reproducing device - Google Patents

Abstract

PURPOSE:To shorten access time by performing a CAV-driving to a disk in a digital disk reproducing device. CONSTITUTION:A CD-ROM disk 11 is rotated at constant speed by a driving circuit 13 and a spindle motor 12. An RF amplifier 16 generates a generative EFM signal by being supplied with a signal from an optical pickup 14. A PLL circuit 17 extracts a synchronizing clock signal and a synchronized regenerative data signal from the regenerative EFM signal. A VCO 19 generates a reference clock for the PLL circuit 17. A rough adjustment circuit 18 controls the center frequency of the VCO 19 so as to coincide with the clock frequency of the regenerative EFM signal based on the regenerative EFM signal and the reference clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital disk player, and more particularly to a CD-ROM player.

[0002]

2. Description of the Related Art In general, an optical disc called a CD-ROM has a digital signal (data) as an EFM (Eight) like an audio CD (compact disc).
t to Fourteen Modulation)
It is recorded by a modulation method called. Also, CD-R
In the OM, the time of a unit bit and a unit frame and the recording length on the disc are the same on the inner and outer circumferences of the disc.

Therefore, in the conventional CD-ROM reproducing apparatus, the rotational speed of the disc is changed according to the position of the optical pickup in the disc radial direction. That is, the disc
The optical pickup scans at a constant linear velocity (CLV).

[0004]

In the conventional CD-ROM reproducing apparatus, an arbitrary address on the disc is searched for,
When reproducing, the rotation speed of the disk must be controlled to a speed corresponding to the position of the optical pickup in the disk radial direction. The time required for a spindle motor that rotates a disk to transition from one rotational speed state to another is relatively long. Therefore, the conventional device inevitably has a problem that the access time becomes long.

Further, the spindle motor control circuit (CLV control circuit) for changing the rotation speed of the spindle motor according to the position of the pickup in the radial direction of the disk is complicated and there is a problem that the cost becomes high.

The present invention has been made in view of the above points, and it is possible to shorten the access time at the time of reproducing a disk recorded by the CLV system, and to reproduce the digital disk by simplifying the control circuit of the spindle motor. An object is to provide a reproducing device.

[0007]

DISCLOSURE OF THE INVENTION The present invention is a digital disc reproducing apparatus for producing a reproduction data signal by reading the digital signal from a digital disc on which a digital signal containing clock information is recorded in a constant linear velocity format. Disk drive means for rotating the digital disk at a constant speed, a digital signal reproducing circuit which is supplied with a signal from the pickup to generate a reproduced digital signal, and a clock generated from the reproduced digital signal supplied from the digital signal reproducing circuit. A signal extracting circuit for extracting a signal and a reproduced data signal, a variable frequency oscillator for generating a reference clock signal of the signal extracting circuit and supplying the signal to the signal extracting circuit, a reproduced digital signal from the digital signal reproducing circuit, and Based on the reference clock signal , A configuration and a frequency control circuit for controlling the center frequency of the variable frequency oscillator so as to match the clock frequency of the reproduced digital signal.

[0008]

In the present invention, the digital disk recorded in the constant linear velocity format is rotated at a constant speed, and the clock frequency of the signal read by the pickup changes. The frequency control circuit controls the center frequency of the variable frequency oscillator to match the clock frequency of the reproduced digital signal based on the reproduced digital signal from the digital signal reproducing circuit and the reference clock signal of the variable frequency oscillator. As a result, the signal extraction circuit correctly extracts the clock signal and the reproduction data signal from the reproduction digital signal using the reference clock.

Therefore, according to the present invention, since the spindle motor can rotate at a constant speed, the access time can be shortened, and the rotation control circuit of the spindle motor can be simplified to reduce the cost. Further, since high torque is not required for the spindle motor, it is possible to reduce the power consumption of the device.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the entire structure of a CD-ROM reproducing apparatus according to an embodiment of the present invention. On a CD-ROM disc (hereinafter referred to as a disc) 11, digital signals are recorded by the EFM system. The recording length of the unit bit and the unit frame of the digital signal in the track of the disk 11 is the same in all areas of the disk 11. That is, the data is always transferred at a constant speed by reproducing the disk 11 by the CLV method. Since the bit lengths are the same, the EFM digital signal contains clock information.

The spindle motor 12 for rotating the disk 11 is always rotated at a constant rotation speed by the drive circuit 13. That is, the spindle motor 12 moves the disk 11 to the C position regardless of the position of the optical pickup 14 in the radial direction.
AV drive.

The optical pickup 14 irradiates the disk 11 with a laser beam and detects the reflected light to read the recorded digital signal of the disk 11. The pickup controller 15 controls the seek operation of the optical pickup 14, tracking, focusing, and the like. The reproduced signal from the optical pickup 14 is amplified by the RF amplifier 16 (digital signal reproducing circuit), subjected to waveform shaping processing, and output as a reproduced digital signal (EFM digital signal).

The PLL circuit 17 (signal extraction circuit) is an RF circuit.
The synchronous clock and the synchronous reproduction data are extracted from the reproduced digital signal supplied from the amplifier 16. A VCO (voltage controlled oscillator) 19 generates a reference clock for the PLL circuit 17 and supplies it to the PLL circuit 17 and the coarse adjustment circuit 18.

The coarse adjustment circuit 18 (frequency control circuit) has a P
In order to assist the lock operation of the LL circuit 17, based on the reproduced digital signal supplied from the RF amplifier 16,
The center frequency of the reference clock of the VCO 19 is controlled to match the clock frequency of the reproduced digital signal. V
When the center frequency tuning operation of CO19 is completed,
The coarse adjustment circuit 18 gives a command to the PLL circuit 17 to turn on the lock. Upon receiving the lock-on command from the coarse adjustment circuit 18, the PLL circuit 17 controls the VCO 19 so that the oscillation frequency of the VCO 19 exactly matches the clock frequency of the reproduced digital signal.

The EFM demodulation circuit 20 is supplied with the synchronous clock and the synchronous reproduction data from the PLL circuit 17 and receives the EFM.
Demodulate and generate demodulated data.

As described above, the spindle motor 12 is
It does not require high torque because it only needs to rotate at a constant speed. Therefore, the power consumption of the device can be reduced.

FIG. 2 shows a block diagram of the coarse adjustment circuit together with the VCO 19. The coarse adjustment circuit 18 includes a pulse width detector 25a,
25b, OR circuits 41 to 44, a pulse width determination unit 50, and a control signal generation unit 55.

FIG. 3 shows an explanatory diagram of the EFM signal. The reproduced EFM signal generated from the RF amplifier 16 includes a frame synchronization signal for each frame. When the period of the clock signal of the EFM signal is T ₀ , the pulse width of this frame synchronization signal is 22T ₀ as shown in FIG.

The disk 11 recorded by the CLV system is recorded on the C
When reproduced by the LV system, the cycle T _{0 of the} clock signal
Is constant, and the frame synchronization signal appears as a pulse having a constant time width.

In this embodiment, the disk 11 recorded by the CLV system is reproduced by the CAV system. Therefore, the clock frequency of the reproduced EFM signal is low at the inner circumference and high at the outer circumference of the disk 11. Therefore, in the inner circumference of the disk 11, the period in which the frame synchronization signal appears becomes longer and the pulse width 22T ₀ of the frame synchronization signal becomes longer. In the outer circumference of the disk 11, the cycle of the frame synchronization signal becomes shorter and the frame synchronization signal becomes shorter. Signal pulse width 22
T ₀ becomes shorter.

The coarse adjustment circuit 18 of the present embodiment detects the pulse width of the frame sync signal in the EFM signal and adjusts the pulse width of the frame sync signal to the VCO 19 for 22 cycles of the reference clock. Control the center frequency of. As a result, the center frequency of the VCO 19 is adjusted to the clock frequency of the reproduced EFM signal.

Reproduction EFM supplied from the RF amplifier 16
The frame synchronization signal in the signal includes one that starts at an up edge and one that starts at a down edge. The pulse width detection unit 25a is a circuit for detecting the pulse width of the frame synchronization signal starting at the rising edge, and the pulse width detection unit 25a
Reference numeral b is a circuit for detecting the pulse width of the frame synchronization signal starting at the down edge.

The pulse width detection section 25a comprises a counter reset circuit 26, a counter 27, and a pulse width detection circuit 28. The counter reset circuit 26 includes a T flip-flop (T-FF) 31, a delay circuit 32, and an EX-OR circuit 33.

Reproduction EFM supplied from the RF amplifier 16
The pulse width of the frame synchronization signal in the signal is 22 cycles of the clock signal (22T ₀ ), but in reality, it is 11T _0.
It consists of two positive and negative pulses. Therefore, as described below, in order to correctly detect the pulse width of the frame synchronization signal, with respect to the signal obtained by dividing the EFM signal by 1/2,
The counter 27 counts the number of reference clocks of the VCO 19 for each pulse width.

The T-FF 31 generates a signal obtained by dividing the EFM signal by 1/2 in synchronization with the rising edge of the EFM signal. The delay circuit 32 and the EX-OR circuit 33 generate a counter reset signal synchronized with the up edge and the down edge of the signal obtained by dividing the EFM signal by 1/2. Each time the counter 27 is reset by the counter reset signal, it starts counting the reference clock of the VCO 19 and counts each pulse width of the signal obtained by dividing the EFM signal by 1/2. For the frame sync signal, the pulse width of the frame sync signal starting at the rising edge of the EFM signal is counted.

The count value of the counter 27 is supplied to the 11T detection circuit 35, the 22T detection circuit 36, the 23T detection circuit 37, and the 44T detection circuit 38 which form the pulse width detection circuit 28.

The 11T detection circuit 35 outputs an H level signal (11T detection signal) when the count value of the counter 27 becomes 11 or more. The 22T detection circuit 36 uses the counter 27
When the count value of is 22 or more, an H level signal (22T detection signal) is output. The 23T detection circuit 37 outputs an H level signal (23
T detection signal) is output. The 44T detection circuit 38 outputs an H level signal (44T detection signal) when the count value of the counter 27 becomes 44 or more.

In the 11T detection signal, the counted pulse width is a reference value (1
1T) or more. Similarly, the 22T detection signal, the 23T detection signal, and the 44T detection signal indicate that the counted pulse widths are equal to or larger than the respective reference values (22T, 23T, 44T).

11T detection circuit 35, 22T detection circuit 3
From the combination of the output signals of the 6, 23T detection circuit 37 and the 44T detection circuit 38, it is possible to determine which range of 11T to 44T the pulse width counted by the counter 27 is.
The frame synchronization signal has the longest pulse width in the EFM signal. Therefore, with respect to the pulse width count value of the frame synchronization signal, the 11T detection circuit 35, 22T detection circuit 36, 23
The combination of the output signals of the T detection circuits 37 and 44T detection circuit 38 shows the longest pulse width in the frame.

The 11T detection circuit 35, the 22T detection circuit 36, the 23T detection circuit 37, and the 44T detection circuit 38 are
An H-level signal with a short pulse width is generated as the detection signal.

The pulse width detector 25b is similar to the pulse width detector 25a except that it counts the pulse width of the frame sync signal starting at the down edge of the EFM signal.
The EF from the RF amplifier 16 is used to count the pulse width of the frame sync signal starting at the down edge of the EFM signal.
The M signal is supplied to the counter reset circuit 26 via the inverter circuit 39.

11T detection circuit 3 of pulse width detection section 25a
5, 22T detection circuit 36, 23T detection circuit 37, 44T
The output signals of the detection circuit 38 and the output signals of the 11T detection circuit 35, 22T detection circuit 36, 23T detection circuit 37, 44T detection circuit 38 of the pulse width detection unit 25b are ORed.
The logical sum is obtained by the circuits 41 to 44, and the pulse width determination unit 5
0T 11T confirmation circuit 51, 22T confirmation circuit 52, 23T
The confirmation circuits 53 and 44T are supplied to the confirmation circuit 54, respectively.

The 1/588 frequency dividing circuit 45 divides the reference clock by 1/588 to generate a detection frame pulse. This detection frame pulse indicates the beginning of a pulse detection frame having a length of 588 reference clocks. Further, the 1/16 frequency divider circuit 46 detects the detection frame pulse by 1
The frequency is divided by 16 to generate a definite frame pulse for every 16 pulse detection frames.

The 11T confirmation circuit 51 detects 11T from the pulse width detection section 25a or the pulse width detection section 25b in 16 consecutive pulse detection frames (1 confirmation frame).
When the detection signal is continuously supplied, the H level becomes 11
The T confirmation signal is output. The 22T confirmation circuit 52 outputs a 22T confirmation signal of H level when the 22T detection signal is continuously supplied from the pulse width detection unit 25a or the pulse width detection unit 25b in 16 consecutive pulse detection frames. . The 23T confirmation circuit 53 uses the pulse width detection unit 25a in 16 consecutive pulse detection frames,
Alternatively, when the 23T detection signal is continuously supplied from the pulse width detection unit 25b, the H level 23T confirmation signal is output. The 44T confirmation circuit 54 outputs an H-level 44T confirmation signal when a 44T detection signal is continuously supplied from the pulse width detection unit 25a or the pulse width detection unit 25b in 16 consecutive pulse detection frames. .

11T confirmation signal, 22T confirmation signal, 23T
The confirmation signal and the 44T confirmation signal are surely 11T,
It indicates that a frame synchronization signal having a pulse width of 22T, 23T, 44T or more is detected. In succession with 16 pulse detection frames, 11T detection signal, 22T detection signal,
Only when the 23T detection signal and the 44T detection signal are supplied, the 11T confirmation signal, the 22T confirmation signal, the 23T confirmation signal, and the 44T confirmation signal are generated to prevent erroneous determination of the pulse width due to the influence of noise or the like. .

The output signal of the 11T determining circuit 51 is inverted by the inverter circuit 62 of the control signal generating section 55 to obtain VC
It is supplied to O19. When the H level 11T confirmation signal is not generated, this signal is supplied to the VCO 19 as an H level frequency double command. When the frequency double command is supplied, the VCO 19 sets the current center frequency to double.

The output signals of the 22T determining circuit 52 and the 23T determining circuit 53 are output to the inverter circuits 59 and 60, respectively.
The AND circuit 61 calculates the logical sum of the respective inverted signals and supplies the logical sum to the VCO 19. When neither the 22T confirmation signal nor the 23T confirmation signal is generated, this signal is supplied to the VCO 19 as an H level frequency increasing command. The VCO 19 raises the current center frequency when the frequency increase command is supplied.

The output signal of the 22T determining circuit 52 and the output signal of the 23T determining circuit 53 are logically ORed by the AND circuit 58 and supplied to the VCO 19. 22T
When both the confirmation signal and the 23T confirmation signal are generated, this signal is VC as an H level frequency lowering command.
It is supplied to O19. The VCO 19 lowers the current center frequency when the frequency lowering command is supplied.

The output signal of the 44T determination circuit 54 is VCO.
19 are supplied. When an H-level 44T confirmation signal is generated, this signal is used as a frequency half command.
19 are supplied. The VCO 19 reduces the current center frequency by half when the frequency half command is supplied.

By the inverter circuit 56 and the AND circuit 57, the output signal of the 22T determining circuit 52 and the 23T determining circuit 5
The inversion signal of the output signal of 3 is ORed, and the PLL
It is supplied to the PLL circuit 17 as an ON / OFF signal.
The PLL ON / OFF signal becomes an H-level PLL ON signal when the 22T confirmation signal is generated and the 23T confirmation signal is not generated.

Upon receiving the frequency double command, frequency increase command, frequency decrease command and frequency half command generated by the control signal generation unit 55 based on the signal from the pulse width determination unit 50, V
The CO 19 can adjust the center frequency to the clock frequency of the EFM signal in a short time. When the center frequency of the VCO 19 is adjusted to the clock frequency of the EFM signal, the PLL ON signal is supplied to the PLL circuit 17. As a result, the PLL circuit 17 controls the VCO 19 so that the frequency of the VCO 19 matches the clock frequency of the EFM signal.

When the disk 11 is driven by CAV, the clock frequency of the EFM signal and the frequency of the reference clock of the VCO 19 may be significantly different from each other during the seek operation of the optical pickup 15. In the present embodiment, as described above, the coarse adjustment circuit 18 detects the pulse width of the frame synchronization signal, and the frequency control command corresponding to this frequency shift causes
The frequency of the VCO 19 can be controlled to a frequency at which the PLL circuit 17 can be locked. Therefore, even if the clock frequency of the EFM signal and the frequency of the reference clock of the VCO 19 are significantly deviated, the center frequency of the VCO 19 is correctly controlled in a short time, and the PLL
The lock operation of the circuit 17 can be enabled.

11T determining circuit 51, 22T determining circuit 5
The 2,23T determining circuit 53 and the 44T determining circuit 54 are all configured by the same circuit. FIG. 4 shows the 11T confirmation circuit 51,
The circuit diagram of an example of the 22T confirmation circuit 52, the 23T confirmation circuit 53, and the 44T confirmation circuit 54 is shown. 5 (A) to 5 (J) are timing charts of the signals of the respective parts in FIG. 4 when the confirmation signal is not generated, and FIGS.
(J) shows a timing chart of the signals of the respective parts in FIG. 4 when the confirmation signal is generated. Here, the case of the 23T confirmation circuit 53 will be described.

The detection frame pulse a (negative pulse) indicating the head of the pulse detection frame is the 1/588 frequency dividing circuit 45.
Supplied from The 1/16 frequency divider circuit 46 frequency-divides the detection frame pulse a by 1/16 to generate a definite frame pulse h (negative pulse) for every 16 pulse detection frames.

When the frequency of the reference clock of the VCO 19 matches the clock frequency of the reproduced EFM signal, the time width of the pulse detection frame and the time width of the frame of the reproduced EFM signal match.

The output signal of the 23T detection circuit 37 is supplied to the set terminal S of the SR flip-flop (SR-FF) 71 as the signal b via the OR circuit 43. SR
A pulse obtained by inverting the detection frame pulse a is supplied to the reset terminal R of the -FF 71. SR-FF71 is
When the 23T detection signal of H level is supplied to the set terminal S after the signal c of the output terminal Q becomes L level after being reset at the trailing edge of the detection frame pulse a (the beginning of the pulse detection frame), the output terminal The signal c of Q maintains the H level until the next detection frame pulse a comes.

The output signal c of the SR-FF 71 is slightly delayed by the delay circuit 73 and supplied to the D terminal of the D flip-flop (D-FF) 74 as the signal d.
A pulse obtained by inverting the detection frame pulse a is supplied to the clock terminal CK of the D-FF 74. D-FF74
Outputs a signal d from the output terminal Q as a signal d latched at the trailing edge of the detection frame pulse a (the beginning of the pulse detection frame). Therefore, when the 23T detection signal is generated in the immediately preceding pulse detection frame, the output signal e of the D-FF 74 becomes H level at the falling edge of the detection frame pulse a and remains at H level until the next detection frame pulse a.
Hold the level.

The D-FF 76 has a D input terminal connected to the D-FF.
74 output signal e and D-FF 76 Q output terminal signal j
A signal f obtained by ANDing the logical product of and is supplied. Further, the clock terminal CK of the D-FF 76 is supplied with the pulse g obtained by inverting the detection frame pulse a and then delaying it with the delay circuit 78. Further, the set terminal S of the D-FF 76 is supplied with a pulse i obtained by inverting the definite frame pulse h (negative pulse) generated for every 16 pulse detection frames and delaying it by the delay circuit 78.
As shown in FIGS. 5 and 6, the pulse i has a rising timing delayed from the pulse g.

The D-FF 76, at the beginning of the fixed frame,
It is set at the rising edge of pulse i and the output signal j is H
It becomes a level. After that, the signal f is latched and output at the rising edge of each pulse g. After the output signal j is set to the H level and is set at the rising edge of the pulse i, the signal f is set to the H level while the signal e is continuously held at the H level in each pulse detection frame. j also holds the H level. Set at the rising edge of pulse i,
After the output signal j becomes H level, the signal e becomes L even once.
When it becomes the level, the output signal j becomes the L level, and thereafter,
The signal f becomes L level regardless of the signal e, and the output signal j
Remains at L level until the next pulse i.

The output signal j of the D-FF 76 is delayed by the delay circuit 79 and supplied as the signal k to the D input terminal of the D-FF 80. Clock terminal CK of D-FF80
Is supplied with a pulse i. The D-FF 80 latches the signal k at the rising edge of the pulse i and outputs it as the signal m from the output terminal Q. When the signal j holds the H level in 16 consecutive pulse detection frames after the pulse i is supplied until the next pulse i is supplied, the H level signal k is latched and the H level signal is latched. m, that is, 2
Outputs a 3T confirmation signal.

In FIG. 5, the 23T detection signal is not continuously supplied in 16 pulse detection frames. In the first pulse detection frame, the 23T confirmation signal is supplied. Therefore, the signal j is set at the rising edge of the pulse i (time t ₁ ) at the beginning of the definite frame, and then held at the H level at the rising edge of the pulse g in the next pulse detection frame (time t _2). ). However, the 23T confirmation signal is not supplied in the second pulse detection frame. Therefore, the signal j is at the L level at the rising edge of the pulse g in the third pulse detection frame (time t ₃ ). Once the signal j is once at the L level, regardless of the value of the signal e, the next rising edge of the pulse i (at time t
Hold L level until ₄ ).

Next rising edge of pulse i (time t ₄ ).
Then, the signal k is latched by the D-FF 80 and output as the signal m. In the example of FIG. 5, a signal k obtained by delaying the L-level signal j by the delay circuit 79 is latched at the rising edge of the pulse i. Therefore, the signal m becomes L level, and the 23T confirmation signal is not generated.

In the example of FIG. 6, the 23T detection signal is continuously supplied in 16 pulse detection frames. Therefore, the signal j is set at the rising edge of the pulse i (time t ₁ ) at the beginning of the definite frame and then held at the H level at the rising edge of the pulse g in the next pulse detection frame (time t _12). ). Similarly at time t ₁₃ , the H level is held at the rising edge of the pulse g. Thereafter, similarly, each pulse g until the next rising edge of the pulse i (time t ₁₅ ).
The H level is held at the rising edge of.

Next rising edge of pulse i (time t ₁₅ ).
Then, the signal k is latched by the D-FF 80 and output as the signal m. In the example of FIG. 6, the signal j that is held at the H level until time t ₁₄ is delayed by the delay circuit 79 and the signal k is delayed.
Are latched at the rising edge of the pulse i (time t ₁₅ ).
Therefore, the signal m becomes H level, and the 23T confirmation signal is generated.

As described above, in this embodiment, the coarse adjustment circuit 18 controls the VCO 19 so that the center frequency of the VCO 19 matches the clock frequency of the reproduced EFM signal.
As a result, the disk 11 can be CAV-driven to reproduce the recorded signal. Therefore, the spindle motor 1
Since it is sufficient to rotate 2 at a constant speed, access time is C
This can be shortened as compared with the LV type device, and since the spindle motor 12 does not require a high torque motor, the power consumption of the device can be reduced. Further, unlike the conventional device, a complicated circuit for controlling the CLV of the spindle motor is unnecessary, and the cost can be reduced accordingly.

Further, since the center frequency of the VCO 19 can be controlled without detecting the position of the optical pickup 14, it is not necessary to provide a position sensor for the optical pickup 14.

[0057]

As described above, according to the present invention, the clock signal and the reproduction data signal can be correctly extracted from the signal from the pickup while the spindle motor is rotating at a constant speed, so that the access time is shortened. In addition, the rotation control circuit of the spindle motor can be simplified and the cost can be reduced. Further, since the spindle motor does not require high torque, it has features such as reduction of power consumption of the device.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a position embodiment of the present invention.

FIG. 2 is a configuration diagram of a coarse adjustment circuit and a VCO.

FIG. 3 is an explanatory diagram of an EFM signal.

FIG. 4 is a circuit diagram of an 11T detection circuit, a 22T detection circuit, a 23T detection circuit, and a 44T detection circuit.

FIG. 5 is a timing chart of a 23T detection circuit.

FIG. 6 is a timing chart of a 23T detection circuit.

[Explanation of symbols]

 11 CD-ROM disk 12 Spindle motor 13 Drive circuit 14 Optical pickup 15 Pickup control section 16 RF amplifier 17 PLL circuit 18 Coarse adjustment circuit 19 VCO 20 EFM demodulation circuit 25a, 25b Pulse width detection section 50 Pulse width determination section 55 Control signal generation Department

Claims (1)

[Claims] 1. A digital disc reproducing apparatus for generating a reproduction data signal by reading the digital signal from a digital disc on which a digital signal containing clock information is recorded in a constant linear velocity format, and rotating the digital disc at a constant speed. A disk drive means for driving, a digital signal reproducing circuit which is supplied with a signal from the pickup to generate a reproduced digital signal, and a reproduced digital signal which is supplied from the digital signal reproducing circuit to extract a clock signal and a reproduced data signal. A signal extraction circuit, a variable frequency oscillator that generates a reference clock signal of the signal extraction circuit and supplies the reference clock signal to the signal extraction circuit, a reproduced digital signal from the digital signal reproduction circuit, and the reference clock signal, Variable frequency oscillation above Digital disk reproduction apparatus, characterized in that it comprises a frequency control circuit for the center frequency is controlled to match the clock frequency of the reproduced digital signal.