JP3199112B2 - Frequency comparator, phase locked loop circuit using the same, frequency error detection circuit, and data reader using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit having a frequency comparator for detecting a frequency error between an input signal and a reproduced clock signal, a frequency error detecting circuit, and a frequency error detecting circuit. The present invention relates to a method and a data reading device using the same.

[0002]

2. Description of the Related Art Hitherto, a phase locked loop circuit having a frequency comparator for detecting a frequency error between an input signal and a reproduced clock signal has been employed in various devices. There is a data reading device for reading data from a recording disk on which information is recorded by a recording method.

In the above-described data reading apparatus, data recorded on a recording disk is read using a data reading clock serving as a reproduction clock, so that data recorded on the recording disk is read. In this case, it is necessary to synchronize the data recorded on the recording disk with the data reading clock. Therefore, in the case of skipping the data recorded on the recording disk or the like, it is necessary to control the synchronization between the data recorded on the recording disk and the data reading clock each time.

Therefore, using a phase locked loop circuit,
Synchronous control of data recorded on a recording disk by a data reading clock is performed.

FIG. 6 is a block diagram showing a configuration example of a phase lock loop circuit provided in the data reading device.

In this conventional example, as shown in FIG. 6, a signal having a predetermined frequency and phase is generated based on an input control voltage, and a voltage controlled oscillator 160 for outputting the signal and a signal output from the voltage controlled oscillator 160 are output. A frequency divider 17 that divides the frequency of the signal by 1 / N and outputs it as a data reading clock
0 is compared with the phase of the synchronization detection pattern in the data signal read from the recording disk (not shown) and the data reading clock output from the frequency divider 170, and the phase error between the two is determined by the width corresponding to the error. A phase comparator 110 that converts the pulse signal into a pulse signal having the same, and compares the frequency of the synchronization detection pattern in the data signal read from the recording disk with the frequency of the data reading clock output from the frequency divider 170. A frequency comparator 120 that converts the frequency error of the above into a pulse signal having a width corresponding to the error and outputs the same; a charge pump 180 that converts the pulse signal output from the phase comparator 110 into a voltage and outputs the same; 18
A low-pass filter 130 that cuts off a high-frequency component that becomes a noise of a voltage value output from 0;
A charge pump 140 that converts the pulse signal output from the first into a voltage and outputs the voltage, and outputs a voltage value passed through the low-pass filter 130 or a voltage value output from the charge pump 140 to the voltage control oscillator 160 as a control voltage. The voltage control oscillator 160 generates a signal having a predetermined frequency and phase based on the control voltage output from the adder 150. In the voltage controlled oscillator 160,
It is configured to oscillate at N times (N is a natural number) of the data reading clock to increase the accuracy.

In the error detection circuit configured as described above, first, the voltage controlled oscillator 160 outputs a signal having a frequency and a phase that is somewhat close to the clock of the data recorded on the recording disk. At 1
/ N to generate a data reading clock.

The data reading clock output from the frequency divider 170 is supplied to the phase comparator 110 and the frequency comparator 120
Is input to

Then, in the frequency comparator 120, a frequency error of the data reading clock with respect to the data signal is detected using the synchronization detection pattern of the data signal read from the recording disk, and the width based on the detected error is increased. Is output.

The pulse signal output from frequency comparator 120 is converted into a voltage value by charge pump 140 and output.

[0011] The voltage value output from the charge pump 140 is input as a control voltage to a voltage controlled oscillator 160 via an adder 150.

Then, in the voltage controlled oscillator 160,
Based on the control voltage output from adder 150, a signal having a predetermined frequency is generated.

After a signal having a predetermined frequency is generated by the voltage controlled oscillator 160, the phase comparator 110 uses a synchronization detection pattern of the data signal read from the recording disk to generate a data reading clock for the data signal. Is detected, and a pulse signal having a width based on the detected error is output.

The pulse signal output from the phase comparator 110 is converted into a voltage value by the charge pump 180, and the low-pass filter 130 cuts off a high-frequency component that becomes noise.

The voltage value passed through the low-pass filter 130 is input to a voltage-controlled oscillator 160 via an adder 150 as a control voltage.

Thereafter, in the voltage controlled oscillator 160,
Based on the control voltage output from the adder 150, a data reading clock in phase with the data signal read from the disk is generated.

By repeating the above-described series of operations, the synchronous control of the data reading clock at the time of starting the motor or at the time of screen seeking with respect to the data recorded on the recording disk is performed.

FIG. 7 is a flow chart for explaining the operation from the time when data recorded on the recording disk is read until the synchronization control of the data reading clock is performed.

As shown in FIG. 7, when data is read from a recording disk (step S101), the read data is amplified at a predetermined amplification factor (step S1).
02).

Next, noise removal and waveform equalization of the amplified data are performed, and the data consisting of "0" and "1"
Conversion into value data is performed (step S103).

Thereafter, the above-described synchronization control is performed using the converted binary data (step S10).
4).

Here, in the recording disk as described above, a specific sync pattern is provided for each frame in order to control the synchronization between the data recorded on the recording disk and the data reading clock. As a signal system, EF used for CD (compact disk) is used.
There are an M signal system, an EFMPLUS signal system used for a DVD (digital video disk), and the like.

FIG. 8 shows the EFM signal system and the EFMPLUS
FIGS. 3A and 3B are diagrams for explaining a signal system, and FIG. 3A is a diagram illustrating a configuration of information recorded on a recording disk, and FIG.
FIG. 3C is a diagram showing a sync pattern in the M signal system, and FIG. 3C is a diagram showing a sync pattern in the EFMPLUS signal system.

As shown in FIG. 8A, a sync pattern is added to a data signal for each frame.

The data signal has a length of 11T or less (T is a channel bit length) depending on the pit length and pit interval of the recording disk.

First, a sync pattern in the EFM signal system will be described.

The sync pattern in the EFM signal system has a maximum inversion interval (11T) of 2 as shown in FIG.
It is a continuous signal. Since the data signal is equal to or less than 11T as described above, the data reading clock measures the signal from the rising edge to the next rising edge or from the falling edge to the next falling edge, and the measured value is 22. If it is, it is not a data signal, it can be determined as a sync pattern,
Actually, the sync pattern is detected in such a manner. A specific example is disclosed in JP-A-59-172180.

Next, a sync pattern in the EFMPLUS signal system will be described.

As shown in FIG. 8C, the sync pattern in the EFMPLUS signal system is a signal having an inversion interval of 14T and 4T.

Here, in the EFMPLUS signal system, "1" is set within 18T which is one cycle of the sync pattern.
9 times, followed by "0" 9 times, 9T + 9T,
"1" lasts 10 times, then "0" lasts 8 times, 10T
Since there is a possibility that a data signal such as + 8T is included, the data reading clock is used to measure from the rising edge of the signal to the next rising edge or from the falling edge to the next falling edge. Cannot be determined as a sync pattern.

Therefore, the data reading clock is
From the rise to the fall, or from the fall to the rise, the measured value is other than 14, a frequency error signal is output based on the measured value, and when the measured value becomes 14, further data Using the read clock, the signal is measured until the rise or fall of the signal thereafter, and the frequency error is detected based on the measured value.

FIG. 9 shows the frequency comparator 120 shown in FIG.
It is a figure for explaining operation of.

As shown in FIG. 9, the data reading clock measures from the rising to the falling or from the falling to the rising of the read EFMPLUS signal, and when the measured value is other than 14, the measured value is used. Pulse signals having mutually different widths are output as frequency error signals (S2 to S4, L2 to L4) on the basis of the measured values, and when the measured value becomes 14, further rising or rising of the signal is further performed by the data reading clock. The pulse signal having different widths is measured based on the measured value until the frequency error signal (S1,
L1).

Thereafter, the output frequency error signal (S1
To S4, L1 to L4) are converted into a voltage value by the charge pump 140, input to the voltage-controlled oscillator 160 as a control voltage via the adder 150, and based on the input control voltage in the voltage-controlled oscillator 160. A signal having a predetermined frequency is generated.

When the frequency error signal (Center) is output, the frequency of the data reading clock and the frequency
This means that the frequency of the FMPLUS signal is synchronized.

Here, the relationship between the synchronous control of the reading clock and the control of the rotation speed of the motor for rotating the recording disk will be described.

FIG. 10 is a diagram for explaining a difference in frequency between data recorded on a recording disk and the number of rotations of a motor.

As shown in FIG. 10, when the number of rotations of the motor is 2
In the case of doubling, the pulse width of the same data is halved.

Here, since the synchronous control of the reading clock and the control of the rotation speed of the motor are performed independently of each other,
If the rotation speed of the motor is not constant immediately after the start of the motor, the measured value of the signal read from the recording disk differs from the actual pattern length by the above-described synchronous control of the reading clock. There is a possibility that it will be.

Therefore, as shown in FIG. 9, when the measured value of the signal read from the recording disk is 11 or less, it is determined that the frequency of the data reading clock is low and the frequency is increased. If the measured value of the signal controlled and read from the recording disc is 17 or more,
It is determined that the frequency of the data reading clock is high and is controlled so that the frequency becomes low, whereby the measured value of the signal read from the recording disk is different from the actual pattern length, and the measured value becomes 14 The synchronization control described above is performed even in the case where the distance is far from the distance.

[0041]

However, in the above-described frequency error detection method, the first section in which digital signals of the same level are continuous is measured by the data reading clock, and when the measured value is other than 14, Since the frequency error signal is output based only on the measured value, a scratch or the like is generated on the disk, and the scratch or the like causes the 14T
Is generated, a pattern is determined to be a sync pattern, and there is a problem that incorrect synchronization control of the data reading clock is performed.

The present invention has been made in view of the above-mentioned problems of the conventional technology, and reduces the probability that erroneous synchronization control between data recorded on a recording disk and a reproduction clock is performed. It is an object of the present invention to provide a frequency comparator, a phase locked loop circuit using the same, a frequency detection circuit, and a frequency error detection method.

[0043]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a specific method comprising a first section in which a plurality of digital signals are continuous and a second section in which a plurality of digital signals are continuous. A digital signal including a synchronization pattern is input, and a frequency comparator that detects a frequency error between the frequency of the digital signal and the clock by measuring the synchronization pattern with a clock and obtains an error value corresponding to the frequency error. Recognizing that the plurality of candidates for the first section set in advance as a result of the measurement,
Subsequently, when a plurality of candidates for the second section set in advance are recognized, a frequency error corresponding to a combination of the recognized candidates for the first section and the candidates for the second section is obtained. It is characterized by the following.

A measuring means for measuring the signal pattern; and judging whether or not the measured value of the first section by the measuring means is a plurality of candidates for the first section set in advance. It is determined whether or not the measurement value of the second section by the measurement means is a plurality of candidates for a preset second section, and the measurement value of the first section by the measurement means is determined by the first section. When it is determined that there are a plurality of candidates for the section, and when the measurement value of the second section by the measuring means is a plurality of candidates for the second section, Determining means for outputting the measured values of the first and second sections when the measured value of the section is less than the minimum value or exceeds the maximum value among the plurality of candidates of the first section; Output from judgment means Serial detects the frequency error based on a combination of the first and second measurement values, characterized in that it has a detection means for determining an error value corresponding to the frequency error.

Further, the synchronization pattern includes a first section in which 14 L-level signals continue continuously and a second section in which H-level signals continue 4 times. .

Further, the synchronization pattern includes a first section in which 14 H-level signals are continuously provided and a second section in which four L-level signals are continuously provided. .

Also, a voltage controlled oscillator for generating and outputting a clock signal having a predetermined frequency based on the input signal, a first section in which a plurality of digital signals are continuous, and a plurality of digital signals in succession. A digital signal including a specific synchronization pattern having a second section to be input is input, and a frequency error between the frequency of the digital signal and the clock is detected by measuring the synchronization pattern with a clock, and the frequency error is detected. A frequency comparator for obtaining a corresponding error value, wherein the clock signal is generated by the voltage controlled oscillator based on the frequency error output from the frequency comparator. The device recognizes that there are a plurality of candidates for the first section set in advance as a result of the measurement, and then When it is recognized that there are a plurality of candidates for the set second section, a frequency error corresponding to a combination of the recognized candidates for the first section and the candidates for the second section is obtained. And

Further, the frequency comparator is a measuring means for measuring the signal pattern, and whether the measured value of the first section by the measuring means is a plurality of candidates for the first section set in advance. It is determined whether or not the measurement value of the second section by the measurement means is a plurality of candidates for a preset second section, and the measurement of the first section by the measurement means is performed. If the value is determined to be a plurality of candidates for the first section, and if the measurement value of the second section by the measuring means is determined to be a plurality of candidates for the second section, or If the measured value of the first section by the measuring means is smaller than a minimum value or larger than a maximum value among a plurality of candidates of the first section, the measured values of the first and second sections are output. Determining means for determining And having a detection means for determining an error value corresponding to the frequency error by detecting the frequency error based on a combination of the output of the first and second measurement values from the means.

Also, E having a frame sync pattern
The FMPLUS signal is input, and the EFMPLUS signal pattern is measured by a clock to obtain the EMPPLUS signal.
A frequency error detection circuit for detecting a frequency error between the FMPLUS signal and the clock;
When the measured value at the first level and the measured value at the second level of the signal are recognized as a plurality of predetermined candidates, the frequency error is detected.

Further, a measuring means for measuring the pattern of the EFMPLUS signal, and judging whether or not the measured value of the first level and the measured value of the second level in the measuring means are the plurality of candidates. By determining whether the pattern is the frame sync pattern, if it is determined that the pattern is a frame sync pattern,
Or outputting the first and second measurement values when the measurement value of the first level by the measurement means is less than a minimum value or exceeds a maximum value among a plurality of candidates of the first level. And a detecting means for detecting the frequency error based on the measurement value output from the determining means.

In addition, when the measured value of the first level is 12 and the measured value of the second level is 3 or 4, It is characterized by outputting a level measurement value.

In addition, when the measured value of the first level is 13 and the measured value of the second level is 3 or 4, It is characterized by outputting a level measurement value.

In addition, when the measured value of the first level is 14 and the measured value of the second level is 3, 4 or 5, 2
It outputs a measured value of the level.

Further, the determination means determines that the first and second levels are only obtained when the measured value of the first level is 15 and the measured value of the second level is 4 or 5. It is characterized by outputting a level measurement value.

Further, the determining means determines that the first and second measurement values are only obtained when the measured value of the first level is 16 and the measured value of the second level is 4 or 5. It is characterized by outputting a level measurement value.

Further, when the measured value of the first level is less than 12, the judging means sends a signal to the detecting means.
A signal for increasing the speed of the clock is output.

Further, when the measured value of the first level is larger than 16, the judging means determines that
A signal for lowering the speed of the clock is output.

Further, a first digital signal in which a plurality of digital signals are continuous
A digital signal including a specific synchronization pattern including a section and a second section in which a plurality of digital signals are continued thereafter is input, and the frequency of the digital signal and the clock are measured by measuring the synchronization pattern with a clock. In the frequency error detection method for detecting a frequency error of the first section and obtaining an error value corresponding to the frequency error, the frequency is recognized as a plurality of candidates for the first section set in advance as a result of the measurement, When it is recognized that there are a plurality of candidates for the second section, the first
And a frequency error corresponding to a combination of the section candidate and the second section candidate.

E having a frame sync pattern
The FMPLUS signal is input, and the EFMPLUS signal pattern is measured by a clock to obtain the EMPPLUS signal.
A frequency error output method for detecting a frequency error between an FMPLUS signal and the clock, wherein the EFMPLUS
When the measured value at the first level and the measured value at the second level of the signal are recognized as a plurality of predetermined candidates, the frequency error is detected.

Further, reading means for reading data recorded on the recording disk, driving means for rotating the recording disk, and reproducing RF signal, focus error signal and tracking error signal from the data read by the optical head. Amplifying means for generating, a control means for controlling the optical head and the driving means, a filter for removing noise and shaping the waveform of the reproduced RF signal generated by the amplifying means,
A binarization circuit for performing a binarization process on the reproduced RF signal generated by the amplifying unit, a phase lock loop circuit for generating a clock synchronized with the data binarized by the binarization circuit, In a data reading device having at least demodulation means for demodulating data, the phase locked loop circuit generates a clock signal having a predetermined frequency based on an input signal, and outputs a voltage controlled oscillator, A digital signal including a specific synchronization pattern including a first section in which a plurality of digital signals are continuous and a second section in which a plurality of digital signals are continuous is input, and the synchronization pattern is measured by a clock. As a result of the measurement, it is recognized that there are a plurality of candidates for the preset first section, and subsequently, it is recognized that it is a plurality of candidates for the preset second section. In this case, it has at least a frequency comparator for obtaining a frequency error corresponding to a combination of the recognized candidate of the first section and the candidate of the second section, and the frequency error output from the frequency comparator The voltage signal is generated by the voltage-controlled oscillator based on the clock signal.

(Operation) In a device for controlling the synchronization of a reproduced clock, a first section in which a plurality of digital signals for performing the synchronization control are continuous in the signal, and a second section in which a plurality of digital signals are continuous thereafter. The specific synchronization pattern includes the specific synchronization pattern, and the value of the length of the first section and the value of the length of the second section constituting the pattern are substantially constant.

Therefore, in the present invention configured as described above, a plurality of candidates for the measured values in the first section and the second section are determined in advance, and the measured values in the first section and the second When it is recognized that the measurement value in the section is a plurality of predetermined candidates, it is determined that the pattern is a specific pattern for performing error detection, and a frequency error has been detected. Further, when the measured value in the first section is less than the minimum value or exceeds the maximum value among the plurality of candidates in the first section, a signal for adjusting the clock speed is output.

Thus, the first pattern which is not a specific pattern
Even when a pattern substantially equal to the section is detected, a frequency error is detected only when the measured value in the second section is recognized as a plurality of predetermined candidates, so that erroneous synchronization control is performed. The probability is reduced.

[0064]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the phase locked loop circuit of the present invention, and shows an error detection circuit in the EFMPLUS signal system.

As shown in FIG. 1, the present embodiment generates a signal having a predetermined frequency and phase based on an input control voltage and outputs the signal, and a signal output from the voltage controlled oscillator 60. Frequency divided by 1 / N,
A frequency divider 70 for outputting as a data reading clock, and an EFMPLUS read from a recording disk (not shown)
A phase comparator 10 that compares the phase of a sync pattern in the signal with the phase of the data reading clock output from the frequency divider 70, converts the phase error between the two into a pulse signal having a width corresponding to the error, and outputs the pulse signal. E read from the recording disk
The frequency of the sync pattern in the FMPLUS signal is compared with the frequency of the data reading clock output from the frequency divider 70,
A frequency comparator 20 for converting a frequency error between the two into a pulse signal having a width corresponding to the error and outputting the pulse signal;
A charge pump 80 that converts a pulse signal output from 0 into a voltage and outputs the voltage, a low-pass filter 30 that cuts off a high-frequency component that becomes noise of the voltage value output from the charge pump 80, and an output that is output from the frequency comparator 20. Charge pump 40 that converts a pulse signal into a voltage and outputs the voltage
And an adder 50 that outputs a voltage value passed through the low-pass filter 30 or a voltage value output from the charge pump 40 to the voltage-controlled oscillator 60 as a control voltage. Based on the control voltage output from the unit 50, a signal having a predetermined frequency and phase is generated. The voltage controlled oscillator 60 is configured to oscillate at N times (N is a natural number) of the data reading clock in order to increase the accuracy.

In the error detecting circuit configured as described above, first, the voltage controlled oscillator 60 outputs a signal having a frequency and a phase that is somewhat close to the clock of the data recorded on the recording disk. At 1 / N
And a data reading clock is generated.

The data reading clock output from the frequency divider 70 is input to the phase comparator 10 and the frequency comparator 20.

Then, the frequency comparator 20 detects a frequency error of the data reading clock with respect to the EFMPLUS signal using the sync pattern of the EFMPLUS signal read from the recording disk, and has a width based on the detected error. A pulse signal is output.

The pulse signal output from the frequency comparator 20 is converted into a voltage value by the charge pump 40 and output.

The voltage value output from the charge pump 40 is input to the voltage controlled oscillator 60 via the adder 50 as a control voltage.

After that, in the voltage controlled oscillator 60, a signal having a predetermined frequency is generated based on the control voltage output from the adder 50.

After a signal having a predetermined frequency is generated by the voltage controlled oscillator 60, the phase comparator 10 uses the sync pattern of the EFMPLUS signal read from the recording disk to generate a data reading clock for the EFMPLUS signal. A phase error is detected, and a pulse signal having a width based on the detected error is output.

The pulse signal output from the phase comparator 10 is converted into a voltage value by the charge pump 80, and the low-pass filter 30 cuts off high-frequency components that become noise.

The voltage value that has passed through the low-pass filter 30 is input to the voltage-controlled oscillator 60 via the adder 50 as a control voltage.

Thereafter, in the voltage controlled oscillator 60, a data reading clock in phase with the data signal read from the disk is generated based on the control voltage output from the adder 50.

By repeating the above-described series of operations, the data read clock is synchronized with the data recorded on the recording disk.

Hereinafter, the configuration and operation of the frequency comparator 20 will be described in detail.

FIG. 2 is a diagram showing a configuration of the frequency comparator 20 shown in FIG.

As shown in FIG. 2, the frequency comparator 20 in the present embodiment measures the data reading clock from the rising to the falling (PN) or from the falling to the rising (NP) of the input EFMPLUS signal. A counter 21 that outputs a measured value, and a data reading clock at (PP) from the rising edge of the input EFMPLUS signal to the next rising edge.
A counter 22 for outputting a measured value, and an input EFMP
From the fall of the LUS signal to the next fall (N
N) measures the data reading clock and outputs a measured value, and the measured values of the counters 21 to 23 are input, and the input measured value is compared with a predetermined candidate. It is determined whether or not the EFMPLUS signal input to the counters 21 to 23 is a sync pattern, and only when the measured value is recognized as a predetermined candidate, that is, when it is determined that the measured value is a sync pattern, the measured value is determined. And a frequency error detecting unit 2 for detecting a frequency error based on the measurement value output from the sync pattern determining unit 24.
And 5.

The operation of detecting the frequency error in the frequency comparator configured as described above will be described below.

First, the operation of the counters 21 to 23 shown in FIG. 2 will be described.

FIG. 3 shows the counters 21 to 23 shown in FIG.
It is a timing chart for explaining the operation of,
3A is a diagram illustrating a case where a counter 23 detects a sync pattern, and FIG. 3B is a diagram illustrating a case where a counter 22 detects a sync pattern.

As shown in FIG. 3 (a), EFMPLUS
When the rising of the signal is detected, the counters 21 and 22 are detected.
, The measurement of the EFMPLUS signal is started.

Next, when the falling of the EFMPLUS signal is detected, it is output that the measured value from the rising to the falling of the EFMPLUS signal in the counter 21 is “7”, and the counters 21 and 23 output the EFMPLUS signal. Signal measurement is started.

Next, when the rising of the EFMPLUS signal is detected, it is output that the measured value from the falling to the rising of the EFMPLUS signal in the counter 21 is “3”.
It is output that the measured value from the rising edge of the MPPLUS signal to the next rising edge is “10”.
The measured values of the “1” and “0” levels from the rising of the EFMPLUS signal to the next rising are respectively
7 and 3 are detected.

At the same time, EF
The measurement of the MPPLUS signal is started.

Next, when the falling of the EFMPLUS signal is detected, it is output that the measured value from the rising to the falling of the EFMPLUS signal in the counter 21 is “3”.
It is output that the measured value from the falling edge of the MPPLUS signal to the next falling edge is “6”.
The measured values of the “0” and “1” levels from the fall of the FMPLUS signal to the next fall are respectively
3 and 3 are detected.

At the same time, EF
The measurement of the MPPLUS signal is started.

Next, when the rising of the EFMPLUS signal is detected, the measured value from the falling to the rising of the EFMPLUS signal in the counter 21 is "14".
Is output, and E in the counter 22 is output.
It is output that the measured value from the rising edge of the FMPLUS signal to the next rising edge is “17”, so that the measured values of the “1” and “0” levels from the rising edge of the EFMPLUS signal to the next rising edge are respectively 3 and 14 are detected.

At the same time, EF
The measurement of the MPPLUS signal is started.

Next, when the falling of the EFMPLUS signal is detected, it is output that the measured value from the rising to the falling of the EFMPLUS signal in the counter 21 is “4”.
It is output that the measured value from the fall of the MPPLUS signal to the next fall is “18”, whereby
The measured values of the “0” and “1” levels from the fall of the EFMPLUS signal to the next fall are respectively
14, 4 are detected.

Here, as described above, EFMPLUS
Since the sync pattern of the signal is a signal having an inversion interval of 14T and 4T, in the present embodiment, 12 to 12T are candidates for the first section in which digital signals of the same level are continuous.
16, 3 to 5 are predetermined as candidates for the second section in which digital signals of different levels from the first section are continuous. Therefore, if the measured values of the “0” and “1” levels from the fall of the EFMPLUS signal to the next fall are respectively 14 and 4, it is determined that the detected signal is a sync pattern.

As shown in FIG. 3B, EFMPLUS
When the rising of the signal is detected, the counters 21 and 22 are detected.
, The measurement of the EFMPLUS signal is started.

Next, when the falling edge of the EFMPLUS signal is detected, the counter 21 outputs a value of "7" from the rising edge to the falling edge of the EFMPLUS signal, and the counters 21 and 23 output the EFMPLUS signal. Signal measurement is started.

Next, when the rising of the EFMPLUS signal is detected, it is output that the measured value from the falling to the rising of the EFMPLUS signal in the counter 21 is “3”.
It is output that the measured value from the rising edge of the MPPLUS signal to the next rising edge is “10”.
The measured values of the “1” and “0” levels from the rising of the EFMPLUS signal to the next rising are respectively
7 and 3 are detected.

At the same time, EF
The measurement of the MPPLUS signal is started.

Next, when the falling of the EFMPLUS signal is detected, the measured value from the rising to the falling of the EFMPLUS signal in the counter 21 is "14".
Is output, and E in the counter 23 is output.
It is output that the measured value from the falling edge of the FMPLUS signal to the next falling edge is “17”, thereby measuring the “0” and “1” levels from the falling edge of the EFMPLUS signal to the next falling edge. It is detected that the values are 3 and 14, respectively.

At the same time, EF
The measurement of the MPPLUS signal is started.

Next, when the rising of the EFMPLUS signal is detected, it is output that the measured value from the falling to the rising of the EFMPLUS signal in the counter 21 is “4”.
It is output that the measured value from the rising edge of the MPPLUS signal to the next rising edge is “18”.
The measured values of the “1” and “0” levels from the rising of the EFMPLUS signal to the next rising are respectively
14, 4 are detected.

Here, as described above, EFMPLUS
Since the sync pattern of the signal is a signal having an inversion interval of 14T and 4T, in the present embodiment, 12 to 12T are candidates for the first section in which digital signals of the same level are continuous.
16, 3 to 5 are predetermined as candidates for the second section in which digital signals of different levels from the first section are continuous. Therefore, if the measured values of the “1” and “0” levels from the rising of the EFMPLUS signal to the next rising are respectively 14 and 4, it is determined that the detected signal is the sync pattern.

Next, the operation of the sync pattern determining section 24 and the frequency error detecting section 25 shown in FIG. 2 will be described.

FIG. 4 is a diagram for explaining the operation of the sync pattern determination section 24 and the frequency error detection section 25 shown in FIG.

When the measured values of the counters 21 to 23 are input to the sync pattern determining unit 24, first,
In the sync pattern determination unit 24, the counters 21 to 2
3 is determined whether or not the EFMPLUS signal input to the counter 21 is a sync pattern, and only when it is determined that the EFMPLUS signal input to the counters 21 to 23 is a sync pattern, based on the measurement values of the counters 21 to 23, Frequency error detection is performed by the frequency error detection unit 25.

The operation of the sync pattern determining section 24 and the frequency error detecting section 25 based on the measured values of the counters 21 to 23 will be specifically described below.

When the measured value (PN or NP) of the counter 21 is less than 12, since the value less than 12 is not a candidate in the first section, the sync pattern determining unit 24
It is determined that the sync pattern is too short, and a signal S4 for increasing the frequency of the data reading clock output from the voltage controlled oscillator 60 is output from the frequency error detection unit 25. Note that the signal S4 is a pulse signal having a width for controlling so as to increase the frequency output from the voltage controlled oscillator 60.

The value measured by the counter 21 (PN
If NP) is larger than 16, a value larger than 16 is not a candidate in the first section, so the sync pattern determining unit 24 determines that the sync pattern is too long, and the voltage controlled oscillator 60 outputs the value. A signal L4 for lowering the frequency of the data reading clock is output from the frequency error detection unit 25. Note that the signal L4 is a pulse signal having a width for controlling the frequency output from the voltage controlled oscillator 60 to be reduced.

The value measured by the counter 21 (EF
(From the rise to the fall or from the fall to the rise of the MPPLUS signal) is 12,
Since 12 is a candidate in the first section, a subsequent measurement value (from the falling edge to the rising edge or from the rising edge to the falling edge of the EFMPLUS signal) of the counter 21 is fetched, and the measured value is 3 or 4. That is, the measured value (E
From the rising edge of the FMPLUS signal to the next rising edge) or the value measured by the counter 23 (EFMPLU).
If the measured values of the “0” and “1” levels in the (from the fall of the S signal to the next fall) are 12, 3 or 12, 4, respectively, the measured value in the first section is 1
In the case of 2, the candidates for the second section are 3 and 4, so the signal is determined to be a sync pattern, and the frequency error detection unit 25 outputs the frequency error signal S3 corresponding to the measurement value of the counter 21. You. Further, when the measurement value (from the fall to the rise or from the rise to the fall of the EFMPLUS signal) of the counter 21 is other than 3 or 4, it is determined that the pattern is not a sync pattern. No frequency error detection is performed, and the previously output frequency error signal is held and output.

The value measured by the counter 21 (EF
(From the rise to the fall or from the fall to the rise of the MPPLUS signal) is 13,
Since 13 is a candidate in the first section, a subsequent measurement value (from the falling to the rising edge or from the rising to the falling edge of the EFMPLUS signal) of the counter 21 is taken in, and when the measured value is 3, ie, , The value measured by the counter 22 (EFMP
“0” in the measurement value (from the falling edge of the EFMPLUS signal to the next falling edge) in the counter 23 (from the rising edge of the LUS signal to the next rising edge),
When the measured value of the “1” level is 13 and 3, respectively, and when the measured value of the first section is 13 and the candidates of the second section are 3 and 4, Is determined to be a pattern, and the frequency error
A frequency error signal S2 corresponding to the measured value at is output. Further, the value measured by the counter 21 (EF)
When the value of the MPPLUS signal from the fall to the rise or from the rise to the fall) is 4, that is, the value measured by the counter 22 (EFMPPLUS).
The measured values of the “0” and “1” levels in the measured value (from the falling edge of the EFMPLUS signal to the next falling edge) of the counter 23 from the rising edge of the signal to the next rising edge were 13, 4 respectively. In this case, when the measured value of the first section is 13 and the candidates of the second section are 3 and 4, the signal is determined to be a sync pattern. Is output. Also,
The value measured by the counter 21 (EFMPLUS
If the signal from the fall to the rise or from the rise to the fall) is other than 3 or 4, it is determined that the signal is not a sync pattern, and the frequency error detection unit 2
In 5, the frequency error detection is not performed, and the previously output frequency error signal is held and output.

The value measured by the counter 21 (EF)
(From the rise to the fall or from the fall to the rise of the MPPLUS signal) is 14,
Since 14 is a candidate in the first section, the subsequent measurement value (from the fall to the rise or from the rise to the fall of the EFMPLUS signal) of the counter 21 is taken in, and when the measured value is 3, that is, , The value measured by the counter 22 (EFMP
“0” in the measurement value (from the falling edge of the EFMPLUS signal to the next falling edge) in the counter 23 (from the rising edge of the LUS signal to the next rising edge),
When the measured value of the “1” level is 14, 3 respectively, the candidate of the second section when the measured value of the first section is 14 is 3, 4, 5 Is determined to be a sync pattern, and a frequency error signal S1 corresponding to the value measured by the counter 21 is output from the frequency error detection unit 25. Further, when the measurement value (from the falling edge to the rising edge or from the rising edge to the falling edge of the EFMPLUS signal) of the counter 21 is 4, that is, the measurement value (EFMPLUS
“0” in the measurement value (from the falling edge of the EFMPLUS signal to the next falling edge) in the counter 23 (from the rising edge of the LUS signal to the next rising edge),
When the measured values of the “1” level are 14, 4 respectively, and when the measured value of the first section is 14, the candidates of the second section are 3, 4, 5 Is determined to be a sync pattern, and a signal CENTER indicating that the frequency of the data reading clock and the frequency of the EFMPLUS signal are synchronized is output from the frequency error detection unit 25. Further, the value measured by the counter 21 (EF)
When the value of the MPPLUS signal from the fall to the rise or from the rise to the fall) is 5, that is, the value measured by the counter 22 (EFMPPLUS).
The measured values of the “0” and “1” levels in the measured value (from the falling edge of the EFMPLUS signal to the next falling edge) of the counter 23 from the rising edge of the signal to the next rising edge were 14, 5 respectively. In this case, when the measured value of the first section is 14, the candidates of the second section are 3, 4, and 5, so the signal is determined to be a sync pattern, and the frequency error A frequency error signal L1 corresponding to the measured value is output. Further, the measurement value (EFMPL) in the counter 21 thereafter
If the US signal falls from rising to rising or from rising to falling) is other than 3, 4, and 5, it is determined that the pattern is not a sync pattern, and the frequency error detection unit 25 does not perform frequency error detection. The output frequency error signal is held and output.

The value measured by the counter 21 (EF)
(From the rise to the fall or from the fall to the rise of the MPPLUS signal) is 15,
Since 15 is a candidate in the first section, a subsequent measurement value (from the falling edge to the rising edge or from the rising edge to the falling edge of the EFMPLUS signal) of the counter 21 is fetched, and when the measured value is 4, that is, , The value measured by the counter 22 (EFMP
“0” in the measurement value (from the falling edge of the EFMPLUS signal to the next falling edge) in the counter 23 (from the rising edge of the LUS signal to the next rising edge),
When the measured value of the “1” level is 15, 4 respectively, and when the measured value of the first section is 15, the candidates of the second section are 4, 5 Is determined to be a pattern, and the frequency error
, A frequency error signal L1 corresponding to the measured value is output. Further, the value measured by the counter 21 (EF)
When the value of the MPPLUS signal from the fall to the rise or from the rise to the fall) is 5, that is, the value measured by the counter 22 (EFMPPLUS).
The measured values of the “0” and “1” levels in the measured value (from the falling edge of the EFMPLUS signal to the next falling edge) of the counter 23 from the rising edge of the signal to the next rising edge were 15 and 5, respectively. In this case, when the measured value of the first section is 15, the candidates of the second section are 4 and 5, and thus the signal is determined to be a sync pattern. Is output. Also,
The value measured by the counter 21 (EFMPLUS
If the signal (from the fall to the rise or from the rise to the fall) is other than 4 or 5, it is determined that the signal is not a sync pattern, and the frequency error detector 2
In 5, the frequency error detection is not performed, and the previously output frequency error signal is held and output.

The value measured by the counter 21 (EF)
(From the rising edge to the falling edge or from the falling edge to the rising edge of the MPPLUS signal) is 16,
16 is a candidate in the first section, so that a subsequent measurement value (from the fall to the rise or from the rise to the fall of the EFMPLUS signal) of the counter 21 is fetched and the measured value is 4 or 5 That is, the measured value (E
From the rising edge of the FMPLUS signal to the next rising edge) or the value measured by the counter 23 (EFMPLU).
If the measured values of the “0” and “1” levels in the period from the fall of the S signal to the next fall are 16, 4 or 16, 5, respectively, the measured value in the first section is 1
Since the candidates for the second section in the case of 6 are 4, 5, the signal is determined to be a sync pattern, and the frequency error detection unit 25 outputs the frequency error signal L3 according to the value measured by the counter 21. You. If the value measured by the counter 21 (from the falling edge to the rising edge or from the rising edge to the falling edge) of the EFMPLUS signal is other than 4 or 5, it is determined that the signal is not a sync pattern. No frequency error detection is performed, and the previously output frequency error signal is held and output.

The frequency error signals S1 to S
3, L1 to L3 are pulse signals having a width for controlling the frequency output from the voltage controlled oscillator 60 in accordance with the value measured by the counter 21.

Thereafter, the output frequency error signals S1 to S1
S4, L1 to L4 are voltage controlled oscillators 60 as control voltages.
And the voltage is controlled in the voltage controlled oscillator 60 based on the frequency error signals S1 to S4 and L1 to L4, whereby the frequency of the data reading clock is EF.
It is controlled to synchronize with the frequency of the MPPLUS signal.

As described above, in this embodiment, the EFM
A measured value from the rising to the falling or from the falling to the rising in the sync pattern of the PLUS signal, that is, the measured value in the first section;
The measured values until the subsequent fall or rise, that is, the measured values in the second section are 14,
4, the candidates in the first section and the second section are determined in advance, and it is determined whether or not the actual measurement value is a candidate. It is determined whether or not there is, and only when it is determined that the frame sync is detected, the frequency error is detected. In the above-described embodiment, the phase error between the data reading clock and the EFMPLUS signal (−π to +
In consideration of π), several combinations are provided in the above-described ratio, and a frequency error signal corresponding to each combination is output.

For example, the longer sync pattern (14
When T) is measured, assuming that the data reading clock, which is the reproduction clock, is short, at this time, if the phases of the EFMPLUS signal and the data reading clock can take all values from -π to + π, the counter measurement The result is a combination of 14: 5, 14: 4, 15: 4.

However, these combinations are, for example, 1
In the case of 4: 4, this is a combination that occurs when the frequency error of the data reading clock is 0.

As described above, different frequency errors output the same combination result depending on the phase of the EFMPLUS signal and the data reading clock.

Here, the appearance probabilities of these combinations differ for a certain frequency error. For example, when the cycle of the data reading clock is shorter by half a clock, the appearance probability of the combination is 15: 4> 14: 4> 14: 5. Similarly, when the cycle of the data reading clock is shorter by a quarter clock, 14: 5, 15: 4, 1
A 4: 4 combination occurs, but its appearance probability is 1
4: 4> 15: 4> 14: 5.

The above-described circuit is realized by logically synthesizing the HDL description.

FIG. 5 is a block diagram showing a configuration example of a data reading device to which the phase locked loop circuit shown in FIG. 1 is applied.

In this embodiment, as shown in FIG. 5, an optical head 202 as reading means for reading data recorded on the recording disk 201, a disk motor 203 as driving means for rotating the recording disk 201, and an optical head 202 A preamplifier 204 as amplifying means for generating a reproduction RF signal, a focus error signal, a tracking error signal, and the like from the data read by the servo controller 205; a servo controller 205 as control means for controlling the optical head 202 and the disk motor 203; A filter circuit 206 for removing noise and shaping the waveform of the reproduced RF signal generated at 204, and data 2 for binarizing the reproduced RF signal generated at the preamplifier 204 into data consisting of "0" and "1" The binarizing circuit 207 and the data binarized by the data binarizing circuit 207 A phase locked loop circuit 208 that generates a synchronized clock, the demodulation circuit demodulates the data 20
9, an error correction circuit 210 for correcting an error in reproduced data due to a burst or the like, and a CPU 2 for controlling the entire apparatus.
And a phase locked loop circuit 20.
8 is applied as shown in FIG.

In the data reading device configured as described above, the recording head 201
When the data recorded in the preamplifier 20 is read,
In 4, a reproduced RF signal, a focus error signal, a tracking error signal, and the like are generated from the data read by the optical head 202, and the filter circuit 206 removes noise and shapes the reproduced RF signal generated by the preamplifier 204. Is performed, and the reproduced RF signal generated by the preamplifier 204 is binarized by the data binarization circuit 207 into data including “0” and “1”.

Thereafter, in the demodulation circuit 209, the data binarized by the data binarization circuit 207 is demodulated by the clock generated by the phase lock loop circuit 208.

The operation of the phase locked loop circuit 208 is the same as that described above, and a description thereof will not be repeated.

[0126]

As described above, in the present embodiment,
A plurality of measurement value candidates in the first section and the second section are determined in advance, and the measurement value in the first section and the measurement value in the second section are recognized as a plurality of predetermined candidates. In this case, the pattern is determined to be a specific pattern for performing error detection, a frequency error is detected, and the measured value in the first section is smaller than the minimum value among a plurality of candidates in the first section. Alternatively, a signal for adjusting the clock speed is output when the value exceeds the maximum value. Therefore, even when a pattern which is not a specific pattern and which is substantially equal to the first section is detected, the second section is used. The frequency error is output only when it is recognized that the measured values in are a plurality of predetermined candidates, and the probability of performing erroneous synchronization control can be reduced.

As a result, the time required to pull in the frequency of the reproduced clock can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a phase locked loop circuit of the present invention.

FIG. 2 is a diagram showing a configuration of a frequency comparator shown in FIG.

3A and 3B are timing charts for explaining the operation of the counter shown in FIG. 2, wherein FIG. 3A shows a case where a counter 23 detects a sync pattern, and FIG. It is a figure showing the case where a pattern is detected.

FIG. 4 is a diagram for explaining operations of a sync pattern determination unit and a frequency error detection unit shown in FIG. 2;

FIG. 5 is a block diagram illustrating a configuration example of a data reading device to which the phase locked loop circuit illustrated in FIG. 1 is applied.

FIG. 6 is a block diagram illustrating a configuration example of a phase locked loop circuit provided in the data reading device.

FIG. 7 is a flowchart for explaining an operation from reading data recorded on a recording disk to performing synchronization control of a data reading clock.

FIGS. 8A and 8B are diagrams for explaining an EFM signal system and an EFMPLUS signal system, wherein FIG. 8A shows a configuration of information recorded on a recording disk, and FIG. 8B shows a sync pattern in the EFM signal system; Figure, (c) EFMLU
FIG. 3 is a diagram showing a sync pattern in the S signal system.

FIG. 9 is a diagram for explaining an operation of the frequency comparator shown in FIG. 6;

FIG. 10 is a diagram for explaining a difference in frequency of data recorded on a recording disk depending on the number of rotations of a motor.

[Explanation of symbols]

 Reference Signs List 10 phase comparator 20 frequency comparator 21 to 23 counter 24 sync pattern determination unit 25 frequency error detection unit 30, 40 low-pass filter 50 adder 60 voltage-controlled oscillator 70 frequency divider 201 recording disk 202 optical head 203 disk motor 204 preamplifier 205 Servo controller 206 Filter circuit 207 Data binarization circuit 208 Phase locked loop circuit 209 Demodulation circuit 210 Error correction circuit 211 CPU

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L 7/087 G11B 20/14 351 H03L 7/085

Claims (18)

(57) [Claims] 1. A digital signal including a specific synchronization pattern having a first section in which a plurality of digital signals are continuous and a second section in which a plurality of digital signals are continuous is input, and the synchronization pattern is clocked. In the frequency comparator which detects a frequency error between the frequency of the digital signal and the clock by measuring by the measurement, and obtains an error value corresponding to the frequency error, If it is recognized as a plurality of candidates, and subsequently, it is recognized as a plurality of candidates for the preset second section, the recognized candidates for the first section and the candidates for the second section A frequency error according to the combination of the frequency comparator. 2. The frequency comparator according to claim 1, wherein: a measuring unit that measures the signal pattern; and a plurality of first sections in which the measurement value of the first section in the measuring unit is set in advance. And determining whether the measurement value of the second section in the measurement means is a plurality of candidates for a second section set in advance, and determining whether the measurement value of the second section is a plurality of candidates for the second section. It is determined that the measurement value of one section is a plurality of candidates for the first section, and that the measurement value of the second section by the measurement means is a plurality of candidates for the second section. Or when the measurement value of the first section by the measuring means is less than a minimum value or exceeds a maximum value among a plurality of candidates for the first section, the first and second sections Output the measured value of Means, and detecting means for detecting the frequency error based on a combination of the first and second measurement values output from the determining means and obtaining an error value according to the frequency error. Frequency comparator. 3. The frequency comparator according to claim 1, wherein the synchronization pattern is such that a first section in which 14 L-level signals continue continuously and a H-level signal in succession. A frequency comparator comprising four second sections that follow. 4. The frequency comparator according to claim 1, wherein the synchronization pattern is such that a first section in which 14 H-level signals continue continuously and a L-level signal in succession. A frequency comparator comprising four second sections that follow. 5. A voltage-controlled oscillator for generating and outputting a clock signal having a predetermined frequency based on an input signal, a first section in which a plurality of digital signals are continuous, and a plurality of digital signals continuous therefrom. A digital signal including a specific synchronization pattern having a second section to be input is input, and a frequency error between the frequency of the digital signal and the clock is detected by measuring the synchronization pattern with a clock, and the frequency error is detected. A frequency comparator for determining a corresponding error value, wherein the clock signal is generated by the voltage-controlled oscillator based on the frequency error output from the frequency comparator. The device recognizes that there are a plurality of candidates for the first section set in advance as a result of the measurement, and then sets And determining a frequency error corresponding to a combination of the recognized candidate for the first section and the candidate for the second section when the plurality of candidates for the second section are recognized. Phase locked loop circuit. 6. The phase locked loop circuit according to claim 5, wherein the frequency comparator is configured to measure a pattern of the signal, and a measurement value of the first section in the measurement unit is set in advance. And determining whether or not the measurement values of the second section by the measuring means are a plurality of candidates for a second section set in advance. Determining that the measurement value of the first section by the measurement means is a plurality of candidates for the first section, and that the measurement value of the second section by the measurement means is a candidate for the second section. When it is determined that there are a plurality of candidates, or when the measurement value of the first section in the measuring means is less than the minimum value or exceeds the maximum value among the plurality of candidates of the first section, 1st and 1st Determining means for outputting a measured value of the section 2; detecting the frequency error based on a combination of the first and second measured values output from the determining means, and calculating an error value corresponding to the frequency error; A phase-locked loop circuit comprising: 7. An EFM having a frame sync pattern.
A PLUS signal is input, and the EFMPLUS signal pattern is measured by a clock to obtain the EFM signal.
In a frequency error detection circuit for detecting a frequency error between a PLUS signal and the clock, a measurement value at a first level and a measurement value at a second level of the EFMPLUS signal are recognized as a plurality of predetermined candidates. A frequency error detection circuit for detecting the frequency error when the frequency error is detected. 8. The frequency error detection circuit according to claim 7, wherein: a measuring unit for measuring a pattern of the EFMPLUS signal; and a measured value of the first level and a measured value of the second level in the measuring unit. By determining whether or not the pattern is the plurality of candidates, thereby determining whether the pattern is the frame sync pattern. When determining that the pattern is the frame sync pattern, or determining whether the pattern is the frame sync pattern, Determining means for outputting the first and second measured values when the measured value of the level is less than the minimum value or greater than the maximum value among the plurality of candidates of the first level; Detecting means for detecting the frequency error based on the output measurement value. 9. The frequency error detection circuit according to claim 8, wherein the determination unit determines that the measured value of the first level is 12 and the measured value of the second level is 3 or 4. A frequency error detection circuit which outputs the measured values of the first and second levels when there is. 10. The frequency error detection circuit according to claim 8, wherein the determination unit determines that the measured value of the first level is 13 and the measured value of the second level is 3 or 4. A frequency error detection circuit which outputs the measured values of the first and second levels when there is. 11. The frequency error detection circuit according to claim 8, wherein the determination unit determines that the measured value of the first level is 14, and the measured value of the second level is 3, 4, or If it is 5,
A frequency error detecting circuit for outputting the measured values of the first and second levels. 12. The frequency error detection circuit according to claim 8, wherein the determination unit determines that the measured value of the first level is 15 and the measured value of the second level is 4 or 5. A frequency error detection circuit which outputs the measured values of the first and second levels only when there is an error. 13. The frequency error detection circuit according to claim 8, wherein the determination unit determines that the measured value of the first level is 16 and the measured value of the second level is 4 or 5. A frequency error detection circuit which outputs the measured values of the first and second levels only when there is an error. 14. The frequency error detection circuit according to claim 8, wherein the determination unit is configured to increase the clock speed from the detection unit when the measured value of the first level is less than 12. A frequency error detection circuit for outputting a frequency error signal. 15. The frequency error detection circuit according to claim 8, wherein the determination unit is configured to reduce a speed of the clock from the detection unit when the measured value of the first level is larger than 16. A frequency error detection circuit for outputting a signal. 16. A first section in which a plurality of digital signals are continuous, and a second section in which a plurality of digital signals are continuous.
A digital signal including a specific synchronization pattern having a section is input, and a frequency error between the frequency of the digital signal and the clock is detected by measuring the synchronization pattern with a clock, and an error corresponding to the frequency error is detected. In the frequency error detection method for obtaining a value, the plurality of candidates in the first section are recognized as a plurality of candidates in the first section set as a result of the measurement, and then the plurality of candidates in the second section are set in advance. A frequency error detection method comprising: determining a frequency error according to a combination of the recognized candidate for the first section and the candidate for the second section when the recognition is performed. 17. An EF having a frame sync pattern
The MPPLUS signal is input, and the EFMPPLUS signal is measured by a clock to measure the pattern of the EF
In a frequency error output method for detecting a frequency error between an MPPLUS signal and the clock, a measurement value at a first level and a measurement value at a second level of the EFMPLUS signal are recognized as a plurality of predetermined candidates. Detecting the frequency error when the error occurs. 18. A reading means for reading data recorded on a recording disk, a driving means for rotating the recording disk, and a reproducing means for reproducing data from the data read by the optical head.
Amplifying means for generating an F signal, a focus error signal and a tracking error signal, control means for controlling the optical head and driving means, and reproduction R generated by the amplifying means
A filter for removing noise and waveform shaping of the F signal, a binarization circuit for performing a binarization process on the reproduced RF signal generated by the amplifying means, and data binarized by the binarization circuit In a data reading device having at least a phase locked loop circuit that generates a clock synchronized with the data and a demodulation unit that demodulates data, the phase locked loop circuit has a predetermined frequency based on an input signal. A voltage-controlled oscillator for generating and outputting a clock signal; and a digital signal including a specific synchronization pattern including a first section in which a plurality of digital signals are continuous and a second section in which a plurality of digital signals are continuous. The synchronization pattern is input and measured by a clock, and as a result of the measurement, it is recognized that there are a plurality of candidates for the first section set in advance. A frequency comparator for determining a frequency error corresponding to a combination of the recognized candidate for the first section and the candidate for the second section when the plurality of candidates for the second section are recognized. At least
A data reading device, wherein the clock signal is generated by the voltage controlled oscillator based on a frequency error output from the frequency comparator.