JP3222128B2 - Synchronous signal reproducing apparatus and synchronous signal reproducing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to synchronous reproduction of an optical disk drive, and in particular, to a DBF (DiscreteBlode) in which a clock pit is embedded.
The present invention relates to a synchronizing signal reproducing circuit and a synchronizing signal reproducing method suitable for reproducing a synchronizing signal of the (ck Format) type.

[Conventional technology]

2. Description of the Related Art A recording / reproducing apparatus that uses an optical disc and is capable of recording a large amount of data and has excellent portability has been supplied to the market centering on 2.25 inches. As one of the recording formats of this optical disc, a format called a sample servo system or a DBF system has been proposed. This format is
Servo marks are pre-formatted at specific intervals in advance on concentric or spiral tracks on the disk, and clock control, tracking control, focus control and This is to perform access control.

A clock reproducing circuit corresponding to an optical disk having such a format is disclosed in JP-A-63-94731. The format shown here is a standard of 5.25 inches, but the DBF format proposed for 3.5 inches also has servo marks composed of wobble pits, clock pits and access marks.

FIG. 5 is an explanatory diagram showing a configuration example of a 3.5-inch DBF format. The 3.5-inch DBF format has 22 sectors per track, and one sector is composed of 76 segments. The first three segments of the sector are areas in which identification codes of tracks, sectors, and the like and control data are recorded. One segment has a data length of 10 bytes, of which the first two bytes are allocated to servo marks. The data length of 1 byte is composed of 11 channel bits, and in the data portion excluding the servo mark, 4 channel bits out of the 11 channel bits are marked and 4/11 modulated so that the remainder is space and recorded. The servo mark includes an access mark, a clock pit, and a wobble pit, and is used for access control, clock reproduction control, and tracking control, respectively.
The access mark is a 3 out of 6 gray code,
It changes at a 16-track cycle for each track. The clock pit and the wobble pit are always located at the same position, the clock pit is located at the center of the track, and the pair of wobble pits are shifted by 1/4 track from the center of the track in opposite directions. The sector mark exists only in the first segment of the sector, and has a 2-byte length of a unique distance followed by a continuous space of 16 channel bits and a pattern of 4/11 modulation loss.

[Problems to be solved by the invention]

The clock reproduction as a DBF-type synchronous signal reproduction circuit having such a format is performed by extracting a clock pit of a servo mark embedded in a disk and using the clock pit signal as a reference. For this reason, clock pit extraction must be accurate, but noise may cause synchronization to be erroneously introduced into a pseudo pulse around the clock pit, or synchronization may be disturbed by noise and jitter may increase. was there.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a DBF-type synchronous signal reproducing circuit capable of reducing erroneous detection of clock pits due to noise, disturbance of synchronization, jitter and the like.

[Means for solving the problem]

In order to achieve the above object, the present invention includes a noise pulse removing unit that removes, as a noise pulse, a pulse within a specific cycle of an output signal of a peak detection circuit that detects a peak of a reproduced signal. Furthermore, a pseudo clock generating means for generating a pseudo clock is provided, and before the synchronization is established, a window signal used for extracting clock pits is generated using the pseudo clock, and after the synchronization is established, the window signal is generated using the output of the PLL. Is generated.

[Action]

The peak detection circuit detects a peak of the reproduction signal and outputs a peak detection signal. The latch circuit removes noise superimposed on peak detection by latching the peak detection signal with a clock (pseudo clock) from a crystal oscillator. The AND circuit outputs a logical product of the peak detection signal and the output latched by the latch circuit. Since the extraction of the clock pit is performed from the output signal from the AND circuit, the noise of the peak detection signal is removed by the latch circuit, and the phase comparison of the PLL is based on the fall of the peak detection signal of the clock pit. Clock reproduction disturbance due to noise can be reduced and jitter can be reduced.

〔Example〕

 Hereinafter, the present invention will be described in detail.

FIG. 1 is a block diagram showing an embodiment of a synchronization signal reproducing circuit of an optical disk device according to the present invention. In FIG. 1, 1 is a peak detection circuit for detecting a peak position based on a reproduction signal from an optical disk, 2 is a noise pulse elimination circuit for removing noise of the reproduction signal appearing in the peak detection signal, 3 is a shift register, and 4 is a unique. A pattern detection circuit, 5 a crystal oscillator having the same frequency as the clock frequency, 6
Is a counting and decoding circuit for counting its frequency, 7 is a switching circuit, 8 is a clock pit extracting circuit, 9 is a phase comparator, 10 is a voltage controlled oscillator (VCO), 11 is a counting and counting circuit for counting clocks output from the VCO. A decoding circuit 12 is a synchronization control circuit. FIG. 2 shows signal waveforms at various parts shown in FIG.

First, the schematic operation of the synchronization signal reproducing circuit of the present invention will be described with reference to these drawings. In FIG. 1, a reproduced signal from an optical disc is differentiated by a peak detection circuit 1,
As shown in FIG. 2, a peak detection signal A is output so that a pulse comes at the peak position of the reproduction signal. The peak detection signal A is input to the noise pulse elimination circuit 2 and outputs a noise pulse elimination signal B superimposed on the reproduction signal as described later. The noise pulse elimination signal B is input to the shift register 3 and is shifted by a 2-byte length of 22 channel bits by a clock from the crystal oscillator 5 that oscillates the same clock as the pit clock frequency. The unique pattern detection circuit 4 detects the presence of a unique pattern of 16 channel bits based on the parallel output from the shift register 3.
When the unique pattern is detected, the counter of the count & decode circuit 6 that counts the clock from the crystal oscillator 5 is reset at the detection cycle of the unique pattern, and a clock window signal C covering the clock pit before synchronization is established based on the count output. To decode.

Since the window signal C is generated by counting the clock from the crystal oscillator 5, the window signal C is not synchronized with the reproduced signal.
It fluctuates before and after the clock pit as shown in FIG.

The switching circuit 7 outputs a synchronization establishment signal H from the synchronization control circuit 12.
The signal of C is supplied to the clock sampling circuit 8 before synchronization is established. The clock extraction circuit 8 extracts the clock pit portion of the servo mark from the noise pulse elimination signal B from the noise pulse elimination circuit 2 and sends the clock pit to the phase comparison circuit 9 and the synchronization control circuit 12 as shown in FIG. A pit signal E is supplied.

The synchronization control circuit 12 determines whether or not synchronization has been established. When the clock pit signal E extracted from the clock window signal C before synchronization is input for a specified number of consecutive times, it is determined that synchronization has been established. Is switched from the clock window signal C before the synchronization is established to the clock window signal D after the synchronization is established.

A phase comparator 9 counts a clock sampling signal E and a reproduced clock signal G output from a voltage controlled oscillator (VCO) 10 by a count & decode circuit 11 to generate a window signal D. Then, the input voltage to the voltage controlled oscillator 10 is changed according to the phase error. The voltage-controlled oscillator 10 controls the oscillation frequency in accordance with the input voltage, whereby the reproduction clock is applied to the PLL by the clock pit embedded in the optical disk.

FIG. 3 is a block diagram showing details of the noise pulse elimination circuit 2 shown in FIG. 1, in which 31 is a latch circuit, and 32 is an AND circuit.

3, a latch circuit 31 latches a peak detection signal A obtained by detecting a peak of the reproduced signal shown in FIG. 1 by a clock output from the crystal oscillator 5 shown in FIG. The AND circuit 32 takes the logical product of the latch output signal A 'and the peak detection signal A to obtain a noise removal signal B.

FIG. 4 shows an example of a signal waveform of each part in FIGS. 1 and 3.

In FIG. 4, the noise superimposed on the reproduced signal also appears in the peak detection signal A by the peak detection circuit 1, but the latch circuit 31 responds to this noise with the crystal oscillator 5
, The data is erased from the latch output. The noise elimination signal B is an AND of the latch output signal A 'and the peak detection signal A, and the noise is eliminated. The rising edge of the pulse fluctuates in synchronization with the clock from the crystal oscillator, but is synchronized with the reproduction signal. Therefore, the falling edge of the clock pit signal E extracted by the window signals C and D can be used as a phase comparison input of the phase comparator 9 in FIG.

As described above, according to the present embodiment, even if noise is superimposed on the reproduced signal and a pulse due to the noise is generated in the peak detection signal, the noise is removed because the signal is latched by the clock from the crystal oscillator, and the phase of the PLL can be reduced. Since the comparison is performed at the fall of the original clock pit peak detection signal, erroneous detection of clock pits due to noise, disturbance of synchronization, jitter, and the like can be reduced.

〔The invention's effect〕

According to the present invention, the noise superimposed on the reproduction signal is removed by the noise removal means, so that the clock pit extraction is not disturbed by the noise, and accurate synchronous reproduction by the embedded clock can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronizing signal reproducing circuit of an optical disk device according to the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG. FIG. 4 is a detailed block diagram, FIG. 4 is a signal waveform diagram of each part in FIGS. 1 and 3 when noise of a reproduced signal is superimposed, and FIG.
The figure is an explanatory diagram showing a configuration example of a 3.5 inch DBF format,
It is. DESCRIPTION OF SYMBOLS 1 ... Peak detection circuit, 2 ... Noise pulse removal circuit, 3 ... Shift register, 4 ... Unique pattern detection circuit, 5 ... Crystal oscillator, 6 ... Count & decode circuit, 7 ... Switching circuit, 8 …… Clock pit extraction circuit, 9 …… Phase comparison circuit, 10 …… Voltage controlled oscillator, 11 …… Count & decode circuit, 12 …… Synchronous control circuit, 31 …… Latch circuit, 32 …… And circuit.

Continuation of the front page (56) References JP-A-1-212918 (JP, A) JP-A-58-57635 (JP, A) JP-A-61-253674 (JP, A) JP-A-59-67731 (JP, A) , A) JP-A-2-162578 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11B 20/10 G11B 20/14

Claims (3)

(57) [Claims] 1. A synchronous signal reproducing circuit of an optical disk apparatus for detecting a clock pit periodically embedded on a disk track and reproducing a synchronous signal based on the detected clock pit, wherein the reproduction is performed from the disk track. A peak detecting means for detecting a peak position of a signal and generating a pulse synchronized therewith as a peak detecting signal; and a noise pulse removing means for removing a pulse within a specific period as noise from the peak detecting signal generated by the peak detecting means. Means, a clock pit extracting means for extracting a pulse by a clock pit from the peak detection signal after the noise removal, and a PLL (Phase Locked) comprising a clock arriving cycle of the clock pit extracted by the clock pit detecting means.
Loop) circuit, pseudo clock generation means for generating a pseudo clock, and clock switching means for switching a clock used to generate a window signal used when the clock pit extraction means extracts a pulse due to the clock pit. In the synchronous signal reproducing circuit of the optical disk device, the window signal is created using the pseudo clock until the clock pit extracting unit extracts a pulse based on the clock pit, and the clock pit extracting unit generates the window signal. Wherein the window signal is generated by using the output of the PLL circuit after the pulse is extracted by the synchronous signal reproducing circuit. 2. The synchronous signal reproducing circuit according to claim 1, wherein said noise pulse removing means latches a peak detection signal generated by said peak detecting means, and a latch output from said latch means. An AND circuit for performing an AND operation with the peak detection signal generated by the peak detection means, and the output of the AND circuit is used as a peak detection signal from which noise pulses have been removed. Synchronous signal reproduction circuit. 3. A synchronous signal reproducing method for reproducing a synchronous signal obtained by extracting a pulse of a clock pit from a reproduced signal obtained by reproducing a disk track including a clock pit periodically embedded therein. The clock pit pulse is extracted from the reproduction signal using a window signal generated by counting the pseudo clock, and a synchronization signal is reproduced using the extracted clock pit pulse. Extracting the pulse of the clock pit from the reproduced signal using a window signal generated by counting a clock reproduced by a PLL from the reproduced signal, and synchronizing using the extracted pulse of the clock pit. A method for reproducing a synchronous signal, comprising reproducing a signal.