JPH04153954A - Synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To eliminate the extraction of a clock pit from being disturbed due to noise and to realize an accurately synchronous reproducing by means of a embedded clock by eliminating noise impressed on a reproducing signal by means of a noise eliminating means. CONSTITUTION:A latch circuit 31 latches a peak detection signal A with a clock outputted from a crystal generator 5 and an AND circuit 32 obtains a noise eliminating signal B by ANDing a latch output signal A' and the peak detection signal A. That is, although the noise impressed on the reproducing signal appears in the peak detection signal A due to a peak detection circuit 1, it is eliminated from the latch output for the latch circuit 31 latches the noise by means of the clock from the crystal generator 5. Thus, the noise can be eliminated, erroneous detection of the clock pit, the disturbed synchronization or jitter, etc., can be reduced and the accurate synchronization signal can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to synchronous playback of an optical disc drive device.
In particular, DBF (Discre
The present invention relates to a synchronization signal extracting means suitable for reproducing synchronization signals of the TEBlock Format) system.

[Prior Art] Recording and reproducing devices that use optical discs and are capable of large-capacity recording and have excellent portability are being supplied to the market, mainly 5.25-inch discs. As one of the recording formats for this optical disc, a format called a sample servo method or a DBF method has been proposed. In this format, servo marks are preformatted at specific intervals on concentric circles or spiral tracks on the disk, and the servo mark signals obtained periodically as the disk rotates are used for clock control and tracking control. , focus control and access control.

A clock extracting means compatible with an optical disc of such a format is disclosed in Japanese Patent Laid-Open No. 63-94731. The format shown here is the 5.25-inch standard, but the DBF format proposed for 3.5-inch
Similarly, in the format, servo marks are composed of wobble pits, clock pits, and access marks.

FIG. 5 is an explanatory diagram showing an example of the configuration of the 3.5-inch DBF format. In the 3.5-inch DBF format, one track has 22 sectors, and one sector consists of 76 segments.

The first three segments of the sector are areas in which identification codes and control data for tracks, sectors, etc. are recorded.

One segment has a data length of 10 bytes, of which the first 2 bytes are allocated to a servo mark. 1
The data length of a byte is composed of 11 channel bits, and the data portion excluding the servo mark is modulated and recorded by 4711 such that 4 channel bits out of 11 channel bits are marks and the rest are spaces. The servo mark is composed of an access mark, a clock pit, and a wobble pit, and is used for access control, clock reproduction control, and tracking control, respectively. The access mark is a 3 out of 6 Gray code and changes every track at 16 track cycles.

The clock pit and wobble pit always exist in the same position, with the clock pit located at the center of the track, and the pair of wobble pits located one distance from the center of the track in opposite directions.
The position is shifted by 74 tracks. A sector mark exists only in the first segment of a sector and has a unique distance of 16 channel bits followed by a spacer and 471 bits.
One modulation is 2 bytes long with nine patterns.

[Problem to be solved by the invention]

Clock reproduction as a synchronization signal extracting means of the DBF system having such a format is performed by extracting clock pits of servo marks embedded in the disk and using these clock pit signals as a reference. For this reason, the extraction of clock pits must be accurate, but there are problems such as noise causing false pulses around the clock pits to be erroneously synchronized, or noise to disturb synchronization once it has been pulled in, resulting in an increase in jitter. Something happened.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a BF type synchronization signal extraction means that can reduce erroneous clock pit detection, synchronization disturbance, jitter, etc. due to noise.

[Means to solve the problem]

In order to achieve the above object, the present invention is provided with noise pulse removing means for removing pulses within a specific period of the 8-power signal of the peak detection circuit that detects the peak of the reproduced signal as noise pulses.

[Effect]

The peak detection circuit detects the peak of the reproduced signal and outputs a peak detection signal. The latch circuit latches the peak detection signal using a clock (pseudo clock) from a crystal oscillator to remove noise superimposed on the peak detection. The AND circuit outputs the logical product of the peak detection signal and the output latched by the latch circuit. Since the clock pit is extracted from the output signal from the AND circuit, the noise of the peak detection signal is removed by the latch circuit, and the phase comparison of the PLL is based on the falling edge of the peak detection signal of the clock pit. Disturbances in clock reproduction due to noise can be reduced and jitter can be reduced.

〔Example〕

The present invention will be explained in detail below.

FIG. 1 is a block diagram showing an embodiment of a synchronization signal extracting means of an optical disc device according to the present invention.

In FIG. 1, 1 is a peak detection circuit that detects the peak position based on the reproduced signal from the optical disk, 2 is a noise pulse removal circuit that removes noise in the reproduced signal that appears in the peak detection signal, 3 is a shift register, and 4 is a unique A pattern detection circuit, 5 a crystal oscillator with the same frequency as the clock frequency, 6 a counting and decoding circuit for counting the frequency, 7 a switching circuit, and 8 a clock pit extraction circuit.

9 is a phase comparator, and 10 is a voltage controlled oscillator (VCO).

11 is a count and decode circuit that counts clocks output from the VCO, and 12 is a synchronization control circuit.

Further, FIG. 2 shows signal waveforms of each part shown in FIG. 1.

First, the general operation of the synchronization signal extracting means of the present invention will be explained using these figures. In FIG. 1, a reproduced signal from an optical disk is differentiated by a peak detection circuit 1, and a peak detection signal A is outputted so that a pulse is located at the peak position of the reproduced signal as shown in FIG. Peak detection signal A
is input to the noise pulse removal circuit 2, which outputs a noise pulse removal signal B superimposed on the reproduced signal as described later.

The noise pulse removal signal B is input to the cyst register 3, and is shifted by a 2-byte length of 22 channel bits by a clock from a crystal oscillator 5 which oscillates a clock having the same frequency as the pit clock frequency. Unique pattern detection circuit 4
detects the existence of a unique pattern of 16 channel bits from the parallel output from shift register 3, so
When a unique pattern is detected, the counter of the count & decode circuit FI&6 that counts the clock from the crystal oscillator 5 is reset at the unique pattern detection cycle.
From this count output, a clock window signal C that covers the clock pit before synchronization is established is decoded.

Since this window signal C is generated by counting the clock from the crystal oscillator 5, it is not synchronized with the reproduction signal and therefore fluctuates before and after the clock pit as shown in FIG. 2(d).

The switching circuit 7 receives the synchronization establishment signal H from the synchronization control circuit 12.
This is used to switch the clock pit window signal, and before synchronization is established, the C signal is supplied to the clock sampling circuit 8. The clock sampling circuit 8 extracts the clock pit portion of the servo mark from the noise pulse removal signal B from the noise pulse removal circuit 2, and outputs the clock to the phase comparison circuit 9 and the synchronization control circuit 12 as shown in FIG. A pit signal E is supplied.

The synchronization control circuit 12 is a circuit that determines whether or not synchronization has been established. When the clock pit signal E extracted from the clock window signal C before synchronization is inputted consecutively a certain number of times, it is determined that synchronization has been established, and the switching circuit 7 The clock window signal C is switched from the clock window signal C before synchronization is established to the clock window signal C after synchronization is established.

The phase comparison circuit 9 counts the clock sampling signal E and the reproduced clock signal G output from the voltage controlled oscillator (VCO) 10 using a count & decoding circuit 11, and compares which phase of the clock comparison signal F corresponds to the arrival period of the clock pit. Then, the input voltage to the voltage controlled oscillator 10 is changed in accordance with the phase error.

The voltage controlled oscillator 10 controls the oscillation frequency in response to this input voltage, and a recovered clock is generated from this.

PLL by tarok pit embedded in optical disk
It will cost.

FIG. 3 is a block diagram showing details of the noise pulse removal circuit 2 shown in FIG. 1, where 31 is a latch circuit and 32 is an AND circuit.

In FIG. 3, a latch circuit 31 latches a peak detection signal A obtained by detecting the peak of the reproduced signal shown in FIG. 1 using a clock output from the crystal oscillator 5 shown in FIG.

The AND circuit 32 performs the logical product of the latch output signal A' and the peak detection signal A to obtain the noise removal signal B.

FIG. 4 shows an example of signal waveforms at each part in FIGS. 1 and 3.

In FIG. 4, the noise superimposed on the reproduced signal also appears in the peak detection signal A by the peak detection circuit 1.
Since the latch circuit 31 latches this noise using the clock from the crystal oscillator 5, it is erased from the latch output. The noise removed signal B is an AND of this latch output signal A' and the peak detection signal A, and noise is removed, and although the rise of the pulse fluctuates in synchronization with the clock from the crystal oscillator, it is synchronized with the reproduced signal. So,
Tarokku pit signal E extracted at window signals C and D
The falling edge of can be used as the phase comparison input of the phase comparator 9 in FIG.

As explained above, according to this embodiment, even if noise is superimposed on the reproduced signal and a pulse due to the noise is generated in the peak detection signal, the noise can be removed because it is latched with the clock from the crystal oscillator, and the PLL phase Since the comparison is performed at the falling edge of the original clock pit peak detection signal, it is possible to reduce erroneous detection of tarock pits, synchronization disturbance, jitter, etc. due to noise.

〔Effect of the invention〕

According to the present invention, since the noise superimposed on the reproduced signal is removed by the noise removing means, the extraction of clock pits is not disturbed by the noise, and accurate synchronous reproduction using the embedded clock can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronization signal extracting means of an optical disc device according to the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, and FIG. 3 is a diagram of the noise pulse removal circuit of FIG. 1. Detailed block diagram, Figure 4 is a signal waveform diagram of each part in Figures 1 and 3 when noise is superimposed on the reproduced signal, and Figure 5 is a detailed block diagram.
The figure is an explanatory diagram showing a configuration example of a 3.5-inch DBF format. DESCRIPTION OF SYMBOLS 1... Peak detection circuit, 2... Noise pulse removal circuit, 3... Shift register, 4... Unique pattern detection circuit, 5... Crystal oscillator, 6... Count & decode circuit, 7 ...Switching circuit, 8.. Clock pit extraction circuit, 9.. Phase comparison circuit, 10.. Voltage controlled oscillator, 11.. Count & decoding circuit, 12.. Synchronous control circuit, 31..・Latch circuit,
32...AND circuit. Minzushima <h) 7a-/Meiben U Mouth LI Ll ml U Lo eyes u
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Claims (1)

[Claims] 1. A synchronization signal reproducing circuit for an optical disc device that detects clock pits periodically embedded in a disc track and reproduces a synchronization signal based on the clock pits, the circuit comprising: Peak detection means for detecting the peak position of a reproduced signal and generating a pulse synchronized with the peak detection signal as a peak detection signal; clock pit extraction means for extracting clock pits from the peak detection signal; and arrival period of the extracted clock pits. PLL (
PhaseLockedLoop) circuit,
In a synchronization signal reproducing circuit of an optical disk device that uses the output of the PLL circuit as a reproduction synchronization signal, a noise pulse removal means is provided for removing pulses within a specific cycle as noise from the peak detection signal generated by the peak detection means. A synchronous signal reproducing circuit characterized by: 2. The synchronization signal reproducing circuit according to claim 1, further comprising: a pseudo clock generation means; and a synchronization signal extraction means for extracting a synchronization control signal that periodically arrives from the signal sequence output from the clock pit extraction means. and until the synchronization control signal is extracted by the synchronization signal extraction means,
A window signal used for extracting clock pits by the clock pit extraction means is created using the pseudo clock generated by the pseudo clock generation means, and after a synchronization control signal is extracted by the synchronization signal extraction means. , said P
The window signal is created using the output of the LL circuit, and the noise pulse removing means generates the peak detection signal generated by the peak detection means using the pseudo clock generated from the pseudo clock generation means. and an AND circuit that takes the AND of the latch output from the latch and the peak detection signal generated by the peak detection means, and generates a noise pulse using the output of the AND circuit. A synchronization signal regeneration circuit characterized in that it uses a removed peak detection signal.