JP2000339861A - Information recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the recording of information on a recording medium at a position shown by a preliminarily recorded address. SOLUTION: The preliminary information on a disk 1 is read out by a preliminary information reproducing circuit 10, and an address judged as no error based on the result of the error detection by a 2nd error correction system is set. Then, the address specified on the disk 1 and the set address are compared, and when both addresses coincide, the production start of the information to record on the disk 1 is controlled after the lapse of the prescribed time delay, and the control is made so as to record the information from the specified address on the disk 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information recording apparatus such as an optical disk recording apparatus for recording information in accordance with an address previously recorded as preliminary information on an information recording medium such as an optical disk.

[0002]

2. Description of the Related Art Conventionally, an information recording apparatus (for example, a method and apparatus for additionally recording data on a DVD-R for reading out information recorded on a disc, detecting the end of old information, and additionally recording new information). JP-A-9-270171).

[0003] Further, a phase modulation circuit used in the information recording apparatus as described above (for example, edited by Iwao Yamamoto, published by Sanbo, Inc.
-47, Author: Yasushi Inaba Publisher: CQ Publishing Co., Ltd. 232-233).

[0004]

However, the conventional information recording apparatus as described above has the following problems. (1) The first time recording is performed on a disk (recording medium), the recording position on the disk becomes inaccurate. (2) Information cannot be recorded at any accurate position on the disk.

In the above-described conventional phase modulation circuit, since an analog circuit is used for demodulation of the phase modulation signal, integration into a digital IC cannot be performed, and power consumption and space can be reduced. There was a problem that it was difficult.

[0006] The present invention has been made in view of the above points, and has as its first object to enable information to be recorded at a position indicated by an address recorded in advance on a recording medium. It is a second object of the present invention to correctly generate a predetermined delimiter signal when reading preliminary information recorded on a recording medium in advance.

It is a third object of the present invention to detect an address previously recorded on a recording medium and to easily adjust the alignment when recording information at a predetermined position on the recording medium. I do. It is a fourth object of the present invention to remove noise other than a signal indicating necessary information when reading preliminary information recorded in advance on a recording medium. It is a fifth object of the present invention to enable a digital circuit to demodulate preliminary information recorded on a recording medium by a phase modulation method.

[0008]

In order to achieve the first object, the present invention performs predetermined signal processing on information divided for each error correction unit by a first error correction method, and An information recording apparatus that generates information consisting of a unit of (i) and records the preliminary information including a predetermined address processed by the second error correction method on a recording medium in which the preliminary information is recorded in advance. Preliminary information reading means for reading, error detecting means for performing error detection by the second error correction method, and counting means for setting an address determined as having no error based on the result of error detection by the error detecting means; Comparing means for comparing the designated address on the recording medium with the address set in the counting means, and a predetermined time when the addresses match by the comparing means. Controls the generation start of the information to be recorded on the recording medium after being subjected to a rolling, to provide an information recording apparatus provided with a control means for controlling so as to record information from a predetermined address on the recording medium.

[0009] Further, a predetermined signal processing is performed on the information divided for each error correction unit according to the first error correction method to generate information composed of a plurality of units, and the information is processed by the second error correction method. An information recording apparatus for recording on a recording medium in which spare information including a predetermined address is recorded in advance, the spare information reading means for reading the spare information on the recording medium, and performing error correction by a second error correction method Error correcting means, counting means for setting an address determined to be correct based on the result of error correction by the error correcting means, and an address designated on the recording medium and an address set in the counting means. A comparison unit for comparing, and when both addresses match by the comparison unit, start of generation of information to be recorded on the recording medium after a predetermined time delay is controlled. And, better to the information recording apparatus provided with a control means for controlling so as to record information from a predetermined address on the recording medium.

Next, in order to achieve the second object,
In the information recording apparatus as described above, the spare information reading means includes a synchronization signal detecting means for detecting a synchronization signal, and a first and a second means for circulating a numerical value corresponding to a time interval of the synchronization signal.
And when the value of the first counting means is a first predetermined value when the synchronizing signal is detected by the synchronizing signal detecting means, a second predetermined value is added to the second counting means. Is set and a third predetermined value is set in the first counting means, and the value of the first counting means when the synchronization signal is detected by the synchronization signal detection means is not the first predetermined value. Means for setting a third predetermined value in the first counting means, and in any case controlling the generation of a predetermined delimiter signal of the preliminary information based on the numerical value of the second counting means. It is a thing.

Further, in order to achieve the third object,
In the information recording device as described above, the control unit includes:
A means for externally setting a value corresponding to a predetermined time delay is provided.

Further, in order to achieve the fourth object, in the information recording apparatus as described above, a means for controlling the preliminary information reading means so as not to input a signal outside the time of the signal indicating the preliminary information. Is provided.

Further, in order to achieve the fifth object, in the information recording apparatus as described above, when preliminary information is recorded on the recording medium by a phase modulation method, a phase demodulation means by a digital circuit is used. This is to read the preliminary information on the recording medium.

[0014]

Embodiments of the present invention will be specifically described below with reference to the drawings. The data format of the recording information on the recording medium in this embodiment uses a known technique (for example, it is the same as the format of FIGS. 1 and 2 described in Japanese Patent Application Laid-Open No. 9-270171).

First, preliminary information to be recorded in advance on a disk as a recording medium will be described. In the disc in this embodiment, a groove for recording information (“groove”) is used.
ove) ") meandering (" wobbl "
e) "), and at the time of information recording,
Servo control is performed so that the meandering frequency is constant, and the disk is rotated at a constant linear velocity. Alternatively, the disk is rotated at a constant rotation speed, and information is recorded and reproduced in synchronization with the detected wobble signal.

The address of the preliminary information on the disk is recorded by phase modulation of the wobble signal. FIG.
FIG. 3 is a diagram illustrating an example of a wobble signal in which digital data is recorded by phase modulation.

As shown in the figure, a wobble signal having 93 cycles corresponds to, for example, two sync frames shown in FIG. 2 of Japanese Patent Application Laid-Open No. 9-270171, and preliminary information is recorded in the first eight cycles. You.

First, in the first four periods, a periodic signal ((1) in FIG. 10) indicating an error correction unit of preliminary information and a synchronization signal ((2) and (3) in FIG. 10) for every two sync frames are used. Show.
Further, the last four periods indicate data for each bit of the preliminary information. Furthermore, it indicates that there is no information after the synchronization signal indicating the error correction unit of the preliminary information.

[0019] Then, when the latter two periods ((1) in the figure) are in opposite phase, it is set to "0" ((2)), and when the first two periods are in opposite phase, it is set to "1" ((1)). (3). In this way, 1-bit preliminary information is recorded in two sync frames.

FIG. 11 is a diagram showing a data structure in which 13-bit data in one sector (26 sync frames) is represented by four sectors (52 bits). here,
Four bits are one word, and thirteen words are one error correction unit.

The bit (bit) 0 is data following the synchronization signal indicating the error correction unit of the preliminary information, but is defined here as "0". Of the first six words, the lower 22 bits (bit 2 to bit 23) indicate an address, the next two words indicate control information, and the last five words indicate parity data for error correction.

Next, the configuration of the information recording apparatus according to one embodiment of the present invention will be described. FIG. 1 is a functional block diagram showing a schematic configuration of an information recording apparatus according to an embodiment of the present invention.

This information recording device is realized by a microcomputer including a CPU, a ROM, a RAM, and the like, and the disk 1 is an information recording medium for recording information such as an optical disk. The spindle motor 2 is a motor that rotates the disk 1. The pickup 3 irradiates the disk 1 with a laser beam, detects the reflected light, and optically records and reproduces data on the disk 1.

The laser control circuit 4 controls emission of a laser diode in the pickup 3. The encoder 5 converts information to be recorded on the disk 1 into a predetermined format. The servo circuit 6 performs focus control and tracking control of the spindle motor 2 and the pickup 3.

The reproduction amplifier circuit 7 amplifies the output signal from the pickup 3 and outputs various signals such as an information signal and a wobble signal. The decoder 8 restores the information signal reproduced from the disk 1 to the original data.

The interface 9 connects a computer (not shown), and controls data transfer between the computer, the encoder 5 and the decoder 8. The preliminary information reproducing circuit 10 reproduces preliminary information from the wobble signal read from the disk 1.

FIG. 2 is a functional block diagram showing the internal configuration of the spare information reproducing circuit 10 of FIG. The demodulation circuit 11 of the preliminary information reproducing circuit 10 demodulates the phase-modulated wobble signal and outputs it as a digital signal. PLL circuit 1
2 is a wobble clock (Wo) synchronized with the wobble signal.
bble clock) and a clock of the information bit frequency.

A first synchronizing signal detecting circuit (described as "synchronizing signal detecting circuit 1" in the figure) 13 detects a synchronizing signal for every two sync frames. A second synchronization signal detection circuit (described as “synchronization signal detection circuit 2” in the figure) 14 detects a synchronization signal of the error correction unit of the preliminary information.

A first synchronous distance counter (referred to as "synchronous distance counter 1" in the figure) 15 is a predetermined value (a third predetermined value according to claim 3 of the present invention) every time a synchronous signal is detected.
Set. The second synchronous distance counter (described as “synchronous distance counter 2” in the figure) 16 is a predetermined value (a third predetermined value according to claim 3 of the present invention) every time a synchronous signal is detected
Set.

The first determining circuit (referred to as "determining circuit 1" in the figure) 17 determines that the first synchronous distance counter 15 when detecting the synchronous signal has a predetermined value (the first synchronous distance counter 15 according to the third aspect of the present invention).
), A wobble counter (Wobble counter)
A predetermined value (a second predetermined value according to claim 3 of the present invention) is set in the counter 19. The second determination circuit (described as “determination circuit 2” in the figure) 18 determines that the second synchronization distance counter 16 when detecting the synchronization signal has a predetermined value (the first predetermined value according to claim 3 of the present invention). ), The bit counter 2
A predetermined value (a second predetermined value according to claim 3 of the present invention) is set to 0. The first and second counting means according to claim 3 of the present invention correspond to a combination of the fifteen synchronous distance counters 1 and the nineteen wobble counters shown in FIG. Further, the 16 synchronous distance counters 2 and 20 bit counters shown in FIG. 2 also correspond to the first and second counting means as a part of the second combination.

The wobble counter 19 counts the wobble clock and outputs a carry (carry signal) every 93 cycles. The bit counter 20 counts the bits of the preliminary information and outputs a carry every 52 periods.

The address counter 21 counts addresses in the preliminary information. The gate generation circuit 22 generates a gate signal for extracting only the demodulated digital signal of the first eight cycles of the wobble signal. The data detection circuit 23 detects 1-bit data every two sync frames.

The serial / parallel conversion circuit 24 converts the detected 1-bit data into 4-bit parallel data. The error detection circuit 25 performs a predetermined error detection process. The address data register 26 holds address data (22 bits) based on the preliminary information.

A first register (described as "register 1") 27 sets an address based on preliminary information to be detected. The address comparison circuit 28 compares the value of the first register 27 with the value of the address counter 21.

After the addresses match, the delay circuit 29
After a clock delay of the value set in the second register 30, a start signal is output to the encoder. A second register (described as “register 2”) 30 sets a delay amount (the number of clocks).

Next, the operation of the information recording apparatus for reproducing the preliminary information on the disk 1 and recording the information on the disk 1 in accordance with the address will be described. First, in FIG. 1, the encoder 5 is stopped, and the laser output of the pickup 3 is set in a data reading state. The disk 1 is rotated by the spindle motor 2, the output signal from the pickup 3 is amplified by the reproduction amplifier circuit 7, and a predetermined signal is output.

The servo circuit 6 receives a wobble signal and the like from the reproducing amplifier circuit 7 and rotates the spindle motor 2 at a constant linear velocity. Alternatively, the disk 1
To rotate. At the same time, tracking servo control and focus servo control of the pickup 3 are performed. In addition, means for moving the pickup 3 in the radial direction of the disk 1 (not shown) enables tracking of tracks on the disk 1 and high-speed seeking of data.

The wobble signal output from the reproduction amplification circuit 7 is input to the preliminary information reproduction circuit 10 and converted into a demodulated digital signal by the demodulation circuit 11 shown in FIG.
At the same time, the PLL circuit 12 generates a wobble clock signal synchronized with the wobble signal and a clock signal having a bit frequency on the disk 1 for information to be recorded in the groove.

First, the first synchronizing signal detection circuit 13 detects a synchronizing signal every two sync frames, and synchronizes the first synchronizing distance counter 15. FIG. 3 is a diagram showing a signal waveform related to the wobble counter 19. Here, “9” is set in the next wobble clock cycle after detecting the synchronization signal.

Further, even if a false synchronizing signal (x) is detected before two sync frames elapse, the first synchronous distance counter 1
5 are synchronized. After that, correct synchronization signal (○)
Since the distance counter indicates “8” at the second detection when the detection is performed consecutively, the detected synchronization signal can be determined to be correct, and “9” is set to the wobble counter 19 in the next wobble clock cycle. After setting, the wobble counter 19 is synchronized. On the other hand, if a correct synchronization signal cannot be detected, the wobble counter 19 continues counting.

In this manner, the first determination circuit 17 determines that the distance of the detected synchronization signal is two sync frames, and then synchronizes the wobble counter 19 to cope with erroneous detection of the synchronization signal or omission of detection. are doing.

The wobble counter 19 outputs a carry (carry) to the bit counter every 93 cycles (corresponding to two sync frames). In the bit counter 20,
It counts up each time a carry is input, and outputs a carry to the address counter 21 every 52 cycles. When the second synchronization signal detection circuit (synchronization signal detection circuit 2) 14 detects a synchronization signal for each error correction unit, the second synchronization distance counter 16 is synchronized.

FIG. 4 shows the bit counter 20 shown in FIG.
FIG. 4 is a diagram showing a waveform of a signal related to FIG. The second synchronous distance counter 16 counts up in parallel with the bit counter 20. Similarly to the wobble counter 19, the first synchronous distance counter 15, and the first determination circuit 17, when the distance between two consecutively detected synchronous signals is 52 periods,
The bit counter 20 is synchronized.

In the waveform example shown in FIG. 4, when the synchronization signal is detected, if the second synchronization distance counter 16 is "0", the second determination circuit 18 sets the bit counter 20 to "0". ing.

On the other hand, the gate generation circuit 22 decodes the output value of the wobble counter 19 and generates a gate signal for extracting a signal of only the first eight wobble periods of two sync frame periods.

FIG. 5 shows the gate generating circuit 22 shown in FIG.
FIG. 5 is a diagram showing a signal waveform generated by the above. The logical product (AND) of the gate signal and the demodulated digital signal is input to the data detection circuit 23. Thereby, unnecessary noise can be removed.

The data detection circuit 23 detects 1-bit data for every two sync frames, and converts it into 4-bit parallel data by the serial-parallel conversion circuit 24 at the subsequent stage.
Thirteen words, which are error correction units, are input to the error detection circuit 25, and error detection is performed. At the same time, 22 bits indicating the address are held in the address data register 26.

Only when there is no error as a result of the error detection processing, the value of the address data register 26 is set to the address counter 21. Thus, even if the read address data is incorrect, a correct address can be obtained by counting up the address counter 21.

An address comparison circuit 28 compares the value of the address counter 21 with the address set in the first register 27.
When the two addresses match, a start signal is output to the delay circuit 29.

FIG. 6 is a diagram showing an internal configuration of delay circuit 29 shown in FIG. FIG. 7 shows the delay circuit 2 shown in FIG.
9 is a diagram illustrating an example of an output signal of each unit in FIG. When a start signal is input to the down counter 31, the delay circuit 29 sets the value set in the second register 30 to the down counter 31, and starts counting down.

In the signal waveform shown in FIG. 7, the set value of the second register 30 is "4". The decoder 32 detects that the counter value has become "1", and outputs it as an encode start signal via a flip-flop 33 to remove glitches.

In response to the encode start signal, the encoder 5 in FIG. 1 starts operating, converts data input from the interface 9 into a predetermined format, and inputs the data to the laser control circuit 4. The laser light modulated by the laser control circuit 4 causes the disk 1
The information is recorded in

The value set in the second register 30 is determined based on the wobble signal on the disk 1 in consideration of the delay time in the reproducing amplifier circuit 7, the spare information reproducing circuit 10, the encoder 5, the laser control circuit 4, and the pickup 3. It is determined so that the position matches the information to be recorded.

As described above, the disc 1 is set in accordance with the address previously recorded on the disc 1 as preliminary information.
Information can be recorded in the

In this embodiment, an error detection circuit is used in the spare information reproducing circuit 10. However, the same operation can be performed by replacing this with an error correction circuit. In this case, the value of the address data register is set to the address counter 21 when there is no error and when the error can be corrected.

That is, each of the units performs predetermined signal processing on information divided for each error correction unit according to the first error correction method, generates information including a plurality of units, and generates a second error Means for recording on a recording medium the spare information including a predetermined address processed by the correction method is recorded in advance, means for reading the spare information on the recording medium, and means for error detection by the second error correction method. An error detecting means for performing, an counting means for setting an address determined as having no error based on a result of the error detection by the error detecting means, an address designated on the recording medium, and an address set in the counting means. Comparing means for comparing the address with the address; and information to be recorded on the recording medium after a predetermined time delay when both addresses match by the comparing means. Controls the generation start, functions of the control means for controlling so as to record information from a predetermined address on the recording medium.

Further, preliminary information reading means for reading the preliminary information on the recording medium, error correcting means for performing error correction by the second error correction method, and determination of correctness based on the result of error correction by the error correcting means. Counting means for setting the specified address, comparing means for comparing the designated address on the recording medium with the address set in the counting means, and a predetermined time when the addresses match by the comparing means. It also functions as a control unit that controls the start of generation of information to be recorded on the recording medium after a delay, and controls recording of information from a predetermined address on the recording medium.

Further, the preliminary information reading means includes a synchronizing signal detecting means for detecting a synchronizing signal, and first and second counting means for circulating a numerical value corresponding to a time interval of the synchronizing signal. If the value of the first counting means when the detecting means detects the synchronization signal is a first predetermined value, a second predetermined value is set in the second counting means and the first counting means is set. If the value of the first counting means when the synchronization signal is detected by the synchronization signal detecting means is not the first predetermined value, a third predetermined value is set in the first counting means. In any case, the function of the means for controlling the generation of the predetermined delimiter signal of the preliminary information based on the numerical value of the second counting means is also performed.

The control means also functions as a means for externally setting a value corresponding to a predetermined time delay. Further, the preliminary information reading means also functions as a means for controlling so as not to input the signal outside the time of the signal indicating the preliminary information.

Next, an embodiment of the demodulation circuit 11 using a digital circuit will be described. Although the demodulation circuit 11 shown in FIG. 2 can be realized by an analog circuit as in the related art, it is preferable to configure the demodulation circuit 11 by a digital circuit.

FIG. 8 is a block diagram showing a configuration when the demodulation circuit 11 shown in FIG. 2 is a digital circuit. FIG. 9 is a diagram showing signal waveforms at various points during the operation. In this case, the PLL circuit 41 only needs to generate a clock of the information bit frequency synchronized with the wobble signal. Here, as an example, one wobble cycle is set to 32 cycles.

First, a wobble signal is binarized by a binarization circuit 42, and a first delay circuit 43 (referred to as "delay circuit 1" in the drawing) 43 using a counter operated by a clock is used. EOR (Exclusive OR) processing with a signal delayed by a half wobble cycle is performed.

The fall detection circuit 45 detects the fall of the EOR output signal, delays it by a quarter wobble cycle by a second delay circuit (denoted as "delay circuit 2" in the figure) 46, and then generates a wobble clock generation circuit. (Wobble clock generation circuit) 47 generates a wobble clock. The wobble signal binarized at the rising edge of the clock is held by the flip-flop circuit 48 and inverted and output to obtain a demodulated digital signal.

Further, the generated wobble clock is
The delay circuit (described as “delay circuit 3” in the figure) 49
The wobble clock in FIG. 2 is obtained by delaying four cycles and inverting the output.

That is, when the preliminary information is recorded on the recording medium by the phase modulation method, the preliminary information on the recording medium is read by the phase demodulation means by the digital circuit.

As described above, the information recording apparatus of this embodiment reads the preliminary information on the disk and performs error detection, sets the address when there is no error in the counter, and sets the address when there is an error. Is counted up to generate an address, so that a correct address is always obtained.

Since the start of generation of information to be recorded after a predetermined delay time is controlled by comparing the designated address with the address of the counter, information can be recorded in accordance with the address on the disk. Further, since error correction is not performed and error detection is performed, the circuit scale can be reduced.

If the above error detection function is replaced with an error correction function, the reliability of the read address is improved.

Further, there is provided a distance counter which operates in parallel with a counter for generating a predetermined delimiter signal of the preliminary information, and synchronizes the counter only when the interval between the detected synchronizing signals coincides with a predetermined cycle. Erroneous detection of signals and adverse effects of omission of detection can be eliminated, and stable operation can be provided.

Further, since a value corresponding to a delay time until the start of generation of information to be recorded on the disk is stored in a register which can be set from the outside, the delay time is adjusted even if the encoder or the laser control circuit is changed. And versatility can be obtained.

Further, since a gate signal for extracting only the demodulated digital signal corresponding to the wobble signal of the first eight cycles in two sync frames is generated, noise due to other causes such as a disk defect is generated. Can be removed, and the reliability of reading the preliminary information is improved.

If a demodulation circuit, which was conventionally realized by an analog circuit, is realized by a digital circuit, a digital IC
It is possible to perform integration in a semiconductor device, which is advantageous for low power consumption and space saving.

[0073]

As described above, according to the information recording apparatus of the first and second aspects of the present invention, information can be recorded at a position indicated by an address recorded in advance on a recording medium. Further, according to the information recording apparatus of the present invention, when reading the preliminary information recorded in advance on the recording medium, it is possible to correctly generate the predetermined delimiter signal.

Further, according to the information recording apparatus of the present invention, an address pre-recorded on the recording medium is detected, and the position when the information is recorded at a predetermined position on the recording medium is adjusted. It can be easily adjusted.

According to the information recording apparatus of claim 5 of the present invention, when reading the preliminary information recorded in advance on the recording medium, it is possible to remove noises other than the signal indicating the necessary information.

Further, according to the information recording apparatus of the present invention, the preliminary information recorded on the recording medium by the phase modulation method can be demodulated by the digital circuit.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a schematic configuration of an information recording apparatus according to an embodiment of the present invention.

FIG. 2 is a functional block diagram showing an internal configuration of a spare information reproducing circuit 10 shown in FIG.

FIG. 3 is a diagram showing signal waveforms related to the wobble counter 19 shown in FIG.

FIG. 4 is a diagram showing waveforms of signals related to the bit counter 20 shown in FIG.

5 is a diagram showing a signal waveform generated by a gate generation circuit 22 shown in FIG.

6 is a diagram showing an internal configuration of the delay circuit 29 shown in FIG.

FIG. 7 is a diagram illustrating an example of output signals of each unit in the delay circuit 29 illustrated in FIG. 6;

8 is a block diagram showing a configuration when the demodulation circuit 11 shown in FIG. 2 is a digital circuit.

FIG. 9 is a diagram illustrating signal waveforms of respective units when the demodulation circuit 11 illustrated in FIG. 8 operates.

FIG. 10 is a diagram illustrating an example of a wobble signal in which digital data is recorded by phase modulation.

FIG. 11 is a diagram showing a data configuration in which 13-bit data in one sector is represented for four sectors.

[Explanation of symbols]

 1: Disc 2: Spindle motor 3: Pickup 4: Laser control circuit 5: Encoder 6: Servo circuit 7: Reproduction amplification circuit 8: Decoder 9: Interface 10: Preliminary information reproduction circuit 11: Demodulation circuit 12: PLL circuit 13: First 1 synchronization signal detection circuit 14: second synchronization signal detection circuit 15: first synchronization distance counter 16: second synchronization distance counter 17: first determination circuit 18: second determination circuit 19: wobble counter 20: bit counter 21: address Counter 22: Gate generation circuit 23: Data detection circuit 24: Serial / parallel conversion circuit 25: Error detection circuit 26: Address data register 27: First register 28: Address comparison circuit 29: Delay circuit 30: Second register 31: Gown counter 32: decoder 33: flip-flop 41 PLL circuit 42: binarizing circuit 43: first delay circuit 44: EOR circuit 45: falling edge detection circuit 46: second delay circuit 47: wobble clock generating circuit 48: flip-flop 49: third delay circuit 50: inverter circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 574 G11B 20/18 574H

Claims (6)

[Claims] 1. A predetermined signal processing is performed on information divided for each error correction unit according to a first error correction method to generate information including a plurality of units, and the information is processed by a second error correction method. An information recording device for recording on a recording medium in which spare information including a predetermined address is recorded in advance, the spare information reading means for reading the spare information on the recording medium, and performing error detection by a second error correction method Error detecting means, counting means for setting an address determined as having no error based on the result of error detection by the error detecting means, an address specified on the recording medium and an address set in the counting means Comparing means for comparing the two addresses with each other, and controlling the start of generation of information to be recorded on the recording medium after a predetermined time delay when both addresses match. The information recording apparatus characterized by comprising a control means for controlling so as to record information from a predetermined address on the recording medium. 2. A predetermined signal processing is performed on the information divided for each error correction unit according to the first error correction method to generate information including a plurality of units, and the information is processed by the second error correction method. An information recording apparatus for recording on a recording medium in which spare information including a predetermined address is recorded in advance, the spare information reading means for reading the spare information on the recording medium, and performing error correction by a second error correction method Error correcting means; counting means for setting an address determined to be correct based on the result of error correction by the error correcting means; and a designated address on the recording medium and an address set in the counting means. Comparing means for comparing, when both addresses coincide with each other by the comparing means, controlling generation start of information to be recorded on the recording medium after a predetermined time delay, Information recording apparatus characterized by comprising a control means for controlling so as to record information from a predetermined address on the serial recording medium. 3. The information recording apparatus according to claim 1, wherein said preliminary information reading means includes a synchronization signal detecting means for detecting a synchronization signal, and first and second means for circulating a numerical value corresponding to a time interval of the synchronization signal. A second counting unit, wherein when a value of the first counting unit when the synchronization signal is detected by the synchronization signal detecting unit is a first predetermined value, a second counting unit is provided for the second counting unit. A predetermined value is set, and a third predetermined value is set in the first counting means. When the synchronization signal is detected by the synchronization signal detecting means, the value of the first counting means is equal to the first predetermined value. If not, a third predetermined value is set in the first counting means, and in any case, control is performed such that a predetermined delimiter signal of the preliminary information is generated based on the numerical value of the second counting means. And provided Information recording apparatus characterized and. 4. The information recording apparatus according to claim 1, wherein said control means includes means for externally setting a value corresponding to a predetermined time delay. 5. The information recording apparatus according to claim 1, wherein said preliminary information reading means is provided with means for controlling not to input a signal outside a time period of a signal indicating preliminary information. Information recording device. 6. The information recording apparatus according to claim 1, wherein when the preliminary information is recorded on the recording medium by a phase modulation method, the preliminary information on the recording medium is read by a phase demodulation means using a digital circuit. An information recording device characterized in that: