JPH05189884A - Data synchronizing system - Google Patents

Abstract

PURPOSE:To provide a data synchronizing system in which causes for limiting phase margin can be removed. CONSTITUTION:The data synchronizing system comprises a flip-flop 25 for binary coding the output of photodetector 4 corresponding to the information recoded on an optical disc 2 and generating a binary coded signal having significant rising/falling edges for a signal R'DATA having insignificant falling edge not corresponding to the recorded information passed through a noise mask block 11, and a VFO 26 generating a synchronizing signal which is synchronized with rising/falling edges of the binary coded signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data synchronizing device for generating a data synchronizing signal used for reproducing information recorded on a recording medium.

[0002]

2. Description of the Related Art In recent years, optical recording / reproducing devices such as optical disk devices and magneto-optical recording / reproducing devices have become popular.
In these optical recording / reproducing devices, the output of the detector for taking out the information recorded on the recording medium is a weak analog signal, and is subjected to signal processing such as amplification and conversion into a digital signal corresponding to the information, Output to digital signal processing system. During this processing, if the synchronization is disturbed by noise etc.,
The recorded information cannot be reproduced correctly. Therefore, in order to realize highly reliable signal processing, it is necessary to generate a synchronization signal synchronized with the recording information (data) and perform the signal processing in synchronization with this synchronization signal.

For example, FIG. 10 shows the configuration of a conventional data synchronizing apparatus. An optical head 3 is arranged so as to face an optical disk 2 which is rotationally driven by a spindle motor 1. The optical head 3 is movable by a head moving means such as a VCM in a radial direction of the optical disk 2, that is, a direction traversing a track. You can access any track.

A light beam generating means such as a laser diode (not shown) is housed in the optical head 3, and the light beam is focused and irradiated on the optical disk 2 through an optical system.
The light reflected by the optical disc 2 is received by the photodetector 4 in the optical head 3 and is photoelectrically converted to the optical disc 2
It becomes a reproduction signal corresponding to the data recorded in, and this reproduction signal is inputted to the preamplifier 5 which constitutes the data synchronizing device.

Data is recorded on the optical disk 2 by a short hole recording method (inter-mark modulation recording method). Also,
The photodetector 4 is formed of a plurality of elements, and a track error signal and a focus error signal are generated by performing addition or subtraction processing on the outputs of the plurality of elements.

The signal amplified by the pre-amplifier 5 is further amplified by the amplifier 6, and the signal shown in FIG.
As shown in (a), a signal a which becomes a peak at the short hole portion is obtained, and this signal a is input to the differentiator 7 and the first comparator 8. The signal b shown in FIG. 11B is obtained by being differentiated by the differentiator 7, and this signal b becomes a signal that zero-crosses at the peak of the peak of the signal a, that is, at the center position of the short hole portion.

Further, the first comparator 8 compares it with the reference voltage and binarizes it to generate a signal c shown in FIG. 11 (c). In FIG. 11C, the reference voltage is set to 0. The signal b is the second
Is compared with the reference voltage of 0 by the comparator 9 of
It is binarized to generate the signal d shown in FIG.
The trailing edge of the binarized signal d corresponds to the peak position of the signal a.

The two binarized signals c and d are input to the NAND circuit 10 to generate a signal e whose rising edge corresponds to the peak position of the signal a as shown in FIG. Is input to the noise mask block 11 'for masking the. This noise mask block 1
1 ', a reproduction pulse RDATA having a window width (channel bit length) T having a period twice that of the sync clock fc is generated as shown in FIG. 11 (f). As can be seen from FIG. 11, the rising edge of the reproduction pulse RDATA has the meaning of directly corresponding to the center position of the short hole recording portion,
The falling edge does not correspond to the short hole recording part. The reproduction pulse RDATA is applied to the data input terminal D of the D-flip-flop 12 and is also input to the VFO (variable frequency oscillator) 13.

Reproduction pulse R input to this VFO 13
In synchronization with DATA, the signal g having a cycle of 1/2 of this window width T
Is generated as shown in FIG. This signal g is inverted by the inverter 14, and at that time, the time is slightly delayed to become the sync clock fc shown in FIG. 11 (h), which is output to the subsequent stage as SYNC CLOCK and the clock of the D-flip-flop 12 described above. The reproduction pulse RDATA is applied to the input terminal CK, and the reproduction pulse RDATA is input to the data input terminal D at the rising edge of the sync clock fc.
Sync data SYNC shown in FIG. 11 (i) from the output terminal Q
Outputs DATA.

The sync data SYNC DATA is subjected to signal processing for reproduction at the subsequent stage using the SYNC CLOCK as a synchronization signal, and the data corresponding to the information recorded on the optical disc 2 is demodulated. In this conventional example, a circuit element for determining the window width T in the noise mask block 11 'is used, and the window width T of the reproduction pulse RDATA to the VFO 13 is used.
Is set to the state of the sync clock fc so that the phase margin is maximized.

[0011]

However, in this conventional example, the reproduction pulse RDATA for determining the window width T is set.
The trailing edge that does not correspond to the short hole recording portion is a factor that determines the phase and cycle of the sync clock fc generated by the VFO 13. For example, if the window width T fluctuates, the phase and cycle of the sync clock fc will fluctuate according to this fluctuation, so that (from the rising edge timing directly corresponding to the short hole recording portion) of this falling edge If the timing fluctuates, there is a drawback that the phase margin of data reproduction is narrowed.

That is, since the sync clock fc is generated so that its cycle matches the window width T of the reproduction pulse RDATA, if the period from the rising edge to the falling edge changes, the phase and cycle of the sync clock fc are disturbed. This means that the timing of data reproduction in synchronization with the sync clock fc deviates from the optimum timing, and it becomes impossible to perform data reproduction with a low error rate.

In order to prevent this from occurring, strict performance is required so that the power supply voltage dependency, temperature dependency, variation, etc. of the circuit elements that determine the window width T in the noise mask block 11 'have sufficiently small values. There was a drawback that would be required.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a data synchronization device capable of removing a factor for narrowing a phase margin and performing data reproduction with a small error rate.

[0015]

[Means and Actions for Solving Problems] In order to read the record information recorded on the recording medium and generate the binarized reproduction data corresponding to the record information, a synchronization signal synchronized with the reproduction data is generated. In the data synchronization device to generate,
A binarized signal generation circuit for generating a binarized signal having rising and falling edges having a meaning corresponding to recording information, and a variable for generating a synchronizing signal synchronized with the rising and falling edges of the binarized signal. By providing the frequency oscillator, the binarized signal generated by the binarized signal generation circuit becomes a signal having a meaning corresponding to the record information at both the rising and falling edges thereof, and is synchronized with this binarized signal. As described above, the synchronizing signal generated by the variable frequency oscillator has the factors for narrowing the phase margin removed, and enables data reproduction with few errors.

[0016]

Embodiments of the present invention will be specifically described below with reference to the drawings. 1 to 4 relate to a first embodiment of the present invention, FIG. 1 shows a data synchronization device of the first embodiment, FIG. 2 shows a timing chart of the first embodiment, and FIG. 3 shows a first embodiment. FIG. 4 shows a block structure of a VFO used in the example, and FIG. 4 shows an operation explanatory diagram of the VFO.

In the data synchronizing apparatus 21 of the first embodiment shown in FIG. 1, in the conventional example shown in FIG. 10, the noise mask block 11 'has a D-flip-flop 22 and a delay element 23.
And an inverter 24 (this is shown by a noise mask block 11), a D-flip-flop 25 is interposed between the output of the noise mask block 11 and the D-flip-flop 12, and a VFO 13 shown in FIG. A VFO 26 with different functions is used. Others have the same configuration as the conventional example shown in FIG.

That is, the optical head 3 is arranged so as to face the optical disk 2 which is rotationally driven by the spindle motor 1, and the optical head 3 is a head moving means such as a VCM and the like, which is a radial direction of the optical disk 2, that is, a direction traversing a track. It's mobile and accessible to any track.

A light beam generating means such as a laser diode (not shown) is housed in the optical head 3, and the light beam is focused and irradiated on the optical disk 2 through an optical system.
The light reflected by the optical disc 2 is received by the photodetector 4 in the optical head 3 and is photoelectrically converted to the optical disc 2
It becomes a reproduction signal corresponding to the data recorded in, and this reproduction signal is inputted to the preamplifier 5 which constitutes the data synchronizing device.

Data is recorded on the optical disc 2 by the short hole recording method (inter-mark modulation recording method). Also,
The photodetector 4 is formed of a plurality of elements, and a track error signal and a focus error signal are generated by performing addition or subtraction processing on the outputs of the plurality of elements.

The signal amplified by the preamplifier 5 is further amplified by the amplifier 6, and the signal corresponding to the short hole recording data shown in FIG.
As shown in (a), a signal a which becomes a peak at the short hole portion is obtained, and this signal a is input to the differentiator 7 and the first comparator 8. The signal b shown in FIG. 2B is obtained by being differentiated by the differentiator 7, and the signal b becomes a signal that zero-crosses at the peak of the peak of the signal a, that is, at the center position of the short hole portion.

Further, the first comparator 8 compares it with the reference voltage and binarizes it to generate a signal c shown in FIG. 2 (c). In FIG. 2C, the reference voltage is 0
However, a voltage other than 0 may be used. The signal b is compared with the reference voltage of 0 by the second comparator 9 and binarized to generate the signal d shown in FIG. 2 (d). The trailing edge of the binarized signal d corresponds to the peak position of the signal a.

The two binarized signals c and d are input to the NAND circuit 10 to generate a signal e whose rising edge corresponds to the peak position of the signal a as shown in FIG. The output signal e of the circuit 10 is applied to the data input D of a D-flip-flop 22 forming the noise mask block 11, and this D-flip-flop 22 is applied.
Is applied to the clock input terminal CK of the D-flip-flop 25 at the next stage.

This output signal passes through the delay circuit 23 and the inverter 24, and the clear terminal C of the D-flip-flop 22.
It is also applied to LR, and after a delay time T'of the delay circuit 23 from the rising timing of the signal e, this D-flip-flop 22 is cleared. Therefore, the output signal of the D-flip-flop 22 rises in synchronization with the rising timing of the signal e as shown in FIG.
It becomes a signal R'DATA having a pulse width of T '. In addition,
When the delay time of the inverter 24 is also taken into consideration, the pulse width T ′ has a value including the delay time of the inverter 24.

The delay time (delay amount) of the delay circuit 23 is set to a value approximately equal to the cycle of the sync clock fc, for example. This delay amount does not become a factor that determines the phase and cycle of the sync clock fc in the conventional example (that is, the sync clock fc based on the VFO 26 is synchronized with the signal RDATA instead of the signal R'DATA).
There may be power supply voltage dependency. The noise mask block 11 outputs a signal R′DATA having a pulse width T ′ corresponding to the delay amount of the delay circuit 23 from the rising edge of the input signal e.

Therefore, the value of the pulse width T'has not to be set to one cycle of the sync clock fc, but can be set to any value less than the minimum code length of the recording / reproducing modulation code. For example, in the case of 2-7 modulation, it is good if it is less than 3τ. However, considering the function of the noise mask, it is better to set the value as close to the minimum code length as possible. As the delay circuit 23, a monostable multivibrator or the like may be used instead of the delay line, and in this case, the cost can be reduced.

The signal R'DATA is an inverted output terminal / Q.
Is connected to the data input terminal D and is applied to the clock input terminal CK of the D-flip-flop 25 which divides the frequency by 1/2.
The signal RDATA shown in FIG.
Output to the flip-flop 12. This signal RDATA
Has a meaningful rising and falling waveform in which the rising edge and the falling edge respectively directly correspond to the short hole recording portion (recording information). This signal RDAT
A is also input to the VFO 26 for generating a synchronization signal synchronized with its rising edge and falling edge.

Output signal g of VFO 26 and inverter 1
The output signal fc of 4 is shown in FIGS. 2 (g) and 2 (h), respectively. The output signal fc of the inverter 14 is D
-From this D-flip-flop 12 by applying it to the clock input CK of the flip-flop 12
The sync data SYNC DATA shown in (j) is output. This sync data SYNC DATA will be reproduced at the subsequent stage using the sync clock fc (SYNC CLOCK).

The VFO 26 synchronizes the input signal to the VFO 26 with a synchronizing signal g synchronized with the rising edge and the falling edge (the sync clock fc (S as a synchronizing signal used by inverting the signal g to reproduce data).
YNC CLOCK) is generated), and the circuit configuration is shown in FIG.

As shown in FIG. 3, the reproduction pulse RDATA
Is input to the first phase comparator 31A and also input to the first D-flip-flop 32A. The data of the data input terminal D is latched by the output of the VCO (voltage controlled oscillator) 33 applied to the clock input terminal CK of the D-flip-flop 32A and output to the first phase comparator 31A.

The first phase comparator 31A compares the phases of the two input signals, that is, the phase of the rising edge of the reproduction pulse RDATA and the phase of the signal input from the D-flip-flop 32A, and the phase of the reproduction pulse RDATA. UP signal and reproduction pulse R to be advanced when the delay is later than
If it is ahead of the DATA phase, delay it
The N signal is output to the first charge pump 34A. First
The charge pump 34A uses the reproduction pulse RDATA as a reference signal, and outputs a voltage having a value corresponding to the phase shift of the output of the VCO 33 from the phase and correcting the phase shift of the oscillation output of the VCO 33 to the adder 35. ..

On the other hand, the reproduction pulse RDATA is inverted by the inverter 37 and inverted reproduction pulse / RDATA.
Is generated and input to the second phase comparator 31B and also to the second D-flip-flop 32B.
The clock input terminal CK of this D-flip-flop 32B
The data of the data input terminal D is latched by the output of the VCO 33 applied to the second phase comparator 31B.
The phase comparator 31B compares the phase of the falling edge of the reproduction pulse RDATA with the phase of the signal input from the D-flip-flop 32A, and when it is behind the phase of the reproduction pulse RDATA, advances the UP signal and the reproduction. If it leads the phase of the pulse RDATA, delay it D
The OWN signal is output to the second charge pump 34B.

The second charge pump 34B outputs to the adder 35 a voltage corresponding to the phase shift of the output of the VCO 33 from the phase of the reproduction pulse RDATA. When the addition is performed by the adder 35, the average value of the two input signals may be calculated by halving. A low-pass component is extracted from the signal output added by the adder 35 through a low-pass filter 36 and is input to the VCO 33. The VCO 33 outputs a signal synchronized with the rising and falling edges of the reproduction pulse RDATA.

That is, the reproduction pulse RD shown in FIG.
A rising signal g synchronized with the phase of the rising edge of ATA is generated as shown in FIG.
This signal g is the reproduction pulse / RDATA shown in FIG.
It also becomes a rising signal synchronized with the phase of the rising edge of.

In the VFO 26 of FIG. 3, the outputs of the two charge pumps 34A and 34B are added by the adder 35 and input to the low-pass filter 36. However, the outputs of the charge pumps 34A and 34B are respectively input to the low-pass filter. You may make it add after passing 36. Further, one charge pump may be controlled by the outputs of the two phase comparators 31A and 31B, and in this case, the adder 35 becomes unnecessary.

According to this embodiment, not the binarized signal which does not include the falling edge which does not correspond to the short hole recording portion in the conventional example, but both the rising edge and the falling edge have the meaning corresponding to the short hole recording portion. A signal RDATA as a binarized signal is generated, and this signal RDATA is generated.
Is input to the VFO 26 for generating the sync clock fc, so that it is possible to eliminate the factor that narrows the phase margin (for the falling edge portion that does not correspond to the short hole recording portion in the conventional example). Therefore, it is possible to perform highly reliable signal reproduction processing with a low error rate.

Further, the allowable value for the circuit element that determines the window width of the noise mask block 11 can be increased, and the allowable value for the temperature dependency and the like can be increased. The first embodiment is not limited to an optical disc as a recording medium, but can be used for synchronization when a reproduction signal for magnetic recording such as a magnetic tape or a magnetic disc is generated.

In the first embodiment, the input or output signal to the noise mask block 11 is a portion corresponding to the record information (meaningful) at the rising edge.
The same can be applied to the case where the trailing edge corresponds to the recorded information (for example, the same processing can be performed by passing it through an inverting circuit).

FIG. 5 shows a main part of the data synchronization device 41 of the second embodiment of the present invention. This embodiment differs from the first embodiment in the output format of the sync data SYNC DATA.
In the first embodiment shown in FIG. 1, the output of the D-flip-flop 12 is further input to the D-flip-flop 42 and the exclusive-OR circuit 43. The sync clock SYNCCLOCK is applied to the clock input terminal of the D-flip-flop 42, and this D-
The output of the flip-flop 42 is also input to the exclusive OR circuit 43. Two D-flip-flops 12
, 42 to obtain sync data SYNC from the exclusive OR circuit 43.
DATA is output.

Next, the operation of this embodiment will be described with reference to FIG. As described in the first embodiment, the outputs of the VFO 26, the inverter 14 and the D-flip-flop 25 are as shown in FIG.
The signals g, fc, and RDATA shown in (g) to (i) are obtained, and the output of the D-flip-flop 12 becomes the signal j shown in FIG. 6 (j). This signal j is the signal fc (SYNC C
LOCK) as a clock
Then, the signal k shown in FIG. 6 (k) is obtained.

These two signals j and k are passed through the exclusive OR circuit 43, so that the sync data SYNC having a rising edge has a meaning as shown in FIG. 6 (l).
DATA is output. The operation and effect of the second embodiment are almost the same as those of the first embodiment.

FIG. 7 shows a main part of a data synchronization device 51 according to the third embodiment of the present invention. The first and second embodiments were for synchronizing the reproduction signals corresponding to the short hole recording method, but this embodiment is for reproduction corresponding to the long hole recording (mark length modulation recording) method peculiar to the optical disc. It is for synchronizing the signals.

As shown in FIG. 7, the reflected light of the light applied to the optical disc 2'on which the long hole recording is performed is detected by the photodetector 4, photoelectrically converted, amplified by the preamplifier 5 and the amplifier 6, and then converted into the state shown in FIG. The signal a shown in a) is obtained and is input to the comparator 8. This comparator 8 is compared with the reference voltage to generate a binarized signal c corresponding to the long hole recording length, as shown in FIG. 8B. This signal c is input to the noise mask block 52, noise masked, and then input to the D-flip-flop 25. This D
-The configuration after the flip-flop 25 is the same as that of the first embodiment.

In the short hole recording method of the first embodiment, the input signal e to the noise mask block 11 is the signal portion corresponding to the recording information only at the rising edge portion. Therefore, noise mask processing is performed in the vicinity of this rising edge portion. However, in this embodiment, the noise mask block 5
The input signal c to 2 is a signal portion in which both the rising edge portion and the falling edge portion correspond to the recording information. For this reason, the noise mask block 52 in this embodiment is configured to function on both the rising edge portion and the falling edge portion of the input signal c.

The signal c is subjected to noise mask processing for the rising edge portion (the noise mask block 11 portion shown in FIG. 1) D-flip-flop 22 and delay circuit 23.
In addition to the inverter 24, the inverter 53 and the D-flip-flop 54 for noise masking the falling edge portion, and the OR circuit 55 for ORing the two D-flip-flops 22, 54. Composed. The signal RDATA shown in FIG. 8E is passed through the noise mask block 52 and the D-flip-flop 25.
Is generated. This signal RDATA is further input to the D-flip-flop 12 and latched by the signal fc passed through the VFO 26 and the inverter 14, and the sync data SYNC DATA shown in FIG. 8F is generated. This third
The operation and effect of the embodiment are almost the same as those of the first embodiment.

FIG. 9 shows a part of a data synchronizing apparatus according to the fourth embodiment of the present invention. This embodiment is the same as the third embodiment,
The configuration when no noise mask block is used is shown. As shown in FIG. 9, the output signal c of the comparator 8 is input to the D-flip-flop 12 and the VFO 26. The signal c applied to the data input terminal D of the D-flip-flop 12 is the output signal f of the inverter 14.
It is latched by using c as a clock, and the output terminal Q outputs sync data SYNC DATA. The effect of this embodiment is almost the same as that of the third embodiment.

The present invention is a compact disc as a recording medium related to the optical disc, a write-once optical disc,
Not limited to devices that reproduce from magneto-optical disks, optical cards, magnetic tapes, magnetic disks (floppy disks,
It can be widely applied to devices that play from hard disks).

[0048]

As described above, according to the present invention, a binarized signal generating circuit for generating a binarized signal having a rising edge and a falling edge having a meaning corresponding to recording information, and the binarizing Since the variable frequency oscillating means for generating the synchronizing signal synchronized with the rising and falling edges of the signal is provided, the binarized signal generated by the binarized signal generating circuit is recorded on both the rising and falling edges. The signal has a meaning corresponding to the information, and
The synchronizing signal generated by the variable frequency oscillating means so as to be synchronized with the binarized signal eliminates the factor that narrows the phase margin, and enables highly accurate data reproduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data synchronization device according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a block configuration diagram of a VFO used in the first embodiment.

FIG. 4 is an operation explanatory diagram of VFO.

FIG. 5 is a block diagram showing a configuration of a main part of a second embodiment of the present invention.

FIG. 6 is a timing chart diagram for explaining the operation of the second embodiment.

FIG. 7 is a block diagram showing a configuration of a data synchronization device according to a third exemplary embodiment of the present invention.

FIG. 8 is a timing chart diagram for explaining the operation of the third embodiment.

FIG. 9 is a block diagram showing a configuration of a main part of a fourth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional data synchronization device.

FIG. 11 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 2 ... Optical disc 3 ... Optical head 4 ... Optical detector 5 ... Preamplifier 6 ... Amplifier 7 ... Differentiator 8, 9 ... Comparator 10 ... NAND circuit 11 ... Noise mask block 12, 22, 25 ... Flip-flop 14, 24 ... Inverter 21 ... Data synchronizer 23 ... Delay circuit 26 ... VFO

[Procedure amendment]

[Submission date] October 14, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

A light beam generating means such as a laser diode (not shown) is housed in the optical head 3, and the light beam is focused and irradiated on the optical disk 2 through an optical system.
The light reflected by the optical disc 2 is received by the photodetector 4 in the optical head 3 and is photoelectrically converted to the optical disc 2
Becomes a reproduction signal corresponding to the recorded data, the reproduction signal is input to the preamp 5 constituting the data synchronization unit.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006] The signal amplified by the preamp 5 is further amplified by the amplifier 6, in accordance with Tan'ana recording data 11
As shown in (a), a signal a which becomes a peak at the short hole portion is obtained, and this signal a is input to the differentiator 7 and the first comparator 8. The signal b shown in FIG. 11B is obtained by being differentiated by the differentiator 7, and this signal b becomes a signal that zero-crosses at the peak of the peak of the signal a, that is, at the center position of the short hole portion.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

Reproduction pulse R input to this VFO 13
In synchronization with the DATA signal g in the circumferential phase of the window width T is 11
It is generated as shown in (g). This signal g is inverted by the inverter 14, with a slight time delay at that time.
It becomes the sync clock fc shown in (h), and SY is output to the subsequent stage.
It is output as NC CLOCK and is applied to the clock input terminal CK of the D-flip-flop 12,
At the rising edge of the sync clock fc, the reproduction pulse RDATA to the data input terminal D is fetched and output terminal Q
To the sync data SYNC DAT shown in FIG.
Output A.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

However, in this conventional example, the window width T is one cycle of the sync clock fc.
If deviated, short hole recording part in reproduction pulse RDATA
Falling edge that does not correspond to narrowing the phase margin
It had the drawback that it would end up.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

That is, the pulse width T of RDATA is the sync
RDATA falls when it deviates from one cycle of clock fc
It has the drawback that the sharpness narrows the phase margin.
There is .

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0019

[Correction method] Change

[Correction content]

A light beam generating means such as a laser diode (not shown) is housed in the optical head 3, and the light beam is focused and irradiated on the optical disk 2 through an optical system.
The light reflected by the optical disc 2 is received by the photodetector 4 in the optical head 3 and is photoelectrically converted to the optical disc 2
Becomes a reproduction signal corresponding to the recorded data, the reproduction signal is input to the preamp 5 constituting the data synchronization unit.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The amplified signal by the preamp 5 is further amplified by the amplifier 6, in accordance with Tan'ana recording data 2
As shown in (a), a signal a which becomes a peak at the short hole portion is obtained, and this signal a is input to the differentiator 7 and the first comparator 8. The signal b shown in FIG. 2B is obtained by being differentiated by the differentiator 7, and the signal b becomes a signal that zero-crosses at the peak of the peak of the signal a, that is, at the center position of the short hole portion.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

The reflected light of the light irradiated on the optical disk 2 'long hole printing is performed as shown in FIG. 7 is detected by the light detector 4 is photoelectrically converted, preamp 5, is amplified by the amplifier 6 Figure The signal a shown in 8 (a) is input to the comparator 8. This comparator 8 is compared with the reference voltage to generate a binarized signal c corresponding to the long hole recording length, as shown in FIG. 8B. This signal c is input to the noise mask block 52, noise masked, and then input to the D-flip-flop 25. This D
-The configuration after the flip-flop 25 is the same as that of the first embodiment.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction content]

[0048]

As described above, according to the present invention, a binarized signal generating circuit for generating a binarized signal having a rising edge and a falling edge having a meaning corresponding to recording information, and the binarizing Since the variable frequency oscillating means for generating the synchronizing signal synchronized with the rising and falling edges of the signal is provided, the binarized signal generated by the binarized signal generating circuit is recorded on both the rising and falling edges. The signal has a meaning corresponding to the information, and
The synchronizing signal generated by the variable frequency oscillating means so as to be synchronized with the binarized signal eliminates the factor that narrows the phase margin, and enables highly accurate data reproduction.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of reference numerals] 2 ... optical disc 3 ... optical head 4 ... optical detector 5 ... preamp 6 ... amplifier 7 ... differentiator 8,9 ... comparator 10 ... NAND circuit 11 ... Noise Mask block 12,22,25 ... flip-flop 14, 24 ... Inverter 21 ... Data synchronizer 23 ... Delay circuit 26 ... VFO

Claims (4)

[Claims] 1. Data synchronization for reading recording information recorded on a recording medium and generating a synchronization signal synchronized with the reproduction data to generate binarized reproduction data corresponding to the recording information. The device has a rising edge and a falling edge having a meaning corresponding to the recorded information.
A data synchronizing apparatus comprising: a binarized signal generating circuit for generating a binarized signal; and a variable frequency oscillator for generating a synchronizing signal synchronized with rising and falling edges of the binarized signal. 2. When the information is recorded on the recording medium by a short hole recording method, the binarized signal generating circuit has a rising edge or a falling edge at a substantially central position of each short hole recording portion. 2. The data synchronization device according to claim 1, further comprising a frequency dividing circuit that divides the binary signal to a frequency of 1/2 to generate the binary signal. 3. The variable frequency oscillator outputs the binary signal through a rising edge and a falling edge of the binarized signal and an oscillation output of a voltage controlled oscillator that outputs an oscillation signal having a frequency according to a voltage of an input signal. 2. The data synchronization device according to claim 1, further comprising a phase comparator for generating a synchronization clock synchronized with the pulse width of the synchronization signal. 4. The variable frequency oscillator outputs a comparison output of the phase comparator, which is compared at a rising edge and a falling edge of the binarized signal, to the voltage controlled oscillator through a charge pump and a low pass filter. The data synchronization device according to claim 3, wherein the data synchronization device is a data synchronization device.