JPS59207012A - Information reprducing system - Google Patents

Abstract

PURPOSE:To demodulate stably a data signal by providing a reference signal generating means and locking the phase of a PLL circuit on a basis of the output of the reference signal generating means during the period of read of a retrieving signal to reduce the disturbance of phase synchronism in the PLL circuit even if the signal is discontinuous on the same recording track. CONSTITUTION:An output pulse E of a reference signal generating means 16 consisting of a quartz oscillating circuit or the like passes the second AND gate 17 and is inputtd to a PLL circuit 14 through an OR gate 13. During the period of read of an address area ADR, the phase of the PLL circuit 14 is locked by the pulse E having the same frequency as demodulation of a data area DAT; and consequently, when the read of the data area DAT is started after the read of the address area ADR, acquisition of synchronism in th PLL circuit 14 is completed in a shorter time, and the data signal is demodulated stably from the almost start of the data area DAT.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention is capable of transmitting the data signal through the pickup by rotating a recording medium on which a modulated digital data signal is recorded relative to the pickup. reading,
It relates to an information reproduction method for demodulating the information, and is effectively applied to, for example, electronic files for document recording.

Prior Art In this type of reproduction method, a plurality of recording tracks are provided concentrically on a disk-shaped recording medium, and a search signal as address information is partially provided in at least one location on each recording track. data signals are recorded in the remaining portion on the same track. Therefore, during playback, the recording medium is rotated, a search signal is detected through the pickup, the pickup is positioned on a predetermined recording track using this as address information, and the data signal on the trunk is read out through the pickup. .

The recorded data is, for example, a digital signal obtained by band-compressing the bit pattern of a document image using M)l (Modified Huffman) encoding and then modulating it using the EFM (8-14 modulation) method. The differential signal read out in this manner must be demodulated in order to be reproduced.

For this reason, in particular, for the purpose of demodulating the EFM, a PLL circuit is provided which is phase synchronized based on the data signal read out through the pickup, and the EFM is demodulated using the output of this circuit as a clock signal.

The problem at this time is that since the search signal and the data signal are completely arranged and recorded on the same recording track, the data signal string that has been read out becomes discontinuous during the read period of the search signal. That is, such discontinuity causes instability in the operation of the PLL circuit, resulting in a large disturbance in the phase synchronization of the clocks. This means that it takes time for the PLL circuit output to be brought into proper phase synchronization again, and stable demodulation of the data signal cannot be performed during this time.

(c) Purpose of the Invention The present invention reduces disturbances in phase synchronization in a PLL circuit and enables stable demodulation of data signals even if there is discontinuity of signals on the same recording track/track as described above. This is what we aim for.

(E) Structure of the Invention The present invention provides a reference signal generating means separately from the PLL circuit in the conventional reproduction method, and during the reading period of the search signal, the PLL circuit is activated based on the output of the generating means. It is characterized by applying phase synchronization.

(f) Embodiment Figure 1 shows a disk-shaped recording medium (1) used in this embodiment.
) indicates the recording format. A plurality of concentric recording tracks (2a, 2b), etc. are assigned to the medium (1), and each recording track is assigned an address area MADR and a data area DAT. Address area A
On the DR, black lines (3) and (4) are printed on both sides of the area indicating the area, and in this address area, address numerical information is recorded as a search signal by digital phase change UA. . On the other hand, a digital data signal obtained by modulating a bit pattern representing a document image using the EFM method is completely recorded in the data area DAT.

Digital phase modulation of the search signal is effective in terms of error detection, and EFM of the data signal is effective in improving recording density. In addition, in this embodiment, each of these signals is recorded by coating a thin alloy film on the surface of the recording medium (1), and using a laser beam to record the information on the recording trunk in accordance with each modulated digital signal. This is done by providing a bit on the alloy thin film.

FIG. 2 shows a block circuit diagram of this embodiment. recoding media(
1) is rotated at a constant speed by a motor (5), and an optical pickup (6) relatively traces any one recording track of the recording medium (1). Pickup (6)
The output signal can be detected by the address detection section (7), and also enters the first demodulation section (10) via the waveform shaping section (8) and edge detection section (9). The outputs A and B of the waveform shaping section (8>) and the edge detection section (9) are shown in FIG. 3 A and B, respectively.
The areas ADH and DAT are shown as corresponding to the address area ADR and data area DAT in FIG. 1, respectively.

During processing in the address detection section (7), the address area ADH is determined based on the corresponding pickup outputs of the black lines (3) and (4) on the recording medium. Address detection section (7
), on the other hand, outputs a high level signal C during the read period of the address area ADH, this signal enters the AND gate (12) via the inverter (11), and during the period of No. 14 C,
Close the AND gate (12).

Therefore, of the output B of the edge detection section (9), only the data signal in the data area DAT is processed by the AND gate (1
2) and enters the PLL circuit <14> via the OR gate (13).

The PLL circuit (14) generates a clock pulse D (FIG. 3 D) with a frequency of, for example, around 4.3218 MHz, but when there is a pulse input from the OR gate (13), phase synchronization is applied thereby. In particular, when the phase is constantly synchronized by the signal of the data area DAT in the output B of the edge detection section (9), the signal is synchronized with the phase of the signal of the data area DAT and is fixed at generates a dead clock pulse D.

The first demodulator (O) demodulates the output signal B of the edge detector (9) using the clock pulse D output from the PLL circuit (14). As a result, a data signal with an 8-bit code representation is obtained. Then, in the second demodulating section (15), M
)! It is decoded and finally output and displayed on a printer, CRT, etc.

As mentioned above, the edge detection section (9) of the Antogame B12)
) is closed during the period of the address area ADH, and conventionally, no phase synchronization is applied to the PLL circuit (14) during this period. Therefore, in such a case, during the read period of the address area ADH, the clock pulse D is in a completely unstable state in both frequency and phase, and therefore, after the read state enters the data area DAT from the address area ADH, the PLL It takes a longer time to achieve synchronization in the circuit (14), and during this time one demodulator has 10
) cannot perform stable demodulation. By opening the AND gate (12) during the entire period of the output of the edge detection section 9), even if phase synchronization is applied to the PLL circuit (14) during the entire period, the signal in the address area ADR remains unchanged. This signal is completely different from and unrelated to the signal in the data area DAT, so it is not effective.

As a feature of the present invention, a 4.3218 MHz reference signal generating means 16) consisting of a crystal oscillation circuit or the like is provided, and a second AND gate gate circuit which is opened by the output C of the address detecting section (7) is provided. 17) is prepared, and the output pulse E of the reference signal generating means (16) is applied to the second ant game h.
(17) and then through the or gate <13) to P
Enters the LL circuit (14). Therefore, the above address area A
During the readout period of the DH, the PLL circuit (14) is phase synchronized by a pulse E having the same frequency as when demodulating the data area DAT.
When reading from data area DAT starts, synchronization pull-in in the PLL circuit (14) is completed in a shorter time, and stable demodulation can be performed almost from the beginning of data area DAT.

In the waveforms shown in FIG. 3, ■ indicates a synchronization pull-in process, and ■ indicates a synchronization state, that is, a long state.

Note that among the outputs of the edge detection section (9), the address area AD
The H portion also enters the first demodulating section (10), but it is discarded after leaving the first demodulating section (10), so there is no problem).

In the above embodiment, address area A of the recording medium (1)
Although there is one DH per recording track, there may be a plurality of DHs.

Effects of the Invention According to the present invention, by running a recording medium in which a search signal and a modulated digital data signal are arranged and recorded on the same recording track relative to a pickup, the data can be recorded through the pickup. When reading No. 18 and demodulating it, even if there is discontinuity of the signal on the same recording track, the disturbance of phase synchronization in the PLL circuit for demodulation is reduced, and stable demodulation of the data signal is achieved. be able to.

[Brief explanation of drawings]

An embodiment of the invention is shown in FIG. 1, a diagram showing a recording format of a recording medium, FIG. 2 a circuit diagram, and FIG. 3 a signal waveform diagram. (1>...recording medium, ri14)...PLL circuit, (
16)...Reference signal generation means.

Claims (1)

[Claims] 1) By running a recording medium in which a search signal and a modulated digital data signal are arranged and recorded on the same recording track relative to a pickup, the data signal is read out through the pickup and demodulated. When doing so, phase synchronization is performed based on the above data signal.
In the information reproducing method in which an L circuit is provided and the demodulation is performed using the output of the circuit as a clock signal, a reference signal generating means is provided, and during the reading period the retrieval signal described in - is based on the output of the reference signal generating means. An information reproducing method characterized in that the PLL circuit is subjected to phase synchronization.