JPH0877723A - Optical disk reproducing device - Google Patents

Abstract

PURPOSE: To enable shortening of the seek time at the time of an seek operation and to enable setting a data transfer rate to a proper value. CONSTITUTION: A disk driving means 12 makes an optical disk 11 rotate with a set number of revolution. The number of revolution setting means 13 sets reference numbers of revolutions of a prescribed range whose differences of numbers of revolutions between at the times of reproducings in a constant linear velocity are set to respective plural areas in the radial direction of the optical disk 11 and sets the reference number of revolution of an area in which the position of an optical pickup 14 detected by an optical pickup position detecting means 18 belongs to a disk driving means 12. A digital signal reproducing means 15 generates a reproducing digital signal from a reproducing signal from the optical pickup 14 and a reproducing PLL circuit 16 generates reproduced data and a synchronizing clock by allowing the oscillation signal of an incorporated variable frequency oscillator to be phase-locked with the reproducing digital signal. A free-running frequency control means 17 makes the free-running frequency of the reproducing PLL circuit 16 coincide with the bit frequency of the reproducing digital signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device,
In particular, it relates to an optical disc device for reproducing an optical disc of a CLV recording system such as a CD-ROM.

[0002]

2. Description of the Related Art In general, an optical disc called a CD-ROM (hereinafter, simply referred to as a disc) has a digital signal (data) EFM (Eight to Fourteen Modulation) like a CD (compact disc) for audio.
It is recorded by a modulation method called.

In a CD-ROM, the unit bit and unit frame time and the recording length on the disc are the same on the inner and outer circumferences of the disc. Therefore, in the conventional CD-ROM reproducing apparatus, the rotation speed of the disc is changed according to the position of the optical pickup in the radial direction of the disc so that the disc is scanned at a constant linear velocity (CLV).

[0004]

As described above, in the conventional CD-ROM reproducing apparatus, the rotation speed of the disk is controlled to the speed corresponding to the position of the optical pickup in the disk radial direction. When accessing and reproducing an arbitrary address on the disc, the rotation of the disc is controlled by the EFM signal actually read after the optical pickup reaches the vicinity of the target track. Therefore, in the seek operation of moving the optical pickup to a distant track to access the track, it takes a time of adding the movement time of the pickup and a time for controlling the number of revolutions of the disk, and there is a problem that the seek time becomes long.

Therefore, the number of rotations of the disk with respect to the position in the radial direction of the disk is stored in advance, and during seek operation,
A method has been proposed in which the rotational speed of a disk is controlled so that the rotational speed of a target track is reached while the optical pickup is moving. However, in order to be able to reproduce the data in synchronization with the EFM signal read by the optical pickup after the movement of the optical pickup, it is necessary to adjust the disk rotation speed within several percent of the specified rotation speed of the target track. However, there is a problem that the seek time becomes longer by the adjustment time of the rotation speed.

Also, a method of controlling a CLV disk by CAV (constant angular velocity) has been proposed. However, this method has a problem that the maximum difference in bit rate between the inner and outer circumferences is 2.5 times, and if the upper limit of the data transfer rate is set equal to that of the CLV method, the average transfer rate becomes low.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an optical disk device capable of shortening the seek time during a seek operation and making the data transfer rate an appropriate value.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. A digital signal including clock information is recorded on the optical disc 11 at a constant recording density, and the digital signal is read by the optical pickup 14.

The disk drive means 12 rotates the optical disk 11 at a set rotational speed.

The optical pickup position detecting means 18 generates a position signal indicating the position of the optical pickup 14 in the radial direction of the optical disc 11 every time the optical pickup 14 moves in the radial direction of the optical disc 11.

The rotation speed setting means 13 receives the position signal of the optical pickup 14 from the optical pickup position detecting means 18, and receives a predetermined constant line in each of a plurality of areas preset in the radial direction of the optical disk 11. A reference rotation speed is set so that the difference from the rotation speed when the optical disc is reproduced at a speed is within a predetermined range.
The reference number of revolutions of the area to which the 4 scanning positions belong is set for the disk drive means 12.

The digital signal reproducing means 15 generates a reproduced digital signal from the reproduced signal supplied from the optical pickup 14.

The reproducing PLL circuit 16 is supplied with the reproduced digital signal from the digital signal reproducing means 15,
The oscillation signal of the built-in variable frequency oscillator is phase-synchronized with the reproduced digital signal to generate reproduced data and a synchronous clock synchronized with the reproduced digital signal.

The free-running frequency control means 17, based on the reproduction digital signal supplied from the digital signal reproduction means 15, adjusts the frequency of the variable frequency oscillator of the reproduction PLL circuit 16 so as to match the bit frequency of the reproduction digital signal. Control running frequency.

According to a second aspect of the invention, the playback PL is further provided.
A signal processing circuit for performing a demodulation process of the reproduced data using the reproduced data and the synchronous clock supplied from the L circuit;
Based on the reproduced digital signal supplied from the digital signal reproducing means or the reproduced data or the synchronous clock supplied from the reproduced PLL circuit, the signal processing circuit generates a reference clock used for demodulating the reproduced data. And a reference clock oscillator.

[0016]

According to the first aspect of the present invention, during seek operation, the reference rotation speed of the area to which the target track belongs can be set in the disk drive means to control the rotation speed of the disk while the optical pickup is moving.

When the movement of the optical pickup is completed, the free-running frequency control means sets the free-running frequency of the variable frequency oscillator of the playback PLL circuit to the bit frequency of the playback digital signal based on the playback digital signal. To match. As a result, the reproduction PLL circuit can generate the reproduction data and the synchronization clock by instantly synchronizing the phase with the reproduction digital signal from the time when the optical pickup ends the tracking focusing and the reproduction digital signal is obtained. it can.

Therefore, after the movement of the optical pickup is completed,
It is possible to generate reproduction data based on the reproduction signal of the optical pickup in an extremely short time. Therefore, compared to the conventional CLV type optical disc reproducing apparatus, which can obtain the reproduction data only after waiting for the disc rotation number adjustment time after the movement of the optical pickup, the disc rotation number adjustment time is not required. , Seek time can be shortened.

Further, a plurality of areas are provided in the radial direction of the optical disk, and a reference rotational speed at which a difference from the rotational speed when the optical disk is reproduced at a predetermined constant linear velocity is within a predetermined range is set in each area. Since it is set, the variation width of the bit frequency of the reproduction data can be suppressed to an appropriate value, and the variation width of the data transfer rate and the average data transfer rate can be set to appropriate values.

According to the second aspect of the present invention, the reference clock required for signal processing such as demodulation processing can be obtained from the reproduced digital signal or the reproduced data or the synchronous clock, so that the reproduced PLL circuit is phase-synchronized with the reproduced digital signal. The demodulation process and the error correction process can be performed at substantially the same timing as the above.

[0021]

2 is a block diagram of a CD-ROM reproducing apparatus according to the first embodiment of the present invention. CD-ROM disc (hereinafter,
21), the digital signal is EFM.
Method, the data is recorded at a constant bit density in all areas.
If it is played back at LV, it is played back at a constant bit rate.

The disk drive means is a rotation speed control circuit 2
5, a driver 24, and a spindle motor 23. The rotation speed setting means is composed of the operation control microcomputer 32.

The optical disk 21 has a spindle motor 23.
Is driven to rotate. Spindle motor 23 is FG
It has a pulse generator, and the FG pulse is supplied to the rotation speed control circuit 25. The rotation speed control circuit 25
The FG pulse is used to control the spindle motor 23 via the driver 24 so that the spindle motor 23 rotates at the rotation speed set by the operation control microcomputer 32.

In the present embodiment, the disk 21 is divided into a plurality of areas in the radial direction, and when the pickup 26 is located in each area, the disk 21 is rotationally controlled at a reference rotation speed preset for each area. The reference speed of each area is
It is set to be approximately equal to the rotation speed in the CLV system.

A ROM (not shown) in the operation control microcomputer 32 stores table data in which addresses of respective areas are associated with reference rotational speeds set in the respective areas.

FIG. 4 is a diagram showing an example of division of a region and setting of a reference rotation speed. In this example, the region division and the number of revolutions are made so that the number of revolutions at the center of each of the 10 divided regions is made equal to the number of revolutions of the CLV system and the fluctuation range of the number of revolutions in each region is substantially constant. Has been set.

It should be noted that each region may be divided into approximately equal parts in the radial direction so that the rotational speed at the center of each region matches the rotational speed of the CLV system. In this case, the fluctuation range of the linear velocity in each region is almost constant.

At the time of normal reproduction, the operation control microcomputer 32 obtains the reference rotation speed of the area including the track reproduced by the pickup 26 from the table data based on the address data obtained from the demodulated data. , Is set in the rotation speed control circuit 25. As a result, the disk 21
Is controlled to be rotated at each reference rotation speed for each area.

During the seek operation, the operation control microcomputer 32 obtains the reference rotation speed of the area including the target track from the table data and sets this reference rotation speed in the rotation speed control circuit 25.

The pickup control unit 27 controls the focus /
A tracking control circuit 31, an access control circuit 30,
It is composed of a driver 29 and an access motor 28.

Focus / tracking control circuit 31
Performs focus control and tracking control of the pickup 26 in accordance with commands from the operation control microcomputer 32.

The access motor 28 has a pickup 26.
Are moved in the radial direction of the disk 21. The access motor 28 is, for example, a DC brushless motor, and has a hall element for phase judgment built therein. Access motor 2
Reference numeral 8 has a tacho-generator that utilizes the signal of this Hall element. The tacho generator (optical pickup position detecting means) generates a tacho pulse for each constant rotation speed of the access motor 28, that is, for each constant movement amount of the pickup 26. This tacho pulse is supplied to the operation control microcomputer 32.

The access control circuit 30 controls the drive of the access motor 28 via the driver 29 in accordance with a command from the operation control microcomputer 32. Access control circuit 30
Means that the pickup 26 follows the track of the disk 21 during the normal reproducing operation.
8 is controlled to move the pickup 26 in the target track direction during seek operation.
Control eight.

The operation control microcomputer 32 uses the tacho pulse supplied from the access motor 28 to pick up the pickup 2
The movement amount of 6 can be grasped. During the seek operation, the operation control microcomputer 32 grasps the movement amount of the pickup 26 using the tacho pulse, and controls the access control circuit 30 to move the pickup 26 until the pickup 26 moves by the distance from the current track to the target track. Let it be done.

In this embodiment, since the tacho pulse of the access motor 28 is used, the moving amount can be accurately grasped even when the pickup 26 is moved at high speed. If it is not necessary to move the pickup 26 at a very high speed, a tracking error signal obtained by the focus / tracking control circuit 31 may be used to grasp the movement amount of the pickup 26.

The pickup 26 irradiates the track of the disc 21 with a laser beam and detects the reflected light thereof, thereby reading the signal recorded on the disc 21 and outputting a reproduction signal.

The waveform shaping circuit 34 (digital signal reproducing means) amplifies and waveform-shapes the reproduced signal supplied from the pickup 26 to produce a raw E signal as a reproduced digital signal.
Generate an FM signal. The operation ON / OFF control signal supplied from the operation control microcomputer 32 controls the operation ON / OFF, the tracking and focusing are turned on, and the operation is turned on when the pickup 26 can reproduce the signal. It is said that

The reproduction PLL circuit 36 includes a waveform shaping circuit 34.
Is synchronized with the raw EFM signal supplied from
Synchronous EFM data (reproduced data) synchronized with the FM signal and a synchronous clock are generated. Synchronous clock is synchronous EFM
It is a bit clock for data.

The free-running frequency control means is the synchronization detection circuit 3
7, a reference frequency generating PLL circuit 39, and a free-running frequency setting circuit 40.

The synchronization detection circuit 37 is supplied with the synchronization clock and the synchronization EFM data, and determines whether or not the reproduction PLL circuit 36 is generating the correct synchronization EFM data and the synchronization clock synchronized with the raw EFM signal. / Output the asynchronous judgment signal. More specifically, the frame synchronization pattern “11T” recorded on the disc 21 is recorded.
/ 11T / 2T "(where T is a cycle of 1 bit) is detected, it is determined whether or not the synchronization clock and the synchronization pattern are in synchronization, and a synchronization / asynchronization determination signal is output. To do.

The synchronization detection circuit 37 also generates a synchronization detection signal corresponding to the detected synchronization pattern.

The reference frequency generating PLL circuit 39 is supplied with a synchronous / asynchronous determination signal, a raw EFM signal, and a synchronous detection signal. The reference frequency generation PLL circuit 39 uses the reproduction P
When the LL circuit 36 is not phase-synchronized with the raw EFM signal, a reference frequency signal which is substantially synchronized with the raw EFM signal is generated, and when the reproduction PLL circuit 36 is phase-synchronized with the raw EFM signal, a synchronization detection circuit A reference frequency signal phase-synchronized with the synchronization detection signal supplied from 37 is generated. This reference frequency signal is supplied to the free-running frequency setting unit 40,
Further, it is supplied to the signal processing circuit 42 as a reference clock that serves as a reference for demodulation processing and the like.

The free-running frequency setting section 40 generates free-running frequency control data corresponding to the frequency of the reference frequency signal supplied from the reference frequency generating PLL circuit 39, and reproduces it.
It is supplied to the LL circuit 36. As will be described later, the frequency designated by the free-running frequency control data is set as the free-running frequency of the reproduction PLL circuit 36.

The signal processing circuit 42 is a reproduction PLL circuit 36.
From which synchronous EFM data and synchronous clock are supplied,
A synchronous / asynchronous determination signal is supplied from the synchronous detection circuit 37, and a reference clock is supplied from the reference frequency generating PLL circuit 39.

The signal processing circuit 42 is the reproduction PLL circuit 36.
Is synchronized with the raw EFM signal, demodulation processing and error correction processing of the synchronous EFM data are performed, and the demodulated data is supplied to the interface microcomputer 43.

The interface microcomputer 43 supplies the target address to be accessed and the seek operation command to the operation control microcomputer 32 in accordance with the access command from the host device. During the reproducing operation, the address data in the demodulated data supplied from the signal processing circuit 42 is supplied to the operation control microcomputer 32.

The operation control microcomputer 32, during the reproducing operation,
The current area is determined from the address data supplied from the interface microcomputer 43, and the reference rotation speed of the current area is set in the rotation speed control circuit 25.

During the access operation, the operation control microcomputer 32 obtains the reference rotation speed of the area to which the target address belongs from the target address data supplied from the interface microcomputer 43, and uses this reference rotation speed as the rotation speed control circuit 25.
Set to.

Next, the reproduction PLL circuit 36, the reference frequency generation PLL circuit 39, and the free-running frequency setting circuit 40 will be described in detail.

FIG. 3 is a block diagram of the reproduction PLL circuit 36. The EFM edge detection circuit 51 detects the edge (rising edge and falling edge) of the raw EFM signal supplied from the waveform shaping circuit 34, and generates an edge pulse. The 1/2 channel bit delay circuit 52 is an EFM.
The edge pulse supplied from the edge detection circuit is EFM.
An edge pulse delayed by 1/2 channel bit of the signal is generated. 1/2 channel bit delay circuit 52
Is a circuit for adjusting the delay time in the edge clock extraction circuit 53 described later.

A VCO (voltage controlled oscillator) 57 outputs a VCO clock having a frequency corresponding to the control voltage supplied from an amplifier 56 composed of an operational amplifier A ₁ and resistors R ₁ and R ₂ .

The edge clock extraction circuit 53 is supplied with the VCO clock and the edge pulse from the EFM edge detection circuit 51, and outputs the first VCO clock pulse that arrives after the edge pulse is supplied as the extraction clock pulse. .

The phase comparator 54 compares the phase of the edge pulse supplied from the 1/2 channel bit delay circuit 52 and the phase of the extracted clock pulse supplied from the edge clock extraction circuit 53, and responds to the phase difference between them. Output voltage. The output voltage of the phase comparator 54 is supplied to the non-inverting input terminal of the amplifier 56 as a phase error voltage via the low pass filter 55. This phase error voltage is the raw EF
It is a voltage corresponding to the phase error between the M signal and the VCO clock.

In the data conversion D / A 58, the free-running frequency control data designating the free-running frequency is stored in the free-running frequency setting section 40.
Supplied from The data conversion D / A 58 D / A converts this free-running frequency control data to generate a free-running frequency setting voltage for setting the free-running frequency of the VCO 57.
Inverting input terminal of amplifier 56 (data conversion D / of resistor R ₁
This free-running frequency setting voltage is supplied to the A58 side terminal) from the data conversion D / A 58.

The control voltage supplied from the amplifier 56 to the VCO 57 is a voltage corresponding to the free-running frequency setting voltage and the phase error voltage. Therefore, the VCO 57 generates a VCO clock whose free-running frequency is set by the free-running frequency setting voltage and whose frequency is controlled according to the phase error voltage.

The reproduction PLL circuit 36 outputs the VCO clock as it is as a synchronization clock. Further, the VCO clock is supplied to the latch circuit 61 via the inverter circuit 60.
It is supplied to the trigger terminal of. Latch circuit 61 is 1/2
EFM output from the channel bit delay circuit 52
The edge pulse is latched at the falling edge of the VCO clock and output as synchronous EFM data.

When the free-running frequency is set within the range in which the frequency can be pulled in with respect to the bit frequency of the raw EFM signal, the VCO clock becomes the EFM edge pulse output from the 1/2 channel bit delay circuit 52. Synchronize in phase. At this time, the synchronous EFM data and the synchronous clock that are correctly synchronized with the raw EFM signal are generated.

The 1/2 channel bit delay circuit 52 can switch the delay time in accordance with the free-running frequency control data, and can accurately control the 1/2 channel bit regardless of the fluctuation of the bit frequency of the raw EFM signal. Cause a delay.

As shown in FIG. 2, the reference frequency generating PLL
The circuit 39 includes a frequency comparator 63, an adder 64, a low pass filter 65, a VCO 66, a frequency divider 67, and a phase comparator 6.
8 and a switch 69.

The frequency comparator 63 frequency compares the bit frequency of the raw EFM signal and the reference frequency signal generated by the VCO 66 to generate a frequency error voltage. Raw E
The bit frequency of the FM signal is obtained, for example, by detecting the longest pulse (11T) in the raw EFM signal.

When the reproduction PLL circuit 36 is asynchronous with the raw EFM signal, the switch 69 is turned off by the synchronous / asynchronous determination signal indicating asynchronous. In this case, the frequency error voltage output from the frequency comparator 63 is supplied as a control voltage to the VCO 66 via the adder 64 and the low pass filter 65. Therefore, the reference frequency signal output by the VCO 66 follows the bit frequency of the raw EFM signal.

When the reproduction PLL circuit 36 is synchronized with the raw EFM signal, the synchronization detection circuit 37 detects the synchronization pattern (11T / 11T / 2T) and outputs the phase of the synchronization detection signal corresponding to the synchronization pattern. It is supplied to the comparator 68. This synchronization detection signal is generated for each frame of the synchronous EFM data.

The frequency divider 67 frequency-divides the reference frequency signal and outputs a signal having a frequency corresponding to the frame frequency of the synchronous EFM data on a one-to-one basis. The phase comparator 68 compares the phase of the signal supplied from the frequency divider 67 with the synchronization detection signal supplied from the synchronization detection circuit 37, and outputs a phase error voltage.

When the reproduction PLL circuit 36 is synchronized with the raw EFM signal, the switch 69 is turned on by the synchronous / asynchronous determination signal indicating synchronization. In this case, the frequency error voltage output from the frequency comparator 63 and the phase error voltage output from the phase comparator 68 are added by the adder 64 and supplied to the VCO 66 via the low pass filter 65 as a control voltage. As a result, the reproduction PLL circuit 36 is turned on.
When synchronized with the FM signal, the reference frequency signal output by the VCO 66 is precisely phase-synchronized with the synchronized EFM data and the synchronized clock.

While the reproduction PLL circuit 36 performs phase synchronization at a fine cycle with respect to the edge of the raw EFM signal,
The reference frequency generation PLL circuit 39 performs phase synchronization in a large cycle in units of one frame of synchronous EFM data,
And the response frequency is also very low. Therefore, the playback PLL
Compared to the synchronous clock generated by the circuit 36, the reference frequency generation PLL circuit 39 generates a stable reference frequency signal with a small jitter component as a reference clock.

The free-running frequency setting circuit 40 comprises a frequency counter 71 and a data converter 72. The frequency counter 71 counts the frequency of the reference frequency signal supplied from the reference frequency generating PLL circuit 39 using the high-speed system clock, and outputs the count value to the data conversion unit 7.
Supply to 2. The data converter 72 uses the frequency counter 7
The free-running frequency control data corresponding to the count value supplied from 1 is output.

This free-running frequency control data is the reproduction PLL.
It is supplied to the circuit 36. As described above, the free-running frequency of the VCO 57 of the reproduction PLL circuit 36 is set to the free-running frequency specified by the free-running frequency control data. In this way, to equal the bit frequency of the raw EFM signal,
The free-running frequency of the reproduction PLL circuit 36 is controlled.

The detailed operation of the CD-ROM reproducing apparatus of this embodiment will be described next. During normal playback operation,
As described above, the disk 21 has the operation control microcomputer 32.
Under the control of 1, the rotation is controlled at the reference rotation speed set in the area where the pickup 26 is located. The reproduction PLL circuit 36 is phase-synchronized with the raw EFM signal and generates synchronous EFM data and a synchronous clock. At this time, the reference frequency generation P
Playback PL by the LL circuit 39 and the free-running frequency setting unit 40.
The free-running frequency of the VCO 57 of the L circuit 36 is set to the free-running frequency that matches the bit frequency of the raw EFM signal.

The signal processing circuit 42 generates demodulated data from the synchronous EFM data and the synchronous clock and supplies it to the interface microcomputer 43. The interface microcomputer 43 transfers the demodulated data to the host device.

When the boundary of the area is reached during the reproducing operation, the operation control microcomputer 32 sets the reference rotation speed of the next area in the rotation speed control circuit 25, and the spindle motor 2
The rotation speed of 3 is controlled to the reference rotation speed of the next region.

FIG. 5 is an explanatory diagram of the timing during the seek operation. FIG. 5 shows an example of seeking from the inner circumference to the outer circumference of the disc. FIG. 5 (A) shows the case of the present embodiment.
Spindle motor speed and playback PLL during seek operation
7 is an example of a timing chart showing ON / OFF of synchronization of the circuit 36. Further, FIG. 5B is an example of a timing chart showing the rotation speed of the spindle motor and the synchronization ON / OFF of the reproduction PLL circuit during the seek operation in the conventional apparatus, as compared with the present embodiment. It is assumed that the conventional device is a spindle motor having a torque equivalent to that of the spindle motor 23 of this embodiment.

When the access command is supplied from the host device, the interface microcomputer 43 supplies the target address to be accessed and the seek operation command to the operation control microcomputer 32.

The operation control microcomputer 32 receiving the seek operation command and the target address data commands the focus / tracking control circuit 31 to turn off tracking, and gives the access control circuit 30 a command to perform a seek operation in the target track direction. , To start moving the pickup 26 to the target track. At the same time, the operation control microcomputer 32 refers to the built-in table data to obtain the reference rotation speed of the area to which the target address belongs, and sets this reference rotation speed in the rotation speed control circuit 25. As a result, the control of the rotation speed of the spindle motor 23 (that is, the rotation speed of the disk 21) is started toward the reference rotation speed of the area to which the target address belongs.

In FIG. 5, the seek operation is started at time t ₁ , the pickup 26 moves, and the spindle motor 23
The deceleration control of is started. While the pickup 26 is moving, no reproduction signal is obtained from the pickup 26, and the reproduction PLL circuit 36 is not operating.

The operation control microcomputer 32 determines the amount of movement from the tacho pulse supplied from the access motor 28,
When it is determined that the pickup 26 has moved to the vicinity of the target track, the access control circuit 30 is instructed to stop the seek operation, and the focus / tracking control circuit 31 is instructed to turn on the tracking. As a result, the tracking is turned on, the reproduction signal is output from the pickup 26, and the raw EFM signal is supplied to the reproduction PLL circuit 36 and the reference frequency generation PLL circuit 39.

In FIG. 5, tracking is turned on at time t ₂ and thereafter a raw EFM signal is obtained.

The reference frequency generation PLL circuit 39 uses the raw EF.
When the M signal is supplied, it immediately outputs a reference frequency signal that follows the frequency of the raw EFM signal. The free-running frequency setting circuit 40 generates free-running frequency control data that specifies the free-running frequency corresponding to the frequency of the reference frequency signal, and supplies it to the reproduction PLL circuit 36. This allows the playback PLL
The free running frequency of the VCO 57 of the circuit 36 is set approximately equal to the bit frequency of the raw EFM signal. At this point, the reproduction PLL circuit 36 can be phase-locked to the raw EFM signal, output the synchronous EFM data and the synchronous clock, which are in phase synchronization with the raw EFM signal and normally in synchronization with the raw EFM signal.

Therefore, even if the moving speed of the pickup 26 is very high and the spindle motor 23 does not reach a predetermined rotation speed, the reference frequency generating PLL circuit 39 and the reproducing PLL circuit 36 can be synchronized, and t ₂ The time to get to can be very short.

In FIG. 5A, at time t ₃ , the reproduction PLL circuit 36 is phase-synchronized with the raw EFM signal, and thereafter, effective synchronous EFM data and synchronous clock are obtained, and the signal processing circuit 42 outputs the demodulated data. Is generated. Pickup 26
Of the reproduction PLL circuit 36 from the end of the movement to the phase synchronization with the raw EFM signal (from time t _{2 in} FIG. 5A).
t ₃ ) is an extremely short time.

Normally, the target track is not exactly reached at the end of the movement of the pickup 26. Therefore, the target track is reached after the re-seek operation to the target track is performed based on the address data in the demodulated data. To do. Figure 5
In (A), it has reached the target track again seek operation is performed at time t ₃ ~t _4. After that, the demodulated data can be transferred to the higher-level device.

The reference frequency generating PLL circuit 39 is
After the reproduction PLL circuit 36 synchronizes with the raw EFM signal, it generates a reference frequency signal precisely phase-synchronized with the synchronization clock. As a result, the free-running frequency of the reproduction PLL circuit 36 is
It is precisely set to the bit frequency of the raw EFM signal.

Even after the reproduction PLL circuit 36 is synchronized with the raw EFM signal, the rotation speed of the spindle motor 23 changes until it matches the reference rotation speed set in the area to which the target track belongs. At this time, the bit frequency of the raw EFM signal changes, but the reference frequency signal of the reference frequency generation PLL circuit 39 follows, and therefore the free-running frequency of the reproduction PLL circuit 36 also follows. As a result, the reproduction PLL circuit 36
Maintains phase synchronization with the raw EFM signal.

In the example of the conventional apparatus of the CLV system shown in FIG. 5B, the seek operation is started at time t ₁ , and after the movement of the pickup and the deceleration control of the spindle motor are started,
The timing is the same as that of this embodiment until the pickup reaches the vicinity of the target track, the movement of the pickup is stopped at time t ₂ , and the tracking is turned on.

In the conventional CLV system device, the free-running frequency of the reproduction PLL circuit for generating the synchronous EFM data and the synchronous clock is fixed based on the reproduced EFM signal from the pickup, and the frequency pull-in range for the reproduced EFM signal is It is as narrow as ± several percent. Further, generally, the rotation speed control of the spindle motor 23 at this time is a method of performing open control of the rotation speed difference calculated from the difference between the target track and the current track. Therefore, in the conventional CLV system device, after the tracking is turned on, the bit frequency of the reproduced EFM signal is reproduced by the CLV pull-in function of the CLV servo circuit.
The rotation speed of the spindle motor (that is, the disk) is adjusted so that it falls within the frequency pull-in range of the LL circuit. In FIG. 5 (B), times t _{2 to} t ₅ are this rotation speed adjustment time.

The bit frequency of the reproduced EFM signal is the reproduction PL.
At time t ₅ when the frequency of the L circuit falls within the frequency pullable range, the reproduction PLL circuit is phase-synchronized with the reproduction EFM signal and demodulation data can be generated. After that, after the pickup is accurately adjusted to the target track by the re-seek operation, the demodulated data can be continuously generated and transferred to the host device.

As described above, in the conventional apparatus, after the rotation speed of the spindle motor is adjusted within a few% of the specified rotation speed after the pickup is moved, the reproduction PLL circuit is phase-synchronized with the reproduction EFM signal for the first time. Playback is possible.
On the other hand, in the present embodiment, the reproduction PLL circuit 36 can be phase-synchronized with the raw EFM signal and the demodulated data can be generated in a very short time after the pickup is moved.

Therefore, in this embodiment, it is possible to eliminate the waiting time for the spindle motor adjustment time (t ₂ to t 5 in FIG. ₅ ) after the pickup is moved in the conventional apparatus, and the time until the time t ₂ . Since the time can be shortened, the seek time can be shortened.

By appropriately dividing each region and setting the reference velocity, the maximum value of the linear velocity change width in each region with reference to the linear velocity in the CLV method is set to an appropriate value. Therefore, the change width of the data transfer rate can be suppressed to an appropriate value, and the data transfer rate equivalent to that of the CLV method can be obtained.

Reproduction PLL circuit 36 and reference frequency generation P
The response frequency band of the LL circuit 39 is the spindle motor 2
It is set so that it can sufficiently follow the fluctuation of the rotation speed at the zone boundary of No. 3.

FIG. 6 is a CD-ROM of the second embodiment of the present invention.
The block diagram of a reproducing | regenerating apparatus is shown. 6, the same components as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. In the second embodiment, the 11T detection circuit 81 _-1 is provided as the free-running frequency control means. Further, in order to generate a reference clock, 11T detection circuit 81 _-2 and a reference frequency generator PL
The L circuit 84 is provided.

The 11T detection circuit 81 _-1 outputs the synchronization clock (VCO clock) generated by the reproduction PLL circuit 36 and the raw E signal.
A frequency comparison signal is generated by comparing the frequencies of the FM signals. 11T detection circuit 81 _-2, generated reference clock of the reference frequency generation PLL circuit 84 (reference frequency generating PLL
The VCO clock of circuit 84) is compared with the frequency of the raw EFM signal to produce a frequency comparison signal.

11T detection circuit 81_-1Is a set of counters, etc.
It consists of a combination. 11T detection circuit 81 _-1Is the raw EFM signal
Detects 11T, which is the longest cycle, and reproduces PLL circuit
Measure the time width of 11T with 36 synchronous clocks.
Frequency difference between the raw EFM signal and the synchronization clock
Generates a frequency comparison signal corresponding to. This frequency comparison
The signal is 11T detection circuit as free-running frequency control data.
81_-1Is supplied to the reproduction PLL circuit 36.

11T detection circuit 81_-2Is a set of counters, etc.
It consists of a combination. 11T detection circuit 81 _-2Is the raw EFM signal
11T in the inside is detected, and the reference frequency generating PLL circuit 84
Generated by the reference clock (reference frequency generation PLL circuit 8
4 VCO clock) to measure 11T time width
Allows the raw EFM signal and the reference frequency generation PLL circuit 84
Frequency comparison signal corresponding to the frequency difference from the reference clock of
To generate. This frequency comparison signal is a reference frequency generation P
As a signal for controlling the free running frequency of the VCO of the LL circuit 84
11T detection circuit 81_-2From the reference frequency generation PLL times
It is supplied to the path 84.

In this way, the reproduction PLL circuit 36 is
After frequency synchronization with the raw EFM signal, phase synchronization
The FM data and the synchronous clock are generated. The reference frequency generation PLL circuit 84 is also frequency-synchronized with the raw EFM signal.

The reference frequency generation PLL circuit 84 outputs the synchronization detection signal from the synchronization detection circuit 37 and the reference clock generated by the built-in VCO to one frame (5) of the synchronization EFM data.
88T) for phase comparison to generate a reference clock phase-synchronized with the synchronous EFM data. The reference clock is supplied to the signal processing circuit 42 as a reference clock that serves as a reference for demodulation processing and the like.

The signal processing circuit 42 uses the reproduction PLL circuit 36.
The synchronous EFM data, the synchronous clock, and the reference clock supplied from the reference frequency generating PLL circuit 84 are used to perform demodulation processing, error correction processing, and read processing of the synchronous EFM data.

[0097]

As described above, according to the invention of claim 1,
During the seek operation, it is possible to generate the reproduction data based on the reproduction signal of the optical pickup in a very short time after the movement of the optical pickup, so that the seek time is longer than that of the conventional CLV type optical disc reproducing apparatus. Can be shortened.

Further, since the reference number of revolutions in which the difference from the number of revolutions when the optical disc is reproduced at a predetermined constant linear velocity is within a predetermined range is set in each region in the radial direction of the optical disc, the reproduction data is reproduced. The change width of the bit frequency can be suppressed to an appropriate value, and the change width of the data transfer rate and the average data transfer speed can be set to appropriate values.

According to the second aspect of the present invention, the reference clock required for signal processing such as demodulation processing can be obtained from the reproduced digital signal or the reproduced data or the synchronous clock. The demodulation process and the error correction process can be performed at substantially the same timing as the synchronization.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a CD-ROM reproducing device according to a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a reproduction PLL circuit 36.

FIG. 4 is a diagram showing an example of dividing a region and setting a reference rotation speed.

FIG. 5 is an explanatory diagram of timing during a seek operation.

FIG. 6 is a configuration diagram of a CD-ROM reproducing device according to a second embodiment of the present invention.

[Explanation of symbols]

11 optical disk 12 disk drive means 13 rotational speed setting means 14 optical pickup 15 digital signal reproducing means 16 reproducing PLL circuit 17 free-running frequency control means 18 optical pickup position detecting means 21 optical disk 23 spindle motor 24 driver 25 rotational speed control circuit 26 optical pickup 27 pickup control unit 28 accesses the motor 29 driver 30 access control circuit 32 operates the control microcomputer 34 the waveform shaping circuit 36 reproduction PLL circuit 37 synchronization detection circuit 39 reference frequency generating PLL circuit 40 running frequency setting circuit 42 signal processing circuit 43 interfaces the microcomputer 81 _{- 1} , 81 _-2 11T detection circuit 84 Reference frequency generation PLL circuit

Claims (2)

[Claims] 1. An optical disc apparatus for producing a reproduction data by reading the digital signal from an optical disc on which a digital signal containing clock information is recorded at a constant recording density, and rotating the optical disc at a set number of revolutions. A disc driving means; an optical pickup position detecting means for generating a position signal indicating the position of the optical pickup in the radial direction of the optical disc; and a radius of the optical disc for receiving a position signal of the optical pickup from the optical pickup position detecting means. A reference number of revolutions is set in each of a plurality of regions set in advance with respect to the direction so that the difference from the number of revolutions when the optical disc is reproduced at a predetermined constant linear velocity falls within a predetermined range. The reference rotation speed of the area to which the scanning position belongs is compared with the disk drive means. Rotation speed setting means for setting, a digital signal reproducing means for generating a reproduced digital signal from the reproduced signal supplied from the optical pickup, and a variable frequency built-in supplied with the reproduced digital signal from the digital signal reproducing means. A reproduction PLL circuit for phase-locking the oscillation signal of the oscillator with the reproduction digital signal to generate reproduction data and a synchronous clock synchronized with the reproduction digital signal; and a reproduction digital signal supplied from the digital signal reproduction means, An optical disk reproducing apparatus comprising: a free-running frequency control means for controlling a free-running frequency of a variable frequency oscillator of the above-mentioned reproducing PLL circuit so as to match the bit frequency of a reproduced digital signal. 2. A signal processing circuit for performing demodulation processing of reproduction data using reproduction data and a synchronous clock supplied from the reproduction PLL circuit, and a reproduction digital signal supplied from the digital signal reproduction means or the reproduction. 2. A reference clock oscillator for generating a reference clock used for demodulation of reproduced data in the signal processing circuit based on reproduced data or a synchronous clock supplied from a PLL circuit. Optical disk playback device.