JPH0430104B2

JPH0430104B2 -

Info

Publication number: JPH0430104B2
Application number: JP58099564A
Authority: JP
Priority date: 1983-06-06
Filing date: 1983-06-06
Publication date: 1992-05-20
Also published as: JPS59227069A

Description

[Brief explanation of drawings]

第１図はCD方式DADの記録信号フオーマツ
ト、第２図はPLLを用いたデイスク回転制御系
のブロツク図、第３図はEFM処理過程を表わす
図、第４図は線速度偏差による再生信号のパルス
幅範囲の変動を示す図、第５図は本発明の実施例
を示すブロツク図、第６図、第７図は第１検出回
路、第２検出回路の一具体例を示すブロツク図、
第８図、第９図はそれぞれ第１検出回路、第２検
出回路の動作を説明するための波形図である。符号の説明、１３……第１検出回路、１４……
第２検出回路、１５……混合回路、１６，１７…
…電子スイツチ、１８，２０……カウンタ、１
９，２１……デコーダ、２２……オアゲート、２
３……アンドゲート、２４……インバータ。 Figure 1 shows the recording signal format of a CD-based DAD, Figure 2 is a block diagram of the disk rotation control system using PLL, Figure 3 shows the EFM processing process, and Figure 4 shows the reproduction signal format due to linear velocity deviation. FIG. 5 is a block diagram showing an embodiment of the present invention; FIGS. 6 and 7 are block diagrams showing specific examples of the first detection circuit and the second detection circuit;
FIGS. 8 and 9 are waveform diagrams for explaining the operations of the first detection circuit and the second detection circuit, respectively. Explanation of symbols, 13...first detection circuit, 14...
Second detection circuit, 15... Mixing circuit, 16, 17...
...Electronic switch, 18, 20...Counter, 1
9, 21...decoder, 22...or gate, 2
3...AND gate, 24...Inverter.

Claims

[Claims] 1. A bit synchronized clock generated by supplying a reproduced signal obtained from a digital audio disk to a PLL circuit, or a frame synchronized signal detected from the reproduced signal using this bit synchronized clock as a reference clock. In a digital audio disk playback device that performs phase comparison and plays back at a specified linear velocity by controlling the rotational speed of the disk based on the obtained phase difference signal, the polarity reversal interval of the playback signal is determined by the recording method of the disk. a first detection circuit for detecting that the polarity reversal interval time of the reproduced signal is longer than the maximum polarity reversal interval time of the recording signal determined by the recording method of the disk; and a second detection circuit for detecting that the bit synchronization clock frequency of the reproduced signal is outside the lock range of the PLL circuit, the detection signal from the first or second detection circuit is The rotation speed of the disk is controlled by the PLL, and the bit synchronization clock frequency of the playback signal is
A digital audio disc playback device designed to be within the lock range of the circuit. [Claims] The present invention relates to a digital audio disk (hereinafter referred to as
(referred to as a DAD), and more specifically, it relates to a DAD playback device having a disk rotation control means that quickly and reliably starts up the disk rotation control with respect to a means for controlling the rotation of the disk to a constant linear velocity based on a reproduction signal. . Compact disk type (CD type) DAD digitizes the audio signal, adds an error correction signal, and then converts it to EFM (EIGHT TO FOURTEEN).
It is optically recorded on a disk at a constant linear velocity (1.2 to 1.4 m/s) using a modulation method called MODULATION. During playback, it is synchronized with the bit synchronized clock or frame synchronized signal detected from the reproduced signal. Compare the phase with the reference clock,
In order to eliminate the phase difference, the rotational speed of the disk is controlled to maintain a constant linear velocity reproduction state. In other words, the bits and frame synchronization signals that make up the digital information (audio signal, error correction signal, frame synchronization signal, etc.) recorded on the disk are arranged with a fixed period (bit string) [a sequence of predetermined frequencies]. arranged according to the clock pulses]. To explain the format of the recording signal, the recording signal on the disk is divided into frames, and one frame consists of audio signal bits, error correction bits, frame synchronization signal bits, etc. are subjected to EFM processing, as shown in Fig. 1. It has a total of 588 bits. As is well known, this applies to the 6-sample interval, and
Since the sampling frequency is 44.1 kHz, the frame repetition frequency is 7.35 kHz, and the bit frequency is 7.35 kHz x 588 = 4.32 MHz, and the information bits are arranged in synchronization with the 4.32 MHz clock. Therefore, the bit synchronization clock or frame repetition frequency (frame synchronization signal) is detected from the reproduced signal, and the above-mentioned bit frequency (4.32M
The disk motor may be controlled using a phase difference signal obtained by comparing the phase with a reference clock having a frame repetition frequency (7.35 kHz) or a frame repetition frequency (7.35 kHz). To explain specifically using FIG. 2, the recorded information on the disk 1 is reproduced by the pickup 3 and the PLL circuit
supplied to This PLL circuit 4 includes a phase comparator 5,
Consists of 6 low-pass filters (LPF), 7 DC amplifiers, and 8 voltage-controlled oscillators (VCO).
The center frequency of VCO8 is set to 4.32MHz. The output of the VCO 8 is fed back as a reference signal to the input side of the phase comparator 5, and is also supplied to the synchronous separation clock generation circuit 9. The synchronous separated clock obtained from the synchronous separated clock generation circuit 9 is supplied to the frame synchronization circuit 10. The frame synchronization circuit 10 detects a frame synchronization signal from the reproduced signal from the pickup 3 using a synchronization separation clock. The output of the frame synchronization circuit 10 is a signal with a frame repetition frequency of 7.35 kHz when the disc is being reproduced at a specified linear velocity, which corresponds to a frequency division of 1/588 of the bit synchronization clock. This frequency-divided bit synchronized clock is sent to phase comparator 1.
1, the phase is compared with a reference clock (7.35MHz), and the obtained phase difference signal is added to the motor drive circuit. As a result, the oscillation frequency of VCO8 is 4.32MHz
If so, a 7.35kHz signal is supplied to the phase comparator 11, no phase signal is generated, and the current linear velocity is maintained. On the other hand, the oscillation frequency of VCO8 is 4.32MHz
If the deviation is from the reference clock 7.35kHz, the phase comparator 11 supplies a phase difference signal corresponding to the phase difference with the reference clock 7.35kHz to the motor drive circuit 12 to control the rotational speed of the motor and always reproduce at the specified linear velocity. This is what we do. However, the PL circuit that extracts the bit-synchronized clock described above has a lock range, that is, a range in which it can synchronize with the input signal frequency at most ±5% (±200kHz with a center frequency of 4.32MHz). In this DAD system, during playback,
Since the rotation speed changes approximately 2.5 times from 500 rpm to 200 rpm, for example, when starting playback after skipping song selection, there will be a large deviation from the normal rotation speed and it will fall outside the lock range of the PLL circuit.
There was a risk that the rotational speed of the disk could not be controlled. Also, if the recorded signal is lost for a certain period of time due to scratches or dust on the disk, it may become impossible to detect the bit synchronized clock.
There was a danger that the lock range of the PLL circuit would be exceeded. The present invention eliminates the above-mentioned drawbacks,
Extract the bit synchronized clock from the reproduced signal
To provide a means for quickly returning the disk rotation speed to within the lock range and maintaining a specified disk rotation speed even when a disk rotation speed deviation that goes out of the lock range of a PLL circuit occurs. First of all,
To explain the technical background of the present invention, as mentioned above, in a CD-based DAD, when recording a digital audio signal (Fig. 3A) on a disk, EFM processing is performed to distinguish bits 1 and 1 of the digital signal. There must be two or more 0 bits in between, 10
It is configured so that less than 1000 yen can be inserted (Fig. 3 A). Furthermore, the EFM-processed bit string is processed using the NRZI modulation method (signal polarity is inverted at bit 1 and non-inverted at bit 0, converting the bit string into an electrical signal change) as shown in Figure 3C. Convert a train to a pulse train. In other words, as shown in Figure 3C, this pulse wave has the minimum pulse width (minimum inversion interval time Tmin) when the bit string is 1001, and the maximum pulse width (maximum inversion interval time Tmax) when the bit string is 100000000001.
The recording signal is expressed by a combination of nine basic pulses having a pulse width (reversal interval time T) defined by Tmin≦T≦Tmax (1). Therefore, when a deviation occurs in the linear velocity during reproduction, a portion of the pulse width T of the reproduced signal deviates from the specified range shown in equation (1) above. FIG. 4 shows this, and the shaded area (a) is the case where reproduction is performed at the specified linear velocity, which is equivalent to equation (1). The shaded area (b) shows the pulse width range when the linear velocity is faster than the specified linear velocity, and a pulse smaller than the minimum pulse width Tmin appears, and conversely, when the linear velocity is slower than the specified linear velocity, the maximum pulse width appears as shown in the shaded area (c). A pulse appears whose width exceeds Tmax. Therefore, in the present invention, when it is detected that the pulse width T of the reproduced signal is outside the range of Tmin≦T≦Tmax, the disk rotation speed is controlled based on the obtained detection signal (time difference signal) to achieve bit synchronization. This is to ensure that the clock frequency quickly falls within the lock range of the PLL circuit, and more specifically, to adjust the pulse width T of the reproduced signal.
the minimum pulse width Tmin and maximum pulse width Tmax
T＜Tmin or T＞
This is to detect Tmax. The present invention will be explained below based on illustrated embodiments. Note that in the drawings below, the same reference numerals are used for structures similar to those of the conventional example. FIG. 5 is a block diagram showing the disk rotation control device of the present invention, and 13 is a first detection circuit that detects whether or not the reproduced signal from the pickup 3 contains a pulse having a pulse width of T>Tmax. To detect. 14 is a second detection circuit, which detects T in the reproduced signal.
It is detected whether a pulse having a pulse width of <Tmin is included. A mixing circuit 15 mixes the detection outputs of the first detection circuit 13 and the second detection circuit 14. 16 is an electronic switch that supplies the output from the mixing circuit 15 to the motor drive circuit 12, and is used when the speed deviation from the specified linear velocity is large and the frame synchronization signal detection by the frame synchronization circuit 10 becomes impossible. The first and second detection circuits 13 and 14 are closed and opened when the motor drive control is started and locked to a predetermined rotation speed.
The rotation control is terminated. 17 is an electronic switch, which connects the first and second detection circuits 13 and 14;
The PLL circuit 4 is locked by the initial rotation control and is closed when the frame synchronization signal is detected, forming a speed control loop for the disk drive motor. On the other hand, the loop is open until the frame synchronization signal is detected, and the speed control loop of the disk drive motor is in an open state. Next, the first detection circuit 13 and the second detection circuit 14
A specific example will be explained. FIG. 4 shows an example of the first detection circuit, and 18 is a counter, which has a count enable terminal, a reference clock (4.32 MHz) input terminal CK, and a reset input terminal into which the reproduced signal from the pickup 3 is input. Note that although the counter 18 used in this embodiment is a negative logic reset counter, it is obvious that it is not limited to this. A decoder 19 reads reference clock count information from the counter 18 and outputs a control signal from an output terminal NO. In this embodiment, the reference clock frequency is 4.32MHz, which matches the bit synchronization clock frequency at the specified linear velocity.
Tmax is equal to the clock duration of reference clock 11 (if the reference clock is 8.64MHz, Tmax is 2
2 clock duration or approximately 6 clock duration if 0.4MHz is used as the reference clock is equal to Tmax). Therefore, when the count value of the counter 18 exceeds 11, the decoder 19 reads the count information from the counter 18 and outputs a control signal. Next, FIG. 7 shows an example of the second detection circuit, with 20
is a negative logic reset counter with a count enable terminal similar to 18 above, and has a reference clock input terminal CK, a reset input terminal, and a count information output terminal O. 21 is a decoder, which generates a pulse signal from the time when the counter 20 exceeds the count value of the reference clock number 3 corresponding to Tmin until it is reset (output terminal NO). 22 is an OR gate which inputs the reproduction signal pulse from the pickup 3 and the output signal of the decoder 21, and its output is applied to the reset terminal of the counter 20. 23 is an AND gate, to the input of which a reproduced signal pulse and an output signal are applied via an inverter 24, respectively. Note that the NO output signal of the decoder 21 is input to the terminal of the counter 20. The configuration is as described above, and its operation will be explained next. During playback, if the disk playback speed has a large deviation from the specified linear speed and the bit synchronization clock is outside the lock range of the PLL circuit 4,
Since no frame synchronization signal is detected by the frame synchronization circuit 10, the electronic switch 16 is closed and the electronic switch 17 is opened, as shown in FIG. The reproduced signals are supplied to the first and second detection circuits, respectively, and processed as described below. In the first detection circuit 13, the reproduced signal shown in FIG.
When it is inverted to (H), the counter 18 starts counting operation and counts the reference clock input to the CK terminal. The pulse width of the reproduced signal pulse _P1 , which continues from time to to time _t1 , is longer than Tmax, that is, the 11 clock counting time of the reference clock, and when the count value of the counter 18 exceeds 11, the output terminal of the decoder 19
NO is inverted to high level (Figure 8b) and the pulse
The high level (H) is maintained until _P1 is inverted to (L) at time _t1 , that is, until the counter 18 is reset. The counter 18, which was reset at time _t1, does not perform a counting operation until the reproduction signal rises to (H) again. In this way, the pulse width Tp ₁ of pulse P ₁ and
The first detection circuit outputs a T>Tmax detection signal that holds (H) during a period corresponding to the time difference T _N1 from Tmax. As described above, the detection output is obtained from the first detection circuit when the linear velocity is slower than the specified linear velocity. Note that the configuration in which the output of the decoder 19 is applied to the enable terminal in FIG. 6 is to ensure that the counter 18 is reset at the end of the reproduced signal pulse.For example, a hexadecimal counter (4-bit digital counter) is used as the counter 18. In this case, if the reference clock is counted for 16 clocks, it will be reset regardless of the reset input, so if the pulse width of the reproduced signal is long, an accurate time difference TN cannot be obtained. Therefore, when the decoder output is at a high level, the counter 11 is not reset unless a reset signal is input to the reset terminal. Next, in the second detection circuit, the reproduced signal shown in _FIG . , counter 2
0 starts the counting operation. In this case, the pulse width of the reproduced signal pulse P ₁ is shorter than the 3-clock duration of the reference clock (that is, reproduction is being performed at a higher speed than the specified linear velocity), and the reproduced signal pulse comes first (at time t' ₁ ). However, since the output of the decoder 20 is maintained at (H) at this time ((Fig. 9c), the output of the OR gate 22 remains (H) (Fig. 9b). , the counter 20 is not reset. When the counter 20 counts the reference clock three clocks, the NO output is inverted to (H) (FIG. 9b) and (L) in accordance with the counting information, so that the OR gate 22 The output is also reversed to (L) and the counter 20
will be reset. Also, at the same time as the reset, the NO output immediately returns to (L). On the other hand, in the above operation process, the AND gate 2
3 is at a high level from the start of the counting operation of the counter 20 until the reproduction pulse _P1 ' is inverted to a low level, and the reproduction signal level via the inverter is at a low level, so no control signal appears on the output side. After the reproduction signal is inverted to (L) (low level state), it is held at (H) until the counter 20 is reset. (Figure 9e). In this way pulse
A detection signal of T<Tmin, which maintains (H) during a period corresponding to the time difference _T'N1 between the pulse width T'p1 of _P1 _' and Tmin, is output from the second detection circuit. As mentioned above, the second
The fact that a detection output can be obtained from the detection circuit means that
This is the case when the linear velocity is faster than the specified linear velocity. Note that the reproduced signal pulses P ₂ and P′ ₂ shown in FIGS. 8a and 9a
As in, the pulse width Tp ₂ , T′p ₂ is Tmin≦
This includes pulses Tp ₂ , T′p ₂ ≦Tmax, but the 8th
As shown in FIG. b and FIG. 9e, no detection signal is output. Next, the detection signals from each detection circuit 13 and 14 are turned into a single signal by a mixing circuit 15, and an electronic switch 16
The rotation control signal is supplied to the motor drive circuit 12 as a rotation control signal. In this case, if the disc playback speed is slower than the specified linear velocity, the single signal is composed only of the detection signal from the first detection circuit 13, and conversely, if it is faster than the specified linear velocity, the single signal is composed of the detection signal from the second detection circuit 13. It is composed only of the detection signal from the circuit 14. When the disk playback speed is slower than the specified linear speed, the motor (not shown) is controlled to rotate faster, and when the disk playback speed is faster than the specified linear speed, the motor rotation is slowed down. controlled by. The initial rotation of the disk is controlled by the detection signal from the detection circuit 13 or 14, the PLL circuit 4 for bit synchronization clock generation is locked, and when the frame synchronization signal is detected by the frame synchronization circuit (that is, the lock range of the PLL circuit is When the electronic switch 17 is closed, a speed control loop is formed for the motor in which the electronic switch 17 is not closed under the command of an operation control device (not shown) in the DAD reproducing device, and the motor is locked at a specified rotational speed. Detecting this motor rotation speed lock information, the electronic switch 16 is opened in response to a command from the operation control device, and the detection circuit 13,
In addition to stopping the initial rotation control by 14
The disk rotation control by the speed control loop including the PLL circuit 4 continues. As described above, the present invention compares the pulse width T of the reproduced signal of the DAD with the minimum inversion interval time Tmin and the maximum inversion interval time Tmax, respectively.
Since the disk drive motor is controlled based on the time difference detection signal from Tmin or Tmax obtained by detecting Tmin or T=Tmax, even if a large deviation occurs in the disk playback linear velocity, Since it quickly falls within the controllable range of the PLL circuit for disk rotation control, it is possible to avoid the rotation speed becoming uncontrollable.In terms of configuration, there is no need to measure the individual pulse widths in the reproduced signal, so the circuit is greatly simplified. It has excellent effects such as very low detection error. Further, according to the present invention, not only the maximum polarity reversal interval and the minimum polarity reversal interval of the reproduced signal, but also the polarity reversal interval longer than the maximum polarity reversal interval of the recorded signal and the minimum polarity reversal interval of the recorded signal are provided. All those with a short polarity reversal interval are detected,
The rotation of the disk is controlled so that these are no longer detected. For example, when restarting after skipping channel selection, detection signals are output multiple times in one frame period and the rotation of the disk is controlled. Set the bit synchronous clock frequency of the signal to
It can be quickly pulled into the lock range of the PLL circuit.