JP3462896B2 - Synchronous signal generator for EFM signal - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an optical disk storage medium,
For example, an EFM signal for demodulating and creating an EFM channel clock required for EFM (Eight to Fourteen Modulation) modulation in a system (CD-R) capable of recording and reproducing data on a compact disc (hereinafter referred to as a CD). For a synchronizing signal generator for use.

[0002]

2. Description of the Related Art In a system capable of recording and reproducing data on a CD (CD-R), EFM (Eight to Fourteen Modulation) at the time of recording the original information on the CD or reproducing the recorded information on the CD to the original information. Conventionally, a VCO (Voltage Controlled Osillator) device for demodulating and creating an EFM channel clock required for modulation has a configuration as shown in FIG.

Crystal oscillator (denoted as X'tal in the figure)
The output side of 1 is connected to the input side of a first clock generator 2 that creates a word clock (WCK), and the output side of the first clock generator 2 is the input of a word clock output terminal 3 and a frequency divider 4. Connected to the side. The frequency divider 4 divides the frequency of the word clock to 1/12 to generate an EFM frame synchronization (XSYNC) signal, and the output side of the frequency divider 4 is one of the second phase comparators 14 described later. Input side of EF
The M frame sync signal (XSYNC) output terminal 5 and the input side of the frequency divider 6 are connected. The frequency divider 6 divides the EFM frame synchronization signal into 1/98 to generate a subcode frame synchronization signal (XSSYNC), and the output side of the frequency divider 6 is connected to the subcode frame synchronization signal output terminal 7. To be done.

The output side of the EVCO 8 which is a VCO for EFM is connected to a second clock generator 9 for generating an EFM channel clock (hereinafter sometimes referred to as PLCK), and the output side of the second clock generator 9 is connected. Is connected to the EFM channel clock output terminal 10, and is also connected to one input side of the first phase comparator 11 and the input side of the frequency divider 13. On the other input side of the first phase comparator 11,
The output side of the EFM frame synchronization extraction circuit 12 for extracting the EFM frame synchronization pattern from the EFM signal read from the CD during pattern reproduction by pattern matching is connected, and the first phase comparator 11 is externally connected to the EFM frame synchronization extraction circuit 12. An EFM sync signal is provided.

The frequency divider 13 generates an internal EFM synchronization signal by dividing the frequency of the phase-locked clock into 1/588, and the output side of the frequency divider 13 is the other input side of the second phase comparator 14. Connected to. The output sides of the first phase comparator 11 and the second phase comparator 14 are connected to the input side of the selector 15, and the output side of the selector 15 is the loop filter 16
Connected to the input side of. The output side of the loop filter 16 is connected to the input side of the EVCO 8. In addition, EVCO
8, second clock generator 9, first phase comparator 11, EF
The PLL (Phase Locked L) at the time of reproduction is set by the M frame synchronization extraction circuit 12, the selector 15, and the loop filter 16.
oop) circuit, and the EVCO 8, the second clock generator 9, the frequency divider 13, the second phase comparator 14, the selector 15,
The loop filter 16 forms a PLL circuit for recording. Further, the mode switching device 17, which is supplied with a control signal for switching the recording / reproducing mode of information to the CD, sends a mode switching signal corresponding to the first control signal to the selector 15 and the loop filter 16.

The operation of the conventional VCO device configured as described above will be described below. First, the case of demodulating an EFM signal recorded on a CD will be described. In this case, the selector 15
Selects the signal supplied from the first phase comparator 11.
EVCO 8, second clock generator 9, first phase comparator 1
1, EFM frame synchronization extraction circuit 12, selector 15,
And a PLL loop composed of the loop filter 16
PLCK which is a channel clock of FM is generated.
Incidentally, one clock of this PLCK will be referred to as "1T" hereinafter. Further, in the EFM frame synchronization extraction circuit 12 to which the EFM signal read from the CD is supplied, 11T, 11T and 2T shapes starting with “H” or “L” defined by the CD standard “RED BOOK” are provided. The EFM frame synchronization pattern is converted to the above E by the method of pattern matching.
It is extracted from the FM signal, and the extracted signal is sent to the first phase comparator 11 as an external EFM frame synchronization signal. Therefore, the phase comparator 11 performs a phase comparison between the external EFM frame synchronization signal and the first internal EFM frame synchronization pattern supplied from the second clock generator 9 using the PLCK as a basic clock to perform EFM frame synchronization. Take It is noted that the state in which the synchronization of the signals coincides with each other is described as locked. In this way, the EFM frame synchronization is established, and when the PLCK is determined, the 14-bit EFM signal taken in by the internal counter driven by the PLCK is positionally aligned and subjected to inverse EFM conversion to become 8-bit data.

Next, the case of writing the EFM signal to the CD will be described. In this case, the selector 15 is the second phase comparator 1
Select the signal supplied from 1. Therefore, as described above, the EVCO 8, the second clock generator 9, the frequency divider 13, the second phase comparator 14, the selector 15, and the loop filter 16 form a PLL circuit at the time of recording. From the PLL loop used when reading the EFM signal to the above PLC
K (1T) is generated. Then, with the result of phase comparison between the signal having 588T (1EFM frame interval) transmitted from the frequency divider 13 and the signal obtained by frequency-dividing the master clock transmitted from the first clock generator 2 by the frequency divider 4, Lock the clock sent from the EVCO 8.
The EFM modulation is driven by the PLCK generated from the EVCO 8 locked by using the master clock of the crystal oscillator 1 system, and the 8-bit data is converted into the 14-bit EFM pattern according to the configuration defined in the above "RED BOOK". To be done.

When writing the EFM signal, the linking rule described below is specified. In the case of the normal incremental additional writing defined in the standard “ORANGE BOOK PART2”, the EFM write pulse is 26 + 1 / − from the S0 start point of a certain subcode frame on the disc of the write start subcode frame in the user data area. It is required to start writing one EFM frame later and finish writing 26 + 1 / −1 EFM frames after the SO start point of the subcode frame in the data string to be written in the write end subcode frame. Further, the write data is signal-processed in synchronization with the master clock of the crystal oscillator 1 system, but the master clock of the crystal oscillator 1 system and the clock obtained from the EFM pit train on the CD are asynchronous,
This linking is "ORANGE BOOK PART"
It is defined as + 2 / -2 EFM frame from 2 ". Therefore, if the start of the EFM frame on the CD is later than the start of the EFM frame of the crystal oscillator 1 system, part of the prepared data is discarded, and if it is earlier Is written with OOH.

[0009]

The loop filter 16 shown in FIG. 3 is set to have a narrow band in order to absorb fluctuations in the EFM signal due to scratches, dirt, etc. on the CD, that is, in order to avoid the influence of disturbance noise. Has been done. Therefore, when the entire system switches to the data write state, PLCK
Locks for a relatively long time. Therefore, there is a high possibility that the PLCK is not stable in the period 20 shown in FIG. 4, and there is a possibility that data cannot be read in the period 20 after recording. The present invention has been made to solve such a problem, and an object of the present invention is to provide an EFM signal synchronization signal generator capable of eliminating data instability at the start of recording.

[0010]

According to the present invention, an EFM signal for recording original information on an optical disk storage medium is generated. Therefore, a reference signal generated based on a master signal composed of a local oscillator and a reference frequency is used. And a phase comparator that detects a phase difference between the output signal of the local oscillator, and a loop filter that sends a signal from which the disturbance noise included in the signal sent by the phase comparator is removed to the local oscillator,
A feedback loop is used to match the frequency and phase of the output signal of the local oscillator with the frequency and phase of the reference signal.
A synchronization signal generator for transmitting as an FM signal, the input side of which is connected to the output side of the phase comparator, the output side of which is connected to the input side of the loop filter, and a control signal from a certain time before the start of recording of the original information. It is characterized in that it is provided with signal sending means for sending the output signal from the phase comparator to the loop filter, and control means for sending the control signal to the signal sending means.

Further, according to the present invention, since the EFM signal for recording and reproducing the original information with respect to the optical disk storage medium is generated, the local oscillator and the EF reproduced from the optical disk are generated.
A first phase comparator for detecting a phase difference between an input signal based on the M signal and an output signal of the local oscillator, a reference signal generated based on a master signal having a reference frequency, and a position of the output signal of the local oscillator. A second phase comparator that detects a phase difference, a selector that selects and outputs either the output signal of the first phase comparator or the output signal of the second phase comparator, and the recording mode or the reproduction mode. Accordingly, a mode switch for sending a first control signal for selecting a signal to be sent from the selector to the selector, and disturbance noise contained in the signal sent by the selector are removed to output the output signal. A loop filter for sending to the local oscillator, and a feedback loop to match the frequency and phase of the output signal of the local oscillator with the frequency and phase of the input signal during reproduction A synchronizing signal generator for transmitting as an EFM signal in conformity with the frequency and phase of a quasi-signal, wherein the output signal from the second phase comparator is transmitted to the loop filter from a fixed time before the start of recording the original information. Thus, the control means is provided for sending a control signal to the mode switching device, and the mode switching device sends the first control signal when the control signal is supplied.

[0012]

With this structure, the signal sending means and the control means supply the signal to the loop filter from a certain time before the start of recording the original information. Therefore, when the recording operation is actually started, the signal is caused by the loop filter. A malfunction due to an indefinite EFM signal can be prevented, and stable writing of information can be performed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a sync signal generator for EFM signals of the present invention will be described below with reference to the drawings. Most of the components shown in FIG. 1 are the same as the components shown in FIG. In this embodiment, the mode switching unit 17 is provided with a terminal 30 for inputting a control signal, and the control signal input terminal 30 is, for example, a central processing unit for performing operation control in a system equipped with the EFM signal synchronization signal generator. 31 output terminals are connected.

In such a configuration, the EFM signal synchronizing signal generator in this embodiment performs the following operations. The central processing unit 31 connected to the control signal input terminal 30 sends a control signal for switching the mode to the mode switching unit 17 a certain time before the start of the recording operation.
The fixed time is a time required for the loop filter 16 to perform a stable operation, and the control signal is sent at the timing according to the linking rule described above. The mode switch 17 supplied with the control signal is
The first control signal is sent to the selector 15, and the selector 15 sends the signal sent by the first phase comparator 14 to the loop filter 1
Send to 6.

Instead of the central processing unit 31,
The control signal may be sent from a circuit having an internal register and a timer circuit. That is, by operating the value stored in the internal register in the central processing unit, the control signal is sent to the mode switch 17 after a lapse of a predetermined time.

As described above, in the present embodiment, as shown in FIG. 2, the signal is supplied from the first phase comparator 14 to the loop filter 16 to the loop filter 16 before the fixed time before switching to the recording mode. , EVCO due to PLL lock time delay when information recording actually starts
It is possible to prevent an erroneous operation due to the indefiniteness of 8 and to perform stable writing of information.

[0017]

As described above in detail, according to the present invention, since the signal is supplied to the loop filter from a certain time before the recording of the original information is started, when the recording operation is actually started. It is possible to prevent a malfunction due to the indefiniteness of the EFM signal caused by the loop filter, and to perform stable writing of information.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a sync signal generator for EFM signals of the present invention.

FIG. 2 is a timing chart showing the timing of control signals and the like supplied to the mode switch in the EFM signal synchronization signal generator shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional EFM signal synchronization signal generator.

FIG. 4 is a timing chart showing operation timings in the EFM signal synchronization signal generator shown in FIG.

[Explanation of symbols]

1 ... Crystal oscillator, 2 ... First clock generator, 8 ... EVC
O, 9 ... second clock generator, 11 ... first phase comparator,
14 ... 2nd phase comparator, 15 ... Selector, 16 ... Loop filter, 17 ... Mode changer, 30 ... Control signal input terminal, 31 ... Central processing unit.

Claims (3)

(57) [Claims] 1. Recording of original information with an optical disk storage medium,
A local oscillator, a first phase comparator for detecting a phase difference between an input signal based on the EFM signal reproduced from the optical disc and an output signal of the local oscillator, for generating an EFM signal for reproduction, and a reference. A second phase comparator that detects a phase difference between a reference signal created based on a master signal composed of frequencies and an output signal of the local oscillator; and the first phase comparator.
A selector for selecting and transmitting either the output signal of the phase comparator or the output signal of the second phase comparator, and a signal for transmitting from the selector according to the recording mode or the reproducing mode. The feedback loop comprises a mode switch for sending the first control signal to the selector, and a loop filter for removing the disturbance noise contained in the signal sent by the selector and sending the output signal to the local oscillator. A synchronizing signal generator for transmitting the frequency and phase of the output signal of the local oscillator to the frequency and phase of the input signal at the time of reproduction and the frequency and phase of the reference signal at the time of recording and transmitting as an EFM signal, A control signal is sent to the mode switch so that the output signal from the second phase comparator is sent to the loop filter from a certain time before the start of recording the original information. The EFM is provided with a control means for sending out, and the mode switching device sends out the first control signal by being supplied with the control signal.
Signal synchronization signal generator. 2. The EFM signal synchronization signal generator according to claim 1, wherein the control means is a central processing unit that controls the operation of a system having the EFM signal synchronization signal generator. 3. The EFM signal synchronization signal generator according to claim 1, wherein said control means has an internal register and a timer circuit, and sends said control signal in accordance with the setting of the value of said internal register.