JPH06338790A - Synchronous clock regenerating circuit - Google Patents

Abstract

PURPOSE:To perform the pull-in of a PLL to a correct phase-locked state without being disturbed by a spurious component by performing such control that a specific pattern inserted to an input digital signal in the pull-in process of the PLL is detected and the frequency of a reproducing clock signal can coincide with that of a targeted synchronous clock from a detected pulse. CONSTITUTION:The PLL 10 which performs the phase-lock of a digital input signal to which the specific pattern is inserted at every constant interval with the reproducing signal, and a pull-in control circuit 20 which performs the pull-in of the PLL circuit 10 to the correct phase-locked state are provided. The pull-in control circuit 20 is comprised of a circuit 21 which detects the specific pattern inserted to the input digital signal and generates a specific pattern detection pulse, and a circuit 2 which compares the frequency of the specific pattern detection pulse with that of the reproducing clock signal by conforming to the insertion interval of the specific pattern, and controls the frequency of the reproducing signal so as to be the one of integer times the frequency of the specific pattern detection pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for recovering a synchronous clock from an input signal, and more particularly to a synchronous clock recovery circuit used for extracting a synchronous clock from a digital signal modulated by a self-synchronizable modulation method. It is about.

[0002]

2. Description of the Related Art A PLL (Phase Locked Loop) circuit is usually used as a synchronous clock reproducing circuit for extracting and reproducing a synchronous clock from an input signal. This is to detect the phase difference between the input signal and the reproduction clock signal, and control the frequency or phase of the reproduction clock signal so that this becomes zero or a constant value, to obtain correct synchronization.

In the PLL circuit, if the frequency of the synchronous clock which is the clock component in the input signal and the frequency of the reproduced clock signal generated by the PLL circuit differ over a certain range, correct synchronization can be obtained. Retraction becomes impossible or difficult. Therefore, in the synchronous clock recovery circuit, some pull-in control circuit is set to P
Often provided with the LL circuit. For example, a method of sweeping the oscillation frequency of an oscillator that generates a reproduction clock signal is generally used.

[0004]

However, the input digital signal often contains a spurious component in addition to the pure frequency component of the synchronous clock. In the above method, one of the spurious components is a PLL circuit. May be accidentally drawn in. Once the PLL circuit is pulled into a certain spurious component and locks, the intensity of this spurious component decreases, or unless a disturbance that forcibly releases the locked state from the outside is given, the correct synchronization clock It becomes impossible to lock to the frequency. Further, even if the PLL circuit is not drawn into the spurious component, the spurious component may become a disturbance and the pull-in process of the PLL circuit may become unstable.

[0005]

In order to solve the above problems, the present invention provides a PLL circuit for synchronizing the phase of a digital input signal in which a specific pattern is inserted at regular intervals and a phase of a reproduced clock signal, A pull-in control circuit for pulling the PLL circuit into a correct synchronization state, and the pull-in control circuit detects the specific pattern inserted into the input digital signal at the constant intervals and outputs a specific pattern detection pulse. And a circuit for comparing the frequency of the specific pattern detection pulse and the frequency of the reproduction clock signal in correspondence with the insertion interval of the specific pattern. The target synchronization clock is controlled by controlling the frequency so that it becomes an integral multiple of the frequency of the specific pattern detection pulse determined by the pattern insertion interval. It is characterized in that to match the frequency of click.

Further, a judging circuit is provided for determining whether or not the frequency of the reproduced clock signal is within the pullable range of the PLL circuit, and the reproduced clock frequency is outside the pullable range according to the output of the judging circuit. When the above P
The control loop of the LL circuit is opened, and the control loop of the PLL circuit is closed when the reproduction clock frequency is within the pullable range.

Further, according to the output of the judgment circuit, when the reproduction clock frequency is out of the pullable range, the control loop of the pull-in control circuit is closed, and the reproduction clock frequency is in the pullable range. The control loop of the pull-in control circuit is opened.

[0008]

According to the above construction, in the pull-in process of the PLL circuit, the specific pattern inserted into the input digital signal at a constant interval is first detected, and the frequency of the reproduced clock signal is targeted from the frequency of the detected pulse. It is controlled to match the frequency of the synchronous clock. The fact that the frequency of the reproduction clock signal is controlled in this way means that the frequency of the reproduction clock signal is within the pull-in range of the PLL circuit. Therefore, from this state, the PLL circuit is pulled into the correct synchronization state easily and without being disturbed by spurious components.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments according to the present invention will be described below with reference to the drawings.

First, the first embodiment will be described. Figure 1
FIG. 1 is a diagram showing a configuration of a first embodiment when the present invention is applied to an optical digital video disc reproducing apparatus.
It should be noted that parts such as the servo circuit and the decoding circuit which are considered unnecessary for the explanation of the operation of the present invention are not shown and described.

In FIG. 1, a digital signal to be clock-reproduced is reproduced from a disc 1 by using an optical pickup 2. The signal recorded on the disc 1 is a digital signal obtained by converting information of a moving image or / and a still image or / and a sound into a digital signal, and further modulating by a modulation method capable of self-synchronization.

As a concrete example of this modulation method, 1 and 1
The number of consecutive 0s between and is limited to 4 or more and 22 or less, so-called (4,22) RLL (Run Leng)
thLimited) modulation. The (4,22) RLL has many spurious components in addition to the frequency component of the synchronization clock. In an actual disc, such a modulated code has a logical inversion at 1 and has a logical inversion at 0, that is, in the form of NRZI.

Further, as shown in FIG. 2, for example, a specific pattern A consisting of a series of 23T and 24T is inserted at a constant interval, where T is the period of a clock after modulation (so-called channel clock).

Hereinafter, the specific pattern A as shown in FIG. 2, which is inserted at regular intervals, is called a sync pattern. In addition, as shown in FIG. 2 below, the interval B from the head of one sync pattern to the head of the next sync pattern is N as the number of synchronization clocks. N has a value of 2030, for example.

The signal detected by the optical pickup 2 is input to the edge detection circuit 3. Edge detection circuit 3
Is to generate a pulse by detecting the rising and falling edges of the reproduction signal. The edge pulse detected by the edge detection circuit 3 becomes an input digital signal to the PLL circuit 10 and the pull-in control circuit 20. PL above
In the L circuit 10, the phase difference between the reproduced clock signal output from the voltage controlled oscillator 15 and the input digital signal is
Alternatively, a phase comparator 11 that detects a phase difference and a frequency difference and outputs a signal according to the difference is provided, and the difference signal is input to the loop filter 12. Loop filter 1
The output of 2 is applied to the control input terminal of the voltage controlled oscillator 15 through the switch 13 and the adder 14, the oscillation frequency of the voltage controlled oscillator 15 is changed according to this control voltage level, and the recovered clock signal which is the output is input. The control is performed so that the phase difference between the signals becomes zero or a constant value.

In the pull-in control circuit 20, the input digital signal is input to the sync pattern detection circuit 21. The sync pattern detection circuit 21 generates a sync pulse when the sync pattern is detected. The configuration is such that the sync pattern can be detected regardless of the frequency of the reproduction clock signal output from the voltage controlled oscillator 15.

This sync pulse is input to the frequency comparator 22. Furthermore, the reproduced clock signal is divided by 1 / N frequency divider 2
An output signal that is input to the frequency converter 3 and has the frequency of the reproduced clock signal set to 1 / N is output from the 1 / N frequency divider 23 and input to the frequency comparator 22. In this frequency comparator 22, the frequency of the sync pulse and the N of the reproduced clock signal are
A comparison with the fractional frequency is made. A signal corresponding to this frequency difference is output from the frequency comparator 22 and input to the loop filter 24. The output of the loop filter 24 is also applied to the control input terminal of the voltage controlled oscillator 15 through the adder 13 so that the oscillation frequency of 15 is varied according to the control voltage level, and the frequency of the output of the reproduced clock signal is divided by N. 1 is controlled so that the frequency of the sync pulse extracted from the input digital signal matches.

The pull-in possibility determination circuit 30 is a circuit for determining whether or not the frequency of the output reproduction clock signal is within the frequency range in which the PLL circuit 10 can be pulled in. The determination result is applied to the control input of the switch 13, and the switch 13 is closed when it is within the retractable range, and is opened when it is outside the retractable range.

Various methods are conceivable for determining whether or not it is within the pull-in range. For example, whether or not a specific pattern can be detected at a certain frequency or more by sampling an input digital signal with a reproduction clock signal. It can be realized by determining. A sync pattern or the like can be used as the specific pattern.

The synchronous clock regenerated by the clock regenerating circuit composed of these components is supplied to a demodulating circuit (not shown) together with the edge pulse, and is used for demodulating the information recorded on the disc.

The operation of the circuit of FIG. 1 will be described below. First,
The pull-in process from the input of the input digital signal to the synchronization of the recovered clock signal will be described.

When the PLL circuit 10 has not been pulled in and the frequency of the reproduced clock signal output from the voltage controlled oscillator 15 is out of the pullable range of the PLL circuit 10, the pull-up possibility determination circuit 30 outputs to switch. 13 is opened. At this time, the voltage controlled oscillator 15 is controlled only by the output of the pull-in control circuit 20.

The sync pattern detection circuit 21 detects a sync pattern from the input digital signal and outputs a sync pulse. Further, the 1 / N frequency divider 23 generates an output signal having a frequency of 1 / N of the reproduced clock signal from the reproduced clock signal output from the voltage controlled oscillator 15. The sync pulse and the output signal having a frequency of 1 / N of the reproduced clock signal are input to the frequency comparator 22. Frequency comparator 22, 1 / N frequency divider 23, loop filter 24,
By the control loop formed by the adder 14 and the voltage controlled oscillator 15, the frequency of the reproduced clock signal which is the output of the voltage controlled oscillator 15 is controlled so as to match N times the frequency of the sync pulse. When the frequency of the reproduced clock signal substantially matches N times the frequency of the sync pulse, the pull-in determination circuit 30 determines that the PLL circuit 10 can pull in and closes the switch 13. PLL
The circuit 10 starts the pull-in process, but since the frequency of the reproduced clock signal has already been controlled by the pull-in control circuit within the range in which the correct pull-in is possible, the correct pull-in is always performed, and thereafter, it is correctly synchronized with the input digital signal. Output the regenerated clock signal.

Next, due to some disturbance, the PLL circuit 10
Described below is the operation when synchronization is lost. In this case, if the frequency of the reproduced clock signal output from the voltage controlled oscillator 15 does not deviate from the pull-in range of the PLL circuit 10, the pull-in is correctly performed only by the PLL circuit 10. At this time, the pull-in control circuit 20 does not contribute much to the control of the voltage-controlled oscillator 15 because the difference between the frequency of the sync pulse and the frequency of the reproduced clock signal divided by N is small.

When the frequency of the reproduced clock signal output from the voltage controlled oscillator 15 is out of the pullable range of the PLL circuit 10, the pullable determination circuit 30 determines that it is outside the pullable range and opens the switch 13. At this time, the pull-in control circuit 20 controls the voltage-controlled oscillator 15 so that there is no difference between the frequency of the sync pulse and the frequency N of the reproduced clock signal, and the pull-in process described above is repeated.

Next, a second embodiment will be described. In the first embodiment, the error output of the phase comparator and the error output of the frequency comparator are input to separate loop filters, but in the second embodiment, the error output of each comparator is added. Consider a configuration in which a single loop filter is input from.

The circuit configuration in this case is shown in FIG. The input digital signal is the PLL circuit 40 and the pull-in control circuit 50.
And the pull-in possibility determination circuit 30. In the PLL circuit 40, the phase difference between the input digital signal and the reproduced clock signal output from the voltage controlled oscillator 15 is compared by the phase comparator 11, and this difference signal is passed to the loop filter 12 via the switch 41 and the adder 42. Is entered. The output of the loop filter 12 is applied to the control input of the voltage controlled oscillator 15. In the pull-in control circuit 50, the input digital signal is input to the sync pattern detection circuit 21,
Here, the sync pattern is detected. Further, the reproduced clock signal output from the voltage controlled oscillator 15 is the 1 / N frequency divider 2
3 is input, and the frequency of the reproduced clock signal is 1 /
An output signal of N is output from the 1 / N frequency divider 23 and input to the frequency comparator 22. Then, the frequency of the sync pulse and the 1 / Nth of the frequency of the reproduced clock signal output from the voltage controlled oscillator 15 are compared by the frequency comparator 22, and this difference signal is input to the adder 42.

The present invention is not limited to the first and second embodiments described above. When the PLL circuit becomes retractable, the loop of the PLL circuit is closed and the signal of the pull-in control circuit is added. In addition to the method of controlling the voltage-controlled oscillator by using the voltage control oscillator, for example, when the PLL can be pulled in, only the signal from the PLL circuit is used as the control input of the voltage-controlled oscillator to cut off the signal in the pull-in control circuit. It is also possible to adopt a configuration in which the control signal from the PLL circuit and the control signal from the pull-in control circuit are added and input to the voltage-controlled oscillator even in the pull-in process by eliminating the above.

[0029]

The synchronous clock recovery device according to the present invention is
PL that synchronizes the phase of the digital input signal in which a specific pattern is inserted at regular intervals with the recovered clock signal
Since the L circuit and the pull-in control circuit for pulling the PLL circuit into the correct synchronization state are included, when the PLL circuit is pulled in, the frequency component of the reproduction clock signal is extracted from the specific pattern inserted into the input digital signal at regular intervals. Since the method of making the frequency of the target synchronous clock substantially coincide with that of the target, even if the input signal has a spurious component other than the synchronous clock component, the PLL circuit is locked to the spurious component. This can be prevented in advance, and the effect that the correct synchronization clock component is always locked can be obtained.

[0030]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a synchronous clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing that specific patterns are inserted at regular intervals in a signal recorded on a disc.

FIG. 3 is a block diagram showing a configuration of a synchronous clock recovery circuit according to another embodiment of the present invention.

[Explanation of symbols]

 1 ... Disk 2 ... Optical pickup 3 ... Edge detection circuit 10, 40 ... PLL circuit 11 ... Phase comparator 12, 24 ... Loop filter 13, 41 ... Switch 14, 42 ... Adder 15 ... Voltage controlled oscillator 20, 50 ... Pull-in control circuit 21 ... Sync pattern detection circuit 22 ... Frequency comparator 23 ... 1 / N frequency divider 30 ... Retractable judgment circuit

Claims (3)

[Claims] 1. A PLL for synchronizing the phase of a reproduced clock signal with a digital input signal modulated by a self-synchronizable modulation method and having a specific pattern inserted at regular intervals.
And a pull-in control circuit for pulling the PLL circuit into a correct synchronization state. The pull-in control circuit detects the specific pattern inserted in the input digital signal at the constant intervals to detect a specific pattern. A circuit for generating a detection pulse, and a circuit for comparing the frequency of the specific pattern detection pulse and the frequency of the reproduction clock signal in correspondence with the insertion interval of the specific pattern, and for the frequency of the reproduction clock signal A synchronous clock recovery circuit is controlled so as to be an integral multiple of the specific pattern detection pulse frequency determined by the insertion interval of the specific pattern. 2. The frequency of the reproduced clock signal is the PL.
A determination circuit for determining whether or not the L circuit is within the pullable range, and when the reproduction clock frequency is outside the pullable range according to the output of the determination circuit, the control loop of the PLL circuit is opened; 2. The synchronous clock recovery circuit according to claim 1, wherein the control loop of the PLL circuit is closed when the recovery clock frequency is within the pullable range. 3. The control loop of the pull-in control circuit is closed when the reproduction clock frequency is out of the pull-in possible range according to the output of the judging circuit, and the reproduction clock frequency is in the pull-in range. 3. The synchronous clock recovery circuit according to claim 1, wherein the control loop of the pull-in control circuit is opened.