JPH0743890B2 - Digital signal transmission device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital signal transmission device applied to a digital VTR for recording / reproducing a digital video signal by a rotary head, for example.

[Outline of Invention]

According to the present invention, in a digital signal transmission device in which a digital signal whose inversion interval changes irregularly by channel coding is transmitted, the number of change points included in a predetermined period is counted, and the number information of the change points is pseudo-locked. Is coded by the channel coding which is hard to occur, and the number information of the change points subjected to the channel coding is added to the preamble period, so that the pseudo lock is prevented from occurring during the clock reproducing operation on the receiving side.

[Conventional technology]

When a digital information signal such as a digital video signal and a digital audio signal is recorded on a magnetic tape by a rotary head and the digital information signal is reproduced from the magnetic tape, the direct current component of the recorded / reproduced data is reduced or the run length is limited. Channel coding (also called digital modulation) is used for. Various types of channel coding are known. As a simple one, there is NRZ in which "1" of the digital information signal corresponds to a high level and "0" of the digital information signal corresponds to a low level, and inversion occurs at the boundary between bit cells. Further, when the digital information signal is "1", the inversion occurs at the center of the bit cell, and when the digital information signal is "0", the inversion occurs at the end of the bit cell, and the inversion is controlled according to the bit sequence pattern. M ² modulation is known.

On the playback side, NRZ, M ² modulation, 3
A clock is regenerated from data to which channel coding such as PM method and EFM modulation is applied. FIG. 5 shows the configuration of a conventional clock recovery circuit.

In FIG. 5, reproduction data channel-coded is supplied to an input terminal indicated by 31. This reproduction data is supplied to the comparator 32, and the waveform is shaped by the comparator 32. The reproduction signal having the pulse waveform from the comparator 32 is supplied to the D flip-flop 33, and is synchronized with the reproduction clock in the D flip-flop 33.
The recovered clock has a phase comparison circuit 34 and a low-pass filter 35.
And a VCO (voltage controlled oscillator circuit) 36. In the phase comparison circuit 34, the reproduction data and VCO36
The phase of the output signal is compared with the output signal of, and an output signal corresponding to the phase difference between the two is formed.
The error voltage from the low pass filter 35 is supplied to
Supplied from VCO 36. The reproduction signal from the D flip-flop 33 is the gate circuit 37 and the synchronization signal (SYNC) detection circuit 38.
Is supplied to the output terminal 39 and the predetermined length of data defined by the synchronization signal is output to the output terminal 39. The reproduced signal from the output terminal 39 is supplied to the channel coding decoder.

FIG. 6A shows a reproduction signal, and the reproduction signal is a time series with a set of a preamble, a synchronization signal and data as a unit. This data is channel-coded such as NRZ, M ² . A pulse signal having a frequency of, for example, 1/2 of the clock frequency is inserted in the preamble in order to easily pull in the PLL for clock reproduction.

FIG. 6B shows the error voltage from the low pass filter 35. FIG. 6C shows an enlarged part of the reproduction data. In the normal clock reproducing operation, the VCO 36 forms a clock synchronized with the reproduced data at the regular frequency from the reproduced data as shown in FIG. 6D.

[Problems to be solved by the invention]

In the PLL, when the reproduced clock is formed, the rising edge of the data shown in FIG. 6C and the rising edge of the clock are controlled to coincide with each other. However, as shown in FIG. 6C, when the data inversion interval changes irregularly due to channel coding, as shown in FIG. 6E due to temperature drift of the VCO 36 during a long inversion interval. , The frequency of the clock gradually shifts, and as a result, at the timing indicated by 40, the phases of the rising edges of the data and the clock coincide with each other.

The error voltage of the PLL becomes a constant voltage during the locked period 41, gradually changes during the unlocked period 42 where the clock frequency shifts, and becomes a constant voltage during the pseudo-lock period 43 after the timing 40. . The pseudo lock continues until it is cleared by the next change point in the data. During the pseudo lock period 43, the D flip-flop 33 does not correctly capture the reproduction data.

Therefore, an object of the present invention is to provide a digital signal transmission device in which pseudo lock during clock recovery is prevented.

[Means for solving problems]

According to the present invention, in a digital signal transmission device in which a digital signal in which the intervals of change points change irregularly by channel coding is transmitted, a change point counting circuit 9 for counting the number of change points included in a predetermined period of the digital signal. And an encoder 11 for supplying channel count information of the counted change points and performing channel coding in which pseudo lock is unlikely to occur, and an adder circuit 4 for adding the channel code number information of the change points to the preamble period. It is a digital signal transmission device.

[Action]

The number n of change points within a predetermined period (m clock period) of the digital signal defined by the synchronization signal is the change point counting circuit 9
Is counted in. The number of change points n is the encoder
11 and is coded by channel coding in which pseudo lock is less likely to occur. For example, bi-phase modulation, FM modulation, PM modulation or the like in which the difference between the maximum inversion interval and the minimum inversion interval is relatively small is used. The data of the number n of change points from the encoder 11 is added to the preamble period in the adder circuit 4.

At the receiving side, the number N of change points of the recovered clock within the m number of periods is detected for the received data.
Further, the data of the number n of change points inserted in the preamble period is decoded. The magnitude relationship between the number of change points n and N is examined. It is normal that the two match. If a pseudo lock occurs, the two do not match and a correction voltage that forcibly shifts the oscillation frequency is added to the VCO of the PLL for clock recovery, and the pseudo lock is quickly eliminated. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the recording side (or the transmission side),
A digital information signal (video signal, audio signal, etc.) recorded at the input terminal 1 is supplied. This digital information signal is supplied to the encoder 2 and coded for channel coding (M ² modulation, NRZ, 3PM, EFM, etc.). The digital data from the encoder 2 is the delay circuit 3
Is supplied to the adder circuit 4 via. The adder circuit 4 adds the synchronizing signal and the signal in the preamble period, and the record data is taken out to the output terminal 5 of the adder circuit 4. This recorded data is recorded on a magnetic tape by, for example, a rotary head. The encoder 2 uses channel coding that can sufficiently reduce the DC component or limit the run length.

A clock having a bit frequency synchronized with the digital information signal is supplied from the input terminal indicated by 6. This clock is supplied to the counter 7 and counted by the counter 7. The counter 7 is reset by the synchronizing pulse from the terminal 10, and a pulse signal which becomes "1" in the period Tm of m clocks from the timing of the synchronizing pulse is obtained from the counter 7. The pulse signal from the counter 7 is supplied to the gate circuit 8. In the gate circuit 8, the portion of the output signal of the encoder 2 during the period Tm is gated.

The output signal of the gate circuit 8 is supplied to the change point counting circuit 9. The change point counting circuit 9 is reset by a synchronization pulse, a data transition within the period Tm is detected, and the number n of detected change points is counted. The number n of the change points is supplied to the encoder 11. In the encoder 11, a code signal representing the number n of change points is channel coded. Since the encoder 11 only needs to modulate the code signal having a bit number sufficiently smaller than that of the data, the suppression of the DC component or the limitation of the run length is not considered so much, and the encoder 11 is unlikely to cause the pseudo lock. In other words, the system, that is, the system in which the difference between the maximum inversion interval and the minimum inversion interval is small (bi-phase modulation, FM, PM, etc.) is used. The output signal of the encoder 11 is supplied to the adder circuit 4 and inserted in the preamble period.

Further, the sync pulse is supplied to the sync signal generation circuit 12 to generate a sync signal added to the head of data of a predetermined length (called one frame, one block). The sync signal has a unique bit pattern so as to be distinguished from the data in the preamble period and the data in the data period.

FIG. 2 is a time chart showing the operation of the configuration on the recording side. FIG. 2A shows a digital information signal from the input terminal 1. The digital information signal is provided with a data lack period corresponding to the preamble period and the sync signal period, respectively. Further, a synchronizing pulse of a timing that coincides with the timing of the beginning of the data period of the input digital information signal is supplied from the input terminal 10, and the synchronizing pulse resets the counter 7 and the change point counting circuit 9.

The counter 7 generates the pulse signal shown in FIG. 2C which becomes "1" in the period Tm in which the m clocks from the input terminal 6 are being counted. The period Tm is, for example, about half the length of the data period. The length of this period Tm is selected as an appropriate length in consideration of the channel coding method used, the length of the data period, and the like. Gate circuit 8 is a period
It is turned on at Tm, and the number n of change points included in the period Tm is counted by the change point counting circuit 9.

The output data of the encoder 2 is delayed by the delay circuit 3 for the time Td. At the output terminal 5, as shown in FIG. 2D, recorded data composed of a preamble period in which code signals of the number n of change points are modulated and inserted, a synchronizing signal and modulated data are obtained.

The above recording data is recorded on the magnetic tape by the rotary head. Further, the reproduction data taken out from the magnetic tape by the rotary head is supplied to the reproduction-side input terminal 21 shown in FIG.

The reproduction data is supplied to the phase comparison circuit 22 and compared in phase with the clock pulse from the VCO 23. The output signal of the phase comparison circuit 22 is supplied to the addition circuit 25 via the low pass filter 24, and the error voltage from the addition circuit 25 is supplied to the control terminal of the VCO 23. The phase comparison circuit 22, the VCO 23, and the low-pass filter 24 constitute a PLL for clock reproduction. The adder circuit 25 is supplied with the correction voltage generated by the switch circuit 26. Further, the reproduction clock generated in the VCO 23 is taken out to the output terminal 27 and used for latching reproduction data in the subsequent stage.

Reference numeral 28 represents a sync signal detection circuit for detecting a sync signal from the reproduced data. The detected synchronization signal is taken out at the output terminal 29. Since data having a bit pattern that facilitates self-clocking is inserted in the preamble period, the PLL locks right after the preamble period, and thus the synchronization signal is correctly detected. In addition, the reproduction sync signal and the clock are gate pulse generation circuits.
Supplied to 30. The gate pulse generated by the gate pulse generation circuit 30 is supplied to the gate circuit 31. Gate circuit 31
Selects the preamble period in the playback data,
The data in the preamble period is supplied to the decoder 32.
The decoder 32 decodes the channel coding of the data in the preamble period, and the decoder 32 determines the number n of change points.
A code signal indicating is obtained. This code signal is supplied to the comparison circuit 33.

The clock formed by the VCO 23 is supplied to the counter 34. The counter 34 is reset at the beginning of the data period by the reproduction sync signal from the sync signal detection circuit 28. The counter 34 forms a pulse signal which becomes "1" in the period Tm of m clocks from the beginning of the data period. The pulse signal shown in FIG. 4B in association with the reproduced data shown in FIG. 4A is generated by the counter 34. This pulse signal is supplied to the change point counting circuit 35 as an enable signal. In the change point counting circuit 39, the transition of the reproduced data from “0” to “1” or “1” to “0” is detected, and the change point within the period Tm defined by the pulse signal from the counter 34 is detected. Number N
Are counted. As shown in FIG. 4C, the change point counting circuit
At 35, the count value sequentially changes to (0 → 1 → ... N).

The code signal indicating N from the change point counting circuit 35 is the comparison circuit.
The value of N is supplied to 33, and the value of n indicated by the code signal from the decoder 32 is compared by the comparison circuit 33. The comparator circuit 33 detects three relationships (N = n) (N> n) (N <n), and forms an output signal according to these three relationships. The state of the switch circuit 26 is controlled by the output signal from the comparison circuit 33.

The switch circuit 26 has a terminal a grounded (0 V), a terminal b to which a positive correction voltage + V is supplied, and a terminal c to which a negative correction voltage -V is supplied. Any one of these terminals a, b, c is selected, and the output voltage of the switch circuit 26 is the adder circuit.
Supplied to 25. As described above, the adder circuit 25 is supplied with the PLL error voltage from the low-pass filter 24, and the sum of the correction voltage and the error voltage obtained from the adder circuit 25 is supplied to the VCO 23.

In the case of (N = n), the terminal a in the switch circuit 26
Is selected and the VCO 23 is supplied with only the error voltage of the PLL (N = n), which means that the PLL is correctly locked with the reproduction data.

In the case of (N> n), the terminal b in the switch circuit 26
Is selected, and the VCO 23 is supplied with a voltage that is the sum of the correction voltage (+ V) and the error voltage. In the state of (N> n), the period Tm of “1” of the pulse signal generated by the counter 24 is long,
That is, it means that the frequency of the clock formed by the VCO 23 is lower than the regular frequency. Therefore, the correction voltage (+ V) is added to the VCO 23 together with the error voltage, and the oscillation frequency of the VCO 23 is forcibly increased.

In the case of (N <n), the terminal c in the switch circuit 26
Is selected, and the VCO 23 is supplied with a voltage that is the sum of the correction voltage (-V) and the error voltage. The state of (N <n) is
Contrary to the state of (N> n), it means that the frequency of the clock formed by the VCO 23 is higher than the regular frequency. Therefore, the correction voltage (-V) is added to the VCO 23 together with the error voltage, and the oscillation frequency of the VCO 23 is forcibly lowered.

The correction voltage described above prevents the PLL from being pseudo-locked, and the read data is correctly captured by the latch circuit.

〔The invention's effect〕

According to the present invention, it is possible to reliably prevent the pseudo lock from occurring when the clock is extracted from the reproduced data by the self-clock method on the reproducing side or the receiving side. Further, in the present invention, since the preamble period is used, there is an advantage that the redundancy does not increase.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
FIG. 2 is a time chart used for explaining the operation of one embodiment of the present invention, FIG. 3 is a block diagram showing a configuration of a side for reproducing data transmitted by applying the present invention, and FIG. A time chart used for explaining the operation, FIGS. 5 and 6 are a block diagram of a conventional clock extraction circuit and a time chart for explaining the same. Description of main symbols in the drawings 1: Digital information signal input terminal, 2, 11: Channel coding encoder, 7: Counter, 9: Change point counting circuit.

Claims (1)

[Claims] 1. A digital signal transmission apparatus for transmitting a digital signal in which the intervals of change points are irregularly changed by channel coding, and means for counting the number of change points included in a predetermined period of the digital signal. It is provided with means for performing channel coding in which the number information of the counted change points is supplied and pseudo-lock is less likely to occur, and means for adding the number information of the change points subjected to the channel coding to a preamble period. Characteristic digital signal transmission device.