JP2800772B2 - Clock extraction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extracting circuit for reproducing a bit clock from an encoded signal, and more particularly, to a clock extracting circuit suitable for extracting a clock from a file device using an optical disk, a magnetic disk or the like. The present invention relates to a clock extraction circuit.

[0002]

2. Description of the Related Art In a file apparatus using a disk such as an optical disk or a magnetic disk, the data rate of a signal to be reproduced usually fluctuates by about 1% due to uneven rotation of the disk. In order to obtain correct detection data from such a reproduced signal, a PLL (PhaseL) that sets a clock frequency according to the fluctuation is used.
A clock extraction circuit using an ocked loop circuit is required.

[0003] A signal recorded in a file device is generally a data string that has been subjected to a specific coded modulation. In such a data sequence, an RLL code (Run Length Limited) that limits the continuation of the same value is often used. Since these codes do not have a special clock for extracting a clock from the self-clock, that is, the data string itself, control by frequency comparison cannot be performed.

FIG. 8 shows a configuration of a conventional clock extracting circuit. This circuit is constituted by a PLL circuit. A reproduction signal 101 read from a file device (not shown) passes through a phase comparator 102, a loop filter 103, and a voltage controlled oscillator (VCO) 104, and an extraction clock 105 is output. The extracted clock 105 is input to the phase comparator 102, and the reproduced signal 10
1 is detected. For example, the timing at which the polarity of the reproduction signal 101 changes and the extracted clock 1
Detection of the phase difference at the rise of 05 is performed, and a signal 106 proportional to this difference is output. Loop filter 10
Reference numeral 3 denotes a low-pass filter having appropriate frequency characteristics. The signal 107 having passed through the loop filter 103 and having its frequency characteristics adjusted is input to the voltage controlled oscillator 104, and an extraction clock 105 having a frequency corresponding to the input voltage is output. In this manner, the extracted clock 1 having an appropriate frequency response characteristic by the feedback system
05 will be obtained.

[0005]

The oscillation frequency of the PLL circuit obtained as the extraction clock 105 and the reproduction signal 10
If the frequency differs from one channel bit rate, it is necessary to synchronize the phase and simultaneously pull in the frequency. However, the obtained reproduction signal 101 is a data string that has been coded and modulated as described above, and its cycle is not constant. For this reason, it is not expected that the frequency of the reproduction signal 101 is compared with the frequency of the extracted clock 105 to perform the frequency pull-in. Therefore, if the free-run frequency as the oscillation frequency when no input signal is supplied to the PLL circuit is significantly different from the data rate of the reproduction signal 101, synchronization cannot be ensured.

On the other hand, the reproduction signal 101 and the extracted clock 10
In the case where the frequency deviation of No. 5 is relatively small, the leading and lagging phases appear alternately in a cycle determined by the deviation.
Thus, this makes it possible to achieve synchronization by gradually approaching the frequency in the direction of coincidence.

In general, the capture range based on frequency comparison alone, that is, the range in which the frequency can be pulled in, cannot be more than a few percent of the oscillation frequency. For this reason, if there is a possibility that the data rate of the reproduction signal may change significantly, it is necessary to reset the oscillation frequency range to a value close to the data rate of the reproduction signal 101 by using a technique such as switching the free-run frequency. was there. In the case of a disc recorded with a constant linear velocity, the number of rotations of the disc per unit time is changed when the reproduction track changes. For this reason, in the case immediately after the reproduction track has changed greatly, it is difficult to know the approximate data rate due to the fluctuation of the rotation speed of the disk. Therefore, in such a case, it has been difficult to secure synchronization with the reproduction signal 101 until a relatively stable rotation of the disk is obtained after the reproduction track is changed.

An object of the present invention is to provide a clock extracting circuit having a wide capture range and excellent responsiveness.

[0009]

According to the first aspect of the present invention, (a) a reproduced signal obtained by reading out a data series encoded and stored in a predetermined disk device, and a reproduced signal extracted from the reproduced signal. (B) a first phase comparator for inputting an extracted clock and extracting a phase error between the two.
A second phase comparator for inputting the reproduced signal and the extracted clock and extracting a phase error of a positive polarity and a phase error of a negative polarity, and (c) selecting the outputs of the first and second phase comparators (D) a loop filter for adjusting the frequency characteristics of the signal output from the selection circuit;
(E) a voltage-controlled oscillator that receives the signal that has passed through the loop filter and generates the extracted clock having a frequency corresponding to the input voltage, and (f) a comparison between the period of the extracted clock and the reproduced signal. And a rate comparison circuit for determining whether the frequency of the extracted clock is higher or lower than the frequency of the reproduction signal by detecting a state where the mark length defined in the reproduction signal is out of the limit. A synchronization judging circuit for judging whether or not the extracted clock and the reproduced signal are synchronized; and (h) when the synchronization judging circuit judges that the synchronization is established, the first When the phase comparator is selected and it is determined that synchronization is not achieved, an output having a polarity corresponding to the output of the rate comparison circuit in the second phase comparator is selected. A 択回 path control means is provided to the clock extraction circuit.

That is, according to the first aspect of the present invention, the first phase comparator inputs a reproduced signal and an extracted clock extracted from the reproduced signal and extracts a phase error between the two.
Further, the second phase comparator receives the reproduction signal and the extracted clock and extracts the positive and negative phase errors, respectively.
The reproduced signal has characteristics in the waveform of the obtained signal in accordance with the restriction on the run length included in the code word and the equalization method. For example, a code used for recording and reproducing a CD (compact disk) has a restriction that the mark length is 3T or more and 11T or less when the period of the extracted clock is T, so that the polarity of the reproduced signal is The time until the inversion takes a value between 3T and 11T. Therefore,
The period T of the extracted clock extracted from the clock extraction circuit
When the polarity of the reproduced signal changes at intervals shorter than 3T, it can be determined that the oscillation frequency of the extracted clock is higher than the bit rate of the reproduced signal. Similarly, 1
When the change in polarity is detected at intervals longer than 1T, it is understood that the oscillation frequency of the extracted clock is low.

According to the first aspect of the present invention, the output polarity of the phase comparator is controlled while the frequency synchronization is not established, according to the level of the oscillation frequency detected in this way. The determination as to whether or not synchronization has been established can be made by detecting whether or not the difference between the phase of the reproduced signal and the phase of the extracted clock falls within a certain range. If the frequencies do not match, a state in which the phase error is large at a certain frequency or more always appears between the two. For example, in such a case, assuming that the frequency is not synchronized, the selection circuit selects a phase error signal of either polarity of the second phase comparator. As a result, the frequency of the extracted clock is always controlled in the correct direction.

Therefore, even when the data rate of the reproduced signal changes greatly, normal pull-in can be expected without externally changing the free-run frequency. Further, even when the data rate of the reproduction signal is not clear or changes, the frequency of the extracted clock can be automatically controlled so as to be close to the data rate of the reproduction signal. Thus, the responsiveness to a change in frequency is improved.

According to the second aspect of the present invention, (a) a reproduced signal obtained by reading a data sequence encoded and stored in a predetermined disk device and an extracted clock extracted from the reproduced signal are input. A first phase comparator for extracting the phase error between the two, and (b) a state in which the period of the extracted clock is compared with the reproduced signal and the mark length defined in the reproduced signal is out of the limit. (C) a rate comparison circuit that determines whether the frequency of the extracted clock is higher or lower than the frequency of the reproduction signal by detecting
A second phase comparator for inputting the reproduced signal, the extracted clock and the comparison result of the rate comparison circuit, and extracting a positive or negative phase error according to the comparison result; And a selection circuit for selecting the output of the second phase comparator; (e) a loop filter for adjusting the frequency characteristics of the signal output from the selection circuit; A voltage-controlled oscillator for generating the extracted clock having a frequency corresponding to the input voltage; (g) a synchronization determining circuit for determining whether the extracted clock is synchronized with the reproduced signal; If the synchronization determination circuit determines that synchronization is achieved, the first phase comparator is selected. If it is determined that synchronization is not achieved, the second phase comparator is selected. A selection circuit control means for selecting the comparator is provided to the clock extraction circuit.

The differences between the invention of claim 2 and the invention of claim 1 are as follows. According to the first aspect of the present invention, the second phase comparator inputs the reproduced signal and the extracted clock to extract the positive and negative phase errors, respectively. A comparison result of the comparison circuit is also input, and a positive or negative phase error is selectively output according to the comparison result. Therefore, the selection circuit according to the second aspect of the present invention simply selects one of the outputs of the first and second phase comparators. When selecting the output of the phase comparator 2
The output of the polarity according to the output of the rate comparison circuit is selected. Except for this, the principle is the same as that of the first aspect.

According to the third aspect of the present invention, (a) a reproduced signal obtained by reading a data sequence encoded and stored in a predetermined disk device and an extracted clock extracted from the reproduced signal are input. A first phase comparator for extracting the phase error between the two, and (b) a state in which the period of the extracted clock is compared with the reproduced signal and the mark length defined in the reproduced signal is out of the limit. (C) a rate comparison circuit that determines whether the frequency of the extracted clock is higher or lower than the frequency of the reproduction signal by detecting
A second phase comparator that inputs the reproduced signal, the extracted clock, and the comparison result of the rate comparison circuit and extracts a positive or negative phase error according to the comparison result; and (d) the second phase comparator. A first loop filter for adjusting a frequency characteristic of a signal output from the first phase comparator;
A second loop filter for adjusting the frequency characteristic of the signal output from the second phase comparator, and
An adder for adding the output of the second loop filter, and (g) a voltage-controlled oscillator that receives the signal added by the adder and generates the above-described extracted clock having a frequency corresponding to the input voltage. H) a synchronization determination circuit for determining whether or not the extracted clock is synchronized with the reproduced signal; and (iii) the synchronization determination circuit determines if the synchronization determination circuit is synchronized. When the first phase comparator and the first loop filter are connected to each other and it is determined that synchronization is not established, the second phase filter is used.
And a switch circuit for conducting between the phase comparator and the second loop filter.

That is, in the third aspect of the present invention, similarly to the second aspect of the present invention, the second phase comparator also receives the comparison result of the rate comparison circuit and outputs the positive or negative polarity according to the comparison result. Although a phase error is extracted, a first loop filter is further provided corresponding to the first phase comparator, and a second loop filter is provided corresponding to the second phase comparator. An adder is provided on the output side to add the outputs, and the result is input to the voltage controlled oscillator, and only one output of the first and second loop filters is selectively used. A switch circuit is prepared so as to be input to the adder. Except for this, the principle is the same as that of the first aspect.

It should be noted that, in the invention according to claims 1 to 3,
The synchronization determination circuit may perform the determination based on the phase comparison for detecting whether or not the phase difference between the bit clock and the data series exceeds a predetermined value. Further, the data series may be, for example, code data having an RLL limit. In this case, the above-described rate comparison circuit may operate by detecting a state in which the mark length is out of the limit defined by the RLL limit. I just need.

According to a fourth aspect of the present invention, the rate comparison circuit according to the first to third aspects of the present invention determines that the upper limit of the mark length of the data series with respect to the extracted clock is exceeded. When the detection is performed, a flag indicating that the oscillation frequency is high is set, and when it is detected that the oscillation frequency is below the lower limit of the mark length, the flag is lowered, and in other cases, the current flag state is maintained. It is characterized by performing a hysteresis operation.

According to a fifth aspect of the present invention, the rate comparing circuit according to the first to third aspects of the present invention is arranged such that the rate comparison circuit sets the data sequence based on a time interval in which the data sequence takes a predetermined constant amplitude value. It is characterized in that it is detected whether or not the limit of the mark length is exceeded.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of a clock extracting circuit according to an embodiment of the present invention. A reproduction signal 11 read from a file device (not shown) is input to a phase error extraction circuit 12 of the clock extraction circuit of the present embodiment, and is also input to a synchronization determination circuit 13 and a rate comparison circuit 14. I have. A phase error signal 15 output from the phase error extraction circuit 12 is input to a loop filter 16, and an output 17 of the signal is applied to a voltage controlled oscillator (VCO) 18.
And an extraction clock 19 is created. The extracted clock 19 is fed back to the phase error extraction circuit 12, and is also input to the synchronization determination circuit 13 and the rate comparison circuit 14.
The synchronization determination circuit 13 sends a synchronization flag 21 to the phase error extraction circuit 12, and the rate comparison circuit 14 sends a rate flag 22 to the phase error extraction circuit 12.

In the clock extracting circuit having such a configuration, the phase error extracting circuit 12 includes the reproduced signal 11 and the extracted clock 19.
Is used to extract the phase error between the two. The method of extracting the phase error at this time is selected by the synchronization flag 21 input from the synchronization determination circuit 13 and the rate flag 22 input from the rate comparison circuit 14. This operation will be described later in detail.

The phase error signal 15 output from the phase error extraction circuit 12 is input to a loop filter 16. The loop filter 16 is composed of a low-pass filter, similarly to the conventional circuit described with reference to FIG. The signal 17 which has passed through the loop filter 16 and whose high frequency has been removed is input to a voltage controlled oscillator 18, and an extraction clock 19 having a frequency corresponding to the voltage is output. The extracted clock 19 is fed back to the phase error extraction circuit 12 to generate a PLL.
A circuit portion is configured.

In the clock extraction circuit of the present embodiment, this P
A synchronization determination circuit 13 and a rate comparison circuit 14 are provided in addition to the LL circuit. Rate comparison circuit 1
4 inputs the reproduced signal 11 and the extracted clock 19 and monitors whether the bit rate of the extracted clock 19 is higher or lower than the bit rate of the reproduced signal 11. Then, the result is output as the rate flag 22. Such a monitoring result can be obtained, for example, by detecting an interval of polarity inversion appearing in the reproduction signal 11.

As an example, codes used for recording and reproducing CDs are restricted so that the mark length is 3T or more and 11T or less. When the upper limit and the lower limit are set as in this example, the interval until the polarity of the reproduction signal 11 is inverted takes a value from 3T to 11T. Therefore, with respect to the period T of the extraction clock 19, the reproduction signal 11
Is changed at intervals shorter than 3T, the oscillation frequency of the extracted clock 19 is low.
Conversely, when the frequency changes at intervals longer than 11T, the oscillation frequency of the extracted clock 19 is high. The rate flag 22 outputs such a determination result.

On the other hand, the synchronization determination circuit 13 detects whether or not the reproduction signal 11 and the extracted clock 19 are synchronized, and outputs the result as a synchronization flag 21. Such a synchronization determination can be made, for example, based on whether or not the time difference between the timing of the polarity change of the reproduction signal 11 and the timing of the rise of the extracted clock 19 is equal to or smaller than a predetermined small value. If the time difference between the two is equal to or less than this value, the synchronization flag 21 is set so that the phase error extraction circuit 12 operates in the same manner as the conventional phase comparator 102 shown in FIG.

FIG. 2 shows a specific configuration of the phase error extraction circuit. The phase error extraction circuit 12 of the present embodiment includes a phase comparator 31 and a phase comparator 3
2 and a selector 35 which receives the phase error signals 33 and 34 as outputs and selects one of them. The reproduction signal 11 and the extracted clock 19 are input to both the phase comparator 31 and the phase comparator with polarity designation 32. The synchronization flag 21 output from the synchronization determination circuit 13 shown in FIG. 1 is input to the selector 35, and the rate flag 22 output from the rate comparison circuit 14 shown in FIG. Is input to The phase comparator 31 is a conventionally used circuit, for example, a circuit of the same type as the phase comparator 102 shown in FIG.
The polarity comparator with polarity designation 32 changes the polarity of the phase error signal 34 according to the input rate flag 22. The selector 35 selects the phase error signal 33 as the output of the phase comparator 31 when the synchronization flag 21 is set, and otherwise selects the phase error signal 34 as the output of the phase comparator 32 with polarity designation. Is to be selected.

FIG. 3 shows waveforms at various parts of the phase comparator shown in FIG. FIG. 7A shows the reproduction signal 11.
FIG. 3B shows the waveform of the extracted clock 19. Phase comparator 3 shown in FIG.
1 outputs a phase error signal 33 from the rising edge of the extracted clock 19 closest to the polarity inversion timing of the reproduction signal 11, as shown in FIG.
The phase error signal 33 is generated when the timing of the polarity change of the reproduction signal 11 is delayed with respect to the rising edge of the extraction clock 19, that is, when the rising edge of the extraction clock 19 precedes the zero cross point of the reproduction signal 11. , A positive pulse having a pulse width corresponding to the delay. Conversely, when the timing of the polarity change of the reproduction signal 11 is advanced with respect to the rising edge of the extraction clock 19, that is, when the rising edge of the extraction clock 19 is later than the zero-cross point of the reproduction signal 11, the timing is advanced. Is a negative polarity pulse having a pulse width corresponding to. The phase error signal 33 is output from the selector 35 as the phase error signal 15 when the synchronization flag 21 is set.

On the other hand, the phase comparator with polarity designation 32
Is output by the selector 35 when the synchronization flag 21 is not set, and is output as the phase error signal 15. This phase error signal 34 is
Rate flag 2 input to phase comparator 32 with polarity designation
2, the output form differs.

First, the case where the rate flag 22 indicates that the frequency of the extracted clock 19 is lower than the bit rate of the reproduced signal 11 will be described. In this case, as shown in FIG. 3D, the phase comparator with polarity designation always outputs the phase difference between the polarity change of the reproduction signal 11 and the preceding rising edge of the extracted clock 19 as the phase error signal 34. I do. At this time, the phase error signal 34 always has a positive polarity. When the phase error signal 34 shown in FIG. 3D is applied to the loop filter 16, the control voltage of the voltage controlled oscillator 18 gradually increases, and the frequency of the extracted clock 19 approaches the bit rate of the reproduced signal 11. become.

Conversely, when the rate flag 22 indicates that the frequency of the extracted clock 19 is higher than the bit rate of the reproduced signal 11, the phase comparator with polarity designation 32 outputs, as shown in FIG. The phase difference between the polarity change of the reproduction signal 11 and the succeeding rising edge of the extracted clock 19 is always output as the phase error signal 34. At this time, the phase error signal 34 always has a negative polarity. Therefore, when the phase error signal 34 shown in FIG. 3E is applied to the loop filter 16, the control voltage of the voltage controlled oscillator 18 gradually decreases, and the frequency of the extracted clock 19 becomes lower than the bit rate of the reproduced signal 11. You will get closer.

When the bit rate of the reproduced signal 11 and the frequency of the extracted clock 19 approach each other, the phase error between the two becomes relatively small. Accordingly, the frequency at which the synchronization determination circuit 13 shown in FIG. 1 sets the synchronization flag increases. As a result, the phase error extraction circuit 12 shifts to the phase comparison mode using the phase comparator 31 similarly to the conventional clock extraction circuit shown in FIG. As long as the bit rate of the reproduction signal 11 does not greatly change, the extraction clock 19
Changes slowly following this.

FIG. 4 shows the configuration of the rate comparison circuit shown in FIG. The rate comparison circuit 14 includes a binarization circuit 41 for inputting the reproduction signal 11 and an extraction clock 1
9; a unit pulse generating circuit 42 for inputting a 9; an edge detecting circuit 44 for inputting binarized data 43 output from the binarizing circuit to detect an edge; A difference circuit 47 for inputting a unit pulse 46 output from the multiplexing circuit, an integrator 50 for inputting an output pulse 49 of the difference circuit 47 and an edge detection signal 48 output from the edge detection circuit 44 for integration, and A determiner 52 for determining when the output 51 of the integrator 50 becomes negative, a timer 54 for inputting the determination result 53 of the determiner 52, and an SR flip-flop circuit 55 for inputting the same to the set terminal (S) It is composed of The output 56 of the timer 54 is input to the reset terminal (R) of the SR flip-flop circuit 55. The rate flag 22 is output from the SR flip-flop circuit 55, and is input to the phase error extraction circuit 12 described with reference to FIG.

FIG. 5 shows waveforms at various parts of the rate comparison circuit having such a configuration. The operation of the rate comparison circuit 14 will be described with reference to FIG. However, the waveforms of the respective parts shown in FIG. 5 are those at different points in time from the waveforms of the respective parts shown in FIG. The reproduction signal 11 shown in FIG. 5A is input to the binarization circuit 41, and outputs binarized data 43 binarized using the zero level as a threshold as shown in FIG. 5C. The binarized data 43 is input to the edge detection circuit 44. The edge detection circuit 44 is in a state where the binarized data 43 is at the H (high) level,
The rising edge of the extracted clock 19 shown in FIG. This edge detection signal 4
8 is given to the unit pulse generation circuit 42 as a trigger signal. The unit pulse generating circuit 42 is constituted by, for example, a one-shot multivibrator, and outputs a unit pulse 46 composed of a pulse having a predetermined time width as shown in FIG. .

The difference circuit 47 outputs an output pulse 49 as a result of subtracting the unit pulse 46 from the binary data 43 as shown in FIG. This output pulse 4
9 is positive in a section where only the binarized data 43 is present, and is negative in a section where only the unit pulse 46 is present. In the section where both the binarized data 43 and the unit pulse 46 exist, the output pulse does not appear because it is canceled. The output pulse 49 is input to the integrator 50 together with the edge detection signal 48, and each time the edge detection signal 48 outputs a detection timing, the integration of the output pulse 49 is repeated (FIG. 9 (f)).

The determiner 52 determines whether or not the output of the integrator 50 becomes negative. That is, the binarization circuit 4
When the pulse width of the binarized data 43 (FIG. 4C) output from 1 is longer than the pulse width of the unit pulse 46 (FIG. 4D), the output of the integrator 50 always takes a positive value. Take. On the other hand, when the pulse width of the binarized data 43 is shorter, the output of the integrator 50 takes a negative value. When the output of the integrator 50 becomes negative, the determiner 52 changes the determination result 53 to the H level as shown in FIG. Thereby, the SR flip-flop circuit 5
5 is set, and the H-level rate flag 22 is output.

The determination result 53 is also provided to a timer 54. When the signal level of the determination result 53 does not change to the H level for a certain period of time,
The output is changed to H level. At this point, the SR flip-flop circuit 55 is reset and the rate flag 2
2 will return to the L (low) level.

Modification

FIG. 6 shows a rate comparison circuit as a modification of the present invention. 6, the same parts as those in FIG. 4 of the previous embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In this modification, the recording code is RLL.
A rate comparison circuit 14A applicable to the case of a code is shown. The reproduced signal 11 is input to a binarization circuit 41 and binarized. The edge detection circuit 44 outputs the binarized data 43
Is at the H (high) level, the rising edge of the extracted clock 19 is output as the edge detection signal 48. Then, the edge detection signal 48 is supplied to both the 3T pulse generation circuit 61 and the counter 62 as a trigger signal.

For example, EFM (Eight to Fourteen Mo) used for recording and reproduction of a CD (compact disk)
dulation) code, the polarity inversion interval of the reproduction signal 11 is limited to 3T or more and 11T or less. 3T
The pulse generation circuit 61 outputs a pulse 64 for three periods of the extraction clock 19 following the edge detection signal 48. Therefore, by using the pulses 64 for the three cycles, the decision result 53 for setting the SR flip-flop circuit 55 can be output from the decision unit 52 similarly to the rate comparison circuit 14 shown in FIG. it can.

In the modified rate comparison circuit 14A,
The output 56 to be input to the reset terminal of the SR flip-flop circuit 55 can be configured using the counter 62 and the comparator 67. That is, the counter 62 outputs the edge detection signal 48 of the edge detection circuit 44 and the extracted clock 1
9 is input, and the extraction clock 19 is counted and reset by the edge detection signal 48. In this modification, the polarity inversion of the reproduction signal 11 is equal to or greater than 11T.
If it exceeds T, it can be seen that the frequency of the extracted clock 19 is higher than the bit rate of the reproduced signal 11.

The comparator 67 receives the count value 68 output from the counter 62 and performs a comparison as to whether the count value has exceeded "22". When the count value 68 exceeds this value, the output 56 input to the reset terminal of the SR flip-flop circuit 55 is set to H level, and the rate flag 22 is reset.

Incidentally, since noise exists in the reproduced signal 11, the rate flag 2
If 2 is set, an erroneous determination may be made.
If an error occurs in the rate flag 22, the frequency is not normally drawn in the PLL circuit. In order to prevent such a situation, it is conceivable to add a margin to noise in detecting the polarity inversion interval. In this method, for example, when a pulse of 2T or less is generated by a recording code limited to 3T or more, the rate flag 22 is reset for the first time.

Further, the configuration may be such that the rate flag 22 is set for the first time when the polarity inversion interval deviates by a predetermined number of times or more. Further, the edge detection signal (trigger signal) 48 of the rate comparison circuits 14 and 14A shown in FIG. 4 or FIG. 6 is not at the timing of the polarity inversion of the reproduction signal 11 but at the timing at which the reproduction signal 11 reaches a certain amplitude or more. It is also possible to configure it to generate. As a result, the rate flag 22 can be reduced without using a code string whose signal amplitude is small and erroneous determination due to noise is likely to occur.
Can be set.

As yet another configuration of the rate comparison circuit 14, an arrangement may be made to detect that the sum of a plurality of mark lengths is out of a certain range, or the rate comparison circuit 14 may be configured to record the sum of mark lengths at a certain interval on a disk. The arrangement may be such that a mark is used.

In the embodiment, the synchronization determination circuit 13 sets the synchronization flag 21 when the phase error is within a certain range. However, the present invention is not limited to this. For example, the synchronization flag 21 may be controlled using the result of data determination and demodulation. A circuit in which the fact that the phase error is within a certain range is used for synchronization detection has high responsiveness, but has a problem that erroneous determination of noise is likely to occur.

If an out-of-synchronization is detected during locking due to an erroneous determination of the synchronization detection, for example, the phase error signal 34 shown in FIG. Easy to be.

The method of controlling the synchronization flag 21 by utilizing the presence or absence of a demodulation error can ensure a relatively large noise tolerance and eliminate instability due to erroneous determination. Furthermore, it is also effective to use both a technique using a phase error and a technique using a demodulation error. In other words, by using a phase error at the time of pulling in a frequency that requires a high-speed determination for lock, once the demodulation has been performed normally, a synchronization determination is made based on the presence or absence of a demodulation error at that point, thereby achieving a stable And responsiveness can be compatible.

In the normal case, the phase comparator with polarity designation 32 operates when synchronization is not ensured.
Set the oscillation frequency of the extracted clock to 1
It is required to output a phase error signal 15 for approaching a bit rate of 1. The gain for this phase error need not necessarily be the same as that of the phase comparator 31. Further, the phase error extraction circuit 12 and the loop filter 1
6 may have another response characteristic with respect to the phase comparator 31 and the phase comparator with polarity designation 32, respectively.

FIG. 7 shows an example of a phase error extracting circuit in which the phase comparator and the phase comparator with designated polarity have different response characteristics. FIG.
The same reference numerals are given to the same parts as those of the phase error extraction circuit 12 shown in FIG. In the phase error extraction circuit 12A of this modification, the selector 35 of the previous embodiment does not exist, and instead, the first switch 71 for inputting the phase error signal 33 output from the phase comparator 31, A second switch 72 for inputting the phase error signal 34 output from the phase comparator 32 is provided. The synchronization flag 21 is input to the first switch 71 as it is, and is input to the second switch 72 after the logic is inverted by the inverter 73. As a result, the first switch 71 is closed when the synchronization flag 21 is on, and the second switch 72 is open in this state. When the synchronization flag 21 is not set, the second switch 72 is closed, and in this state, the first switch 72 is closed.
Switch 71 is opened.

The phase error signal 33 output when the first switch 71 is selected is output to the first loop filter 7.
5, the frequency characteristic is adjusted by the first characteristic, and becomes one input of the adder 77 as the phase error signal 76.
The phase error signal 34 output when the second switch 72 is selected is input to the second loop filter 78, the frequency characteristic is adjusted by the second characteristic, and the phase error signal This is the other input. Therefore, the signal 17A output from the adder 77 is a signal having different response characteristics to the phase comparator 31 and the phase comparator with polarity designation 32, respectively. That is, the adder 77
A signal 17A is created using the phase error signals 76 and 79 output from the two loop filters 77 and 78 added by the above, and the signal 17A is input to the voltage controlled oscillator 18 shown in FIG. 1 to control the frequency. Thus, it is possible to realize a clock extraction circuit capable of individually setting the response characteristics of the frequency pull-in and the phase pull-in.

If a limiter is added as a response characteristic of the phase comparator with polarity designation 32 so as to limit the pulse width of the output with respect to a certain or more phase error, an error may occur in the determination of the synchronization cancellation. Can also ensure stability. Dividing the output into a plurality of pulses in order to avoid sudden frequency fluctuations is also effective for improving the stability of the clock extraction circuit.

[0054]

As described above, claims 1 to 5 are provided.
According to the invention described above, a second phase comparator is provided in addition to the first phase comparator used for a normal PLL circuit, and a reproduced signal and an extracted clock are input to input a reproduced signal and a positive or negative polarity signal. Since one phase error is extracted, the frequency of the extracted clock can be made as close as possible to the bit rate of the reproduced signal even while the frequency synchronization is not established. That is, even in the case where the data rate of the reproduced signal greatly changes, normal pull-in can be expected without the need to externally change the free-run frequency. Further, according to these inventions, even when the data rate of the reproduction signal is not clear or has changed, the frequency of the extracted clock automatically approaches the data rate of the reproduction signal. In such a case, there is an advantage that the handling is easy and the response characteristic to a frequency change becomes good.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a circuit configuration of a clock extraction circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram specifically showing a part of a phase error extraction circuit of the clock extraction circuit of the present embodiment.

FIG. 3 is various waveform diagrams showing waveforms of respective parts of the phase comparator shown in FIG.

FIG. 4 is a block diagram specifically showing a part of a rate comparison circuit of the clock extraction circuit of the present embodiment.

5 is various waveform diagrams showing waveforms of respective parts of the rate comparison circuit shown in FIG.

FIG. 6 is a block diagram of a rate comparison circuit as a modification of the present invention.

FIG. 7 is a block diagram showing a phase error extraction circuit as another modified example of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional clock extraction circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Reproduction signal 12 Phase error extraction circuit 13 Synchronization judgment circuit 14 Rate comparison circuit 16 Loop filter 18 Voltage controlled oscillator (VCO) 19 Extracted clock 21 Synchronization flag 22 Rate flag 31 Phase comparator 32 Phase comparator with polarity designation 41 Binarization Circuit 42 Unit pulse generation circuit 44 Edge detection circuit 47 Difference circuit 50 Integrator 52 Judgment device 54 Timer 55 SR flip-flop circuit 61 3T pulse generation circuit 67 Comparator 71 First switch 72 Second switch

Claims (5)

(57) [Claims] 1. A reproduction signal obtained by reading a data sequence encoded and stored in a predetermined disk device and an extraction clock extracted from the reproduction signal are inputted to extract a phase error between the two. A second phase comparator for inputting the reproduction signal and the extracted clock to extract positive and negative phase errors, respectively; and outputs of the first and second phase comparators. A loop filter for adjusting the frequency characteristic of a signal output from the selection circuit, and a voltage control for inputting the signal passed through the loop filter and generating the extracted clock having a frequency corresponding to the input voltage. An oscillator compares the period of the extracted clock with the reproduction signal, and detects a state where the mark length limit specified in the reproduction signal is out of the range. A rate comparison circuit that determines whether the frequency of the playback clock is higher or lower than the frequency of the playback signal; a synchronization determination circuit that determines whether the extracted clock is synchronized with the playback signal; If the determination circuit determines that synchronization is achieved, the first phase comparator is selected. If the determination circuit determines that synchronization is not achieved, the rate comparison circuit in the second phase comparator is selected. And a selection circuit control means for selecting an output having a polarity corresponding to the output of the clock extraction circuit. 2. A reproduction signal obtained by reading a data sequence encoded and stored in a predetermined disk device and an extraction clock extracted from the reproduction signal are inputted to extract a phase error between the two. The phase of the extracted clock is compared with the frequency of the reproduced signal by comparing the period of the extracted clock with the reproduction signal and detecting a state where the mark length is out of the limit specified in the reproduction signal. A rate comparison circuit for determining whether the rate is high or low, and a phase signal for extracting the positive or negative phase error according to the comparison result by inputting the reproduction signal, the extracted clock, and the comparison result of the rate comparison circuit. 2, a selection circuit for selecting the outputs of the first and second phase comparators, and a loop filter for adjusting the frequency characteristic of the signal output from the selection circuit. A voltage-controlled oscillator that receives the signal that has passed through the loop filter and generates the extracted clock having a frequency corresponding to the input voltage; and determines whether the extracted clock is synchronized with the reproduced signal. A synchronization judging circuit that performs the synchronization. When the synchronization judging circuit judges that synchronization is achieved, the first phase comparator is selected, and when it is determined that synchronization is not achieved, the second phase comparator is selected. A clock extraction circuit comprising: a selection circuit control means for selecting a phase comparator. 3. A reproduction signal obtained by reading a data sequence encoded and stored in a predetermined disk device and an extraction clock extracted from the reproduction signal are inputted to extract a phase error between the two. The phase of the extracted clock is compared with the frequency of the reproduced signal by comparing the period of the extracted clock with the reproduction signal and detecting a state where the mark length is out of the limit specified in the reproduction signal. A rate comparison circuit for determining whether the rate is high or low, and a phase signal for extracting the positive or negative phase error according to the comparison result by inputting the reproduction signal, the extracted clock, and the comparison result of the rate comparison circuit. 2 phase comparators, a first loop filter for adjusting the frequency characteristics of the signal output from the first phase comparator, and a signal output from the second phase comparator. A second loop filter for adjusting the wave number characteristic; an adder for adding the outputs of the first and second loop filters; and a signal having a frequency corresponding to the input voltage, the signal added by the adder being input. A voltage-controlled oscillator that generates an extracted clock; a synchronization determination circuit that determines whether the extracted clock and the reproduction signal are synchronized; and a case where the synchronization determination circuit determines that synchronization is achieved. Makes the connection between the first phase comparator and the first loop filter, and if it is determined that the synchronization is not established, makes the connection between the second phase comparator and the second loop filter. A clock extraction circuit, comprising: a switch circuit. 4. The rate comparison circuit, when detecting that the extracted clock exceeds an upper limit of a mark length of the data series, sets a flag indicating that an oscillation frequency is high, and sets a lower limit of the mark length. 4. The clock extracting circuit according to claim 1, wherein the flag is lowered when it is detected that the current value is lower than the threshold value, and a hysteresis operation for maintaining the current state of the flag is performed in other cases. . 5. The rate comparison circuit according to claim 1, wherein the rate comparison circuit detects whether or not the data length falls outside the limit of the mark length based on a time interval at which the data sequence takes a predetermined constant amplitude value. The clock extraction circuit according to claim 1.