JP3434421B2 - Apparatus for reproducing digital information modulated and recorded with a discrete recording length - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data detection device for detecting reproduction data of a disk device or the like, and more specifically, a reproduction signal of an optical disk medium digitally recorded so that a linear recording density becomes substantially constant. The present invention relates to a phase locked loop that recovers a clock component that has

[0002]

2. Description of the Related Art In recent years, digitization of information has advanced, and it has permeated not only in information-related fields but also in audio-video fields. An optical disc is one of the media attracting attention as a medium for digitally recording such information as voice and image. Optical discs are generally superior to other magnetic tapes and magnetic discs in terms of random accessibility, medium exchangeability, and storability. Constant linear velocity (Const
ant Linear Velocity (CLV) recording method. The CLV recording method is a method that realizes the maximum recording capacity in the same disk size by making the bit recording density constant and maximal throughout the recordable area. In the data reproduction of the CLV recording method, it is usually necessary to change the disk rotation speed according to the radius of the reproduction area, that is, the track in order to keep the reproduction data rate constant. Usually, in order to convert the reproduced signal to digital data, a phase locked loop for the clock component of the reproduced signal is configured, and a frequency loop for motor control that pulls the clock frequency obtained here to a fixed frequency is provided. It is configured so that the reproduction data rate becomes a predetermined rate.

The phase lock loop used for converting a reproduced signal into digital data has a small sync pull-in range of usually 5% or less, and a high-precision rotation speed control according to the track radius is required to perform the sync pull-in. However, there is a problem in establishing synchronization pull-in because it is not easy. After digital modulation that satisfies the (d, k) rule used in the compact disc as an example of the reproduction signal (however, in the compact disc, d = 2, k = 1)
0), and NRZI (Non Return to Z)
ero, Inverse) modulation is performed and code "1"
Pit Width Modulation (Pit Width Modul)
data, the data is reproduced based on the rising and falling edges of the reproduction signal. The clock information of the reproduced data is reproduced using the phase locked loop by utilizing the fact that this edge is obtained at discrete time intervals determined by the (d, k) rule.

FIG. 1 shows a conventional data detecting device.
This will be described using 9. The data detection device is the optical disc 1
8 and a disk motor 19 for rotating the optical disk 18.
An optical pickup 20 for reproducing the information recorded on the optical disc 18, a binarizing means 1 for binarizing the reproduced signal at a predetermined voltage level and outputting a binary signal, and an output voltage for the low-pass filter means 4. An oscillating means 5 for outputting a clock having a proportional frequency, a phase comparing means 2 for comparing the phases of a binary signal and a clock and outputting a phase error signal, and a charge pump for discharging or sucking current according to the phase error signal. It comprises a means 3, a low-pass filter means 4 for converting the output current of the charge pump means 3 into a voltage and at the same time limiting the band and inputting it to the oscillating means 5, and a motor control means 21 for controlling the motor speed.

The operation of the data detecting apparatus configured as described above will be described below with reference to FIG. The reproduction signal (a) reproduced from the optical disk is binarized by the binarizing means 1 at a predetermined voltage level and converted into a binary signal (b). The oscillating means 5 has a characteristic of oscillating a clock having a frequency proportional to the input voltage, for example, as shown in FIG. 21, and oscillates at the free-running frequency (c) before the synchronization pull-in. The phase comparison means 2 compares the phase of the binary signal with the phase of the oscillation clock. As shown in FIG. 22, when the clock phase is advanced according to the phase relationship of the two inputs, the positive pulse (f) and the binary signal. When the phase is advanced, the negative pulse (g) is output with a time width corresponding to the phase error. The charge pump means 3 outputs positive and negative currents according to the phase error amount. The charge pump means 3 is composed of, for example, current sources I1 and I2 and switches S1 and S2 as shown in FIG. 23. By conducting S1 with a negative pulse, a predetermined current is discharged by the current source I1 and with S2 a positive pulse. A predetermined current is drawn by the current source I2 when the current is turned on. The low-pass filter means 4 is composed of, for example, a resistor R and a capacitance C as shown in FIG. 24, and converts the current output from the charge pump means 3 into a voltage and simultaneously limits the band. The oscillation means 5 oscillates with a clock having a frequency proportional to the voltage generated by the low-pass filter means 4. As described above, when the clock phase of the oscillating means 5 is advanced with respect to the binary signal, a positive pulse is output, current is sucked by the charge pump, and the filter voltage drops, so that the output clock frequency of the oscillating means 5 increases. It becomes low and works in the direction of delaying the clock in phase. On the contrary, when the clock phase of the oscillating means 5 is delayed with respect to the binary signal, a negative pulse is output and the charge pump discharges the current, and the filter voltage rises, so that the output clock frequency of the oscillating means 5 increases. It becomes higher and works in the direction of advancing the clock in phase. In this way, the negative feedback control works, the frequencies of both signals substantially match, and the positive and negative pulse widths finally become small, so that the phase synchronization pull-in of the binary signal (b) and the clock (d) is obtained. Done. Further, when performing CLV control and reproducing data at a fixed transfer rate, the rotation of the motor is controlled so that the oscillation frequency obtained by the oscillation means 5 of the phase locked loop becomes a fixed frequency.

[0006]

[Problems to be Solved by the Invention]
Since the edge information of the value signal is modulated according to the recording data, it does not appear uniformly, and the phenomenon that the phase locked loop is pseudo-locked outside the predetermined frequency occurs. In order to prevent the pseudo lock, it is necessary to adjust the number of rotations of the motor so that the reproduction signal rate becomes almost a predetermined rate.

The narrow lock-in range of this phase-locked loop is that the input data is pulse-modulated data and is temporally scattered information. Therefore, it is impossible to lock in frequency and rely only on phase lock-in. It is due.

As described above, attention must be paid to the lock-in of the phase-locked loop, and there is a problem in realizing a device that does not cause pseudo lock. Therefore, as shown in FIG. 25, the synchronous pull-in circuit requires the motor control means 21 for adjusting the rotation speed of the motor so that the reproduction signal rate is substantially within the synchronous pull-in range. For example, as shown in FIG. 26, the motor control means 21 utilizes that the rising and falling edges of the reproduction signal (a) are obtained at discrete time intervals determined by the (d, k) rule, and the shortest reproduction signal is obtained. A circuit was required to determine the pulse width or the longest pulse width and control the motor rotation so that this pulse width would be a predetermined value. When the pulse width is shorter than the predetermined width as in (h), the disk rotation is fast and the rotation speed is slowed. On the contrary, when it is long as in (i), the disk rotation is slow and the playback signal rate is increased by increasing the rotation speed. The motor speed was controlled so that it was within the phase lock pull-in range.

However, in the above-mentioned conventional configuration, since the response of the motor is slow, it takes time for the disk rotation to fall within the pull-in range of the synchronous circuit, and the ratio of the seek time is large.

Although it is possible to shorten the settling time until the motor rotates steadily, the motor torque and drive current are limited. Also, when controlling the motor rotation by detecting the shortest pulse width or the longest pulse width of the reproduction signal, it is necessary to secure the detection sampling period for a certain time or longer because there is a restriction on the frequency at which the shortest pulse width and the longest pulse width appear. However, it was difficult to increase the control band.

The present invention solves the above-mentioned conventional problems. The shortest or longest pulse width of the reproduced signal is obtained, and at the same time, the output period of the oscillating means 5 is obtained so that the frequency of the oscillating means 5 is phase-locked. It is an object of the present invention to provide a data detection device capable of shortening the time required for synchronization pull-in and significantly shortening the seek time by configuring a frequency loop in which feedback is performed so as to fall within a possible range.

[0012]

SUMMARY OF THE INVENTION The present invention is an apparatus for reproducing digital information which is modulated and recorded with a discrete recording length, and which outputs a binary signal by binarizing a reproduced signal at a predetermined level. The phase difference between the binary signal and the clock signal is obtained by comparing the binary signal and the clock signal with the quantifying means, the oscillating means that outputs a clock signal having a frequency proportional to the input signal. And a phase comparison means for outputting a first difference signal indicating the first difference signal and a first clock indicating either the reproduction period or the reproduction frequency by counting the time width of the specific pattern included in the binary signal with a fixed clock . Specific pattern width detection means for outputting information, and oscillation cycle detection means for outputting second information indicating either the oscillation cycle or the oscillation frequency by detecting the cycle of the clock signal, A cycle comparison means for outputting a second difference signal indicating a difference between the first information and the second information by comparing the first information and the second information, and The oscillating means includes: arithmetic means for performing arithmetic operation according to the first difference signal and the second difference signal; and filter means for band-limiting the output of the arithmetic means and outputting as an input signal of the oscillating means. The phase comparison means and the calculation
The clock signal is binary by the means and the filter means.
Phase synchronization that operates so as to be phase-synchronized with the signal transition edge
Phase loop, the oscillating means, and the specific pattern width detecting means
Stage, the oscillation cycle detection means, the cycle comparison means, and the performance
Clock by calculating means and the low-pass filter means
Frequency loop that operates so that the cycle is almost the same as the playback cycle.
It is characterized in that the above-mentioned purpose is achieved. The oscillation cycle detection means is
The clock signal output from the means is n (n is a natural number)
Characterized in that the number of cycles is counted by the fixed clock.
To do. The calculation means is configured to output the first difference signal and the first difference signal.
A second difference signal and receives the first difference signal and the first difference signal.
It is a voltage generating means for outputting a voltage in accordance with the difference signal of 2.
It is characterized by The calculation means is configured to generate the first difference signal.
And receiving the second difference signal, the first difference signal
And discharge of current according to the second difference signal
Is a charge pump means for sucking
And The oscillation cycle detecting means outputs a clock signal n
(N is a natural number) The fixed clock is divided by a period divided by k.
(K is a natural number) Counted with a divided clock
It is characterized by

With the above structure, the shortest or longest pulse width of the reproduced signal is obtained, and at the same time, the clock period of the oscillating means is obtained so that the frequency of the oscillating means falls within the range in which the phase synchronization can be pulled in. Clock recovery can be performed at high speed and with certainty by also having a phase synchronization pull-in operation.

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[0041]

[0042]

[0043]

[0044]

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The data detection device of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows a block diagram of a data detection device. The data detecting device comprises a binarizing means 1 for binarizing a reproduced signal at a predetermined voltage level and outputting a binary signal, an oscillating means 5 for outputting a clock having a frequency proportional to the output voltage of the low pass filter means 4, Phase comparison means 2 for comparing the phase of a binary signal and a clock and outputting a phase error signal, charge pump means 3 for discharging or sucking current according to the phase error signal, and charge pump means output current converted to voltage. At the same time, the low-pass filter means 4 for limiting the band and the specific pattern detecting means 6 for counting the length of a specific pattern, for example, the longest mark included in the binary signal with a fixed clock and outputting the counting result.
And an oscillation cycle detecting means 7 which counts the oscillation cycle of the oscillation means 5 with a fixed clock and outputs a counting result, and a count output value of the oscillation cycle detecting means 6 and a count output value of the specific pattern width detecting means 6. Then, it comprises a period comparing means 8 which outputs the period error signals of both.

Next, the operation of the first data detector will be described with reference to FIG. FIG. 2 shows a steady reproduction state. The reproduction signal is a signal obtained by reproducing the disc recorded by CLV by pit width modulation. The reproduced signal (a) is binarized at a predetermined level by the binarizing means 1 to become a binary signal (b). To reproduce data from a binary signal,
It is necessary to extract a clock component that is phase-synchronized with this, but due to the characteristics of digital modulation, the edge interval of a binary signal is an integral multiple of the clock cycle and takes a discrete value depending on the recording data, resulting in a spectrum of the binary signal. Since it is spread, it is difficult to detect the frequency component, and the binarization unit 1, the phase comparison unit 2, the charge pump unit 3, the low-pass filter unit 4,
The phase-locked loop composed of the oscillating means 5 cannot perform frequency-dependent pull-in, and only relies on the phase-locked pull-in. The principle of the phase lock pull-in is as described in the conventional example.

Therefore, in order for the binary signal and the clock to be phase-synchronized, the frequency of the clock component of the binary signal and the output clock frequency of the oscillating means 5 have an accuracy of about ± 5% before entering the phase synchronization pull-in. Must match. When the two are greatly different in frequency, they cannot be pulled in to the regular frequency and may be pulled in to the pseudo stable point, so normal synchronization pull-in cannot be expected.

For example, the maximum edge interval of a binary signal corresponds to 16 times the clock period (expressed as 16T, where T is 1).
Clock period), the maximum value of the edge interval of the binary signal is counted with a fixed clock every predetermined detection period in order to prevent the above-mentioned pseudo pull-in.
A specific pattern width detecting means 6 for obtaining cycle information of a clock component of a binary signal from this count value, and a cycle obtained by dividing the oscillation clock 16 of the oscillation means 5 by a fixed clock to obtain clock cycle information. The oscillation cycle detecting means 7 is provided, and the cycle comparing means 8 compares the 16T cycle of the binary signal with the 16-divided cycle of the oscillating means 5 based on these two counting results. The 16T cycle is 16 minutes. When it is larger than the cycle, that is, when the frequency of the oscillating means 5 is lower than the frequency of the clock component of the binary signal, the charge pump means 3 is operated so as to increase the frequency of the oscillating means 5, and vice versa. Further, when the 16-cycle period of the clock of the oscillation means 5 is smaller than the 16T cycle of the binary signal, that is, when the frequency is high, the frequency of the oscillation means 5 is lowered. By operating the pump means 3, constitute a frequency loop as draw in frequency the clock component oscillation clock oscillating means 5 has a binary signal.

FIG. 3 shows the operation of the frequency / phase locked loop. First, since the frequency of the clock component of the binary signal is far from the frequency of the oscillation means 5 (point A), the frequency loop is operated before the operation of the phase locked loop and the frequency and oscillation of the clock component of the binary signal. If the frequency deviation of the clock frequency of the means 5 is within the range of phase lock pull-in, that is, within about ± 5%, and the phase lock loop is operated from point B, normal pull-in is possible without pseudo pull-in. Is. (Point C) The accuracy of frequency acquisition depends on the frequency of the fixed clock, and the higher the frequency of the fixed clock, the higher the detection accuracy. Therefore, it is necessary to determine a fixed clock frequency according to the phase synchronization pull-in range. When a modulation rule in which the maximum edge interval of a binary signal is 16 times (16T) the clock cycle is used, the frequency of the fixed clock used for counting is doubled the oscillation clock frequency of the oscillation means 5 during steady rotation. If set, the detection accuracy is 1/32 = about 3.1%
Accuracy of ± 5% of the phase lock pull-in range
Can be fully met.

However, the detection cycle of the specific pattern detection means 6 must include the maximum edge interval of the binary signal at least once. For example, when the rotation of the disk changes to ½ of the normal rotation due to seeking during disk playback, the maximum edge interval appearance probability is 1/2.
Therefore, it is necessary to have a double detection cycle.

Further, by detecting the maximum value or the minimum value (the minimum value in the above embodiment) of a plurality of adjacent detection sections in the detection of the specific pattern width, the detection error due to the occurrence of a defect on the disk can be reduced. be able to.

The maximum edge interval of the binary signal is 16T.
However, other edge intervals, for example, a recording mark of 14T may be used, and (14T + 4T).
It is also possible to add adjacent edge intervals together in the form of the recording marks and count this interval.

As described above, according to the present embodiment, the phase locked loop and the frequency loop are provided, and the frequency of the clock component of the binary signal and the oscillation of the oscillating means 5 are generated by the frequency loop before the operation of the phase locked loop is started. Since the frequencies are almost the same, the phase-locking operation can be performed reliably without pseudo-phase-locking. Also, as in the conventional method, the rotation of the motor is adjusted and then the phase-locked loop is operated and pulled in. Unlike the above, since the reproduction data rate and the oscillating frequency of the oscillating means 5 are brought close to each other by the frequency loop before the motor enters the steady rotation, the phase synchronization pull-in can be greatly shortened.

Here, both the specific pattern width detecting means 6 and the oscillation cycle detecting means 7 detect the cycle by counting with a fixed clock, but the output clock of the oscillating means 5 is used as the counting clock of the specific pattern width detecting means 6. Even if is used, the relative size of the specific pattern width and the oscillation clock period can be known, and the same operation can be performed. However, in this case, the detection cycle depends on the existence probability of the specific pattern, and in general, the probability of appearance of the specific pattern is low, so the detection cycle becomes long, which limits the control band, and the advantage diminishes. . Since the specific pattern width detection detects a binary signal, that is, a signal obtained from the disc reproduction signal, the variation in the detection value of the specific pattern width is similar to the response of the disc motor and is about several tens Hz, and the sampling frequency for detection is Anything is acceptable. For example, if the appearance frequency of the specific pattern is 1 kHz, it is not a problem because the response speed of the motor is sufficiently high. The response band of the oscillating means 5 is usually set to about several tens KHz, although it depends on the design of the synchronous loop, and thus the fluctuation of the detected value of the oscillation clock cycle is similar to this, and the sampling frequency of detection is at least according to the sampling theorem. At least twice the response band is required.

If the output clock of the oscillating means 5 is used as the counting clock of the specific pattern width detecting means 6 and the relative magnitude relationship between the specific pattern width and the oscillating clock cycle is known, the cycle of the oscillating means 5 will be determined. Since the detection cycle is substantially the same as the detection cycle of the specific pattern detection, it is unreasonable to control the oscillating means 5 based on this detection result.

If the method of measuring the oscillation clock period of the oscillation means 5 with a fixed clock as shown in FIG. 1 is used, the 16-division cycle of the oscillation means 5 (for example, the predetermined data rate is 25 MHz and the maximum edge interval of the binary signal is the clock). If a modulation rule that is 16 times the period is used, the oscillation period can be detected at 640 ns), and a sufficient sampling frequency for the response of the oscillation means 5 can be realized. Based on this detection result, the oscillation means 5 can be controlled sufficiently, and by constructing the frequency loop as described in the first embodiment, it is possible to achieve both the pull-in time reduction and the control stability. .

Further, since the low-pass filters of the phase locked loop and the frequency loop are shared, the shock at the time of switching is absorbed here, and smooth loop switching can be realized.

In the first embodiment, the charge pump means is composed of one charge pump. However, as shown in FIG. 4, the first charge pump for the phase locked loop and the second charge pump for the frequency loop are used. May be provided independently. As a result, the gain settings of the phase locked loop and the frequency loop can be set independently, and the degree of freedom in loop design can be expanded.

Further, the frequency loop and the phase locked loop are stopped by prohibiting the current output of the charge pump. As shown in FIG. 5, the loop control means 9 for switching the loop operation outputs the first signal. Each loop may be controlled by the first hold signal for inhibiting the output of the first charge pump and the second hold signal for inhibiting the output of the second charge pump.

Further, in the specific pattern width detecting means 6, the clock output from the oscillating means 5 and the fixed clock for counting may be divided and then detected as shown in FIG. As a result, the operating frequency of the counting circuit can be suppressed to a low level, and the detection accuracy can be increased by increasing the frequency division ratio of the oscillation means 5 as compared with the frequency division ratio of the fixed clock.

Further, as shown in FIG. 7, the loop control means 9 determines the first hold signal and the second hold signal for inhibiting the outputs of the first charge pump and the second charge pump based on the cyclic error signal. Something may occur. When the cycle error is large, the operation of the phase-locked loop is stopped by the first hold signal and only the frequency loop is operated so that the cycle of the clock component of the binary signal and the clock cycle of the oscillating means 5 become asymptotic, and the cycle error is reduced. If it is within the phase lock pull-in range, the first hold signal is released and the phase lock loop is operated, and when the phase lock loop pulls in,
For example, when the cycle error becomes zero, the second hold signal inhibits the second charge pump output to stop the operation of the frequency loop, so that the reliable pull-in operation can be performed. The frequency loop may be instantaneously switched to the phase locked loop, but more reliable and smooth switching is possible by creating a state in which both are operating at the time of switching.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. A block diagram of the data detection device is shown in FIG. In FIG. 8, the data detection device includes a binarizing means 1 for binarizing a reproduction signal at a predetermined voltage level and outputting a binary signal, and a low pass filter means 4.
Oscillator 5 for outputting a clock having a frequency proportional to the output voltage of V, phase comparator 2 for comparing the phase of a binary signal and a clock and outputting a phase error signal, and discharging or sucking current according to the phase error signal. And a low-pass filter means 4 for converting the output current of the charge pump means into a voltage and simultaneously limiting the band.
And a specific pattern included in the binary signal, for example, the length of the longest mark is counted with a fixed clock and a counting result is output, and the oscillation cycle of the oscillator 5 is counted with a fixed clock and counted. The oscillation cycle detecting means 7 for outputting the result and the cycle comparing means 8 for comparing the count output values of the count output values of the specific pattern width detecting means 6 and the oscillation cycle detecting means 7 and outputting the cycle error signals of both of them have been described above. The configuration is the same as that of 1. Here, further, the synchronizing means 10 for synchronizing the binary signal with the output clock of the oscillating means 5 to generate the reproduced data synchronized with the clock, and the output clock of the oscillating means 5 and the reproduced data are input to the reproduced data. It is configured by adding pattern detecting means 11 for detecting the locked state of the phase locked loop by detecting the fixed pattern included therein.

The pattern detection means 11 is, for example, a synchronization mark for synchronizing the entire data recorded in the reproduction data at regular intervals, and detects the presence of a fixed pattern and the periodicity. This is performed by reading the reproduced data output from the converting means 10 with the clock of the oscillating means 5.

The cycle of the clock component of the binary signal,
The fixed pattern is not detected when the cycle of the output clock of the oscillating means 5 is different, but the fixed pattern is detected when the cycle becomes asymptotically, and the detected cycle of the fixed pattern in the phase locked state is the output clock cycle of the oscillating means 5. When counted, it becomes a predetermined count value. However, when the phase is not locked, the cycle, that is, the cycle in which the fixed pattern is detected does not reach the predetermined count cycle due to a slight deviation in frequency. Therefore, if the fixed pattern is detected and the period in which the fixed pattern is detected is a predetermined period, it can be determined that the phase synchronization state is established.

The operation of the data detection device of FIG. 8 will be described. The basic synchronization pull-in method is the same as in the first embodiment. When the cycle error is large, the operation of the phase locked loop is stopped and only the frequency loop is operated to operate the cycle of the clock component of the binary signal and the oscillation means 5.
The clock cycle of the asymptotic clock, and if the cycle error falls within the phase lock pull-in range, the phase lock loop is further operated, and when the pattern detection device 11 confirms the lock of the phase lock loop, the second hold signal Disables the charge pump output of and stops the frequency loop operation. FIG. 7 shows the operation sequence of the frequency loop and the phase locked loop in the second embodiment.

In this way, the reliability can be improved by performing the switching from (frequency loop + phase locked loop) to (phase locked loop) with high accuracy using the pattern detection means 11.

In the second embodiment, switching from (frequency loop) to (frequency loop + phase locked loop) is judged by looking at the period error, but it can be replaced with a tracking on signal of the disk drive or the like. Is. Also, switching from (frequency loop + phase-locked loop) to (phase-locked loop) is performed by confirming the synchronization pull-in by pattern detection. For example, this is the default value when the absolute value of the phase error signal is integrated. Any other method may be used as long as it is a means for confirming the synchronization state of the phase locked loop, such as determining that it is in the synchronization state if it is below the level.

Further, in FIG. 9, the sequence ends when the operation is switched to only the phase-locked loop, but a large phase error signal is generated when a signal is missing due to a defect on the disk, and the phase-locked loop is generated. It may come off. When the frequency is largely deviated, it cannot be recovered only by the phase locked loop, so when the pattern cannot be detected, the frequency / phase locked loop is once operated as shown in the operation sequence diagram of FIG. Alternatively, as shown in the operation sequence diagram of FIG. 9, the operation of the phase locked loop may be temporarily stopped and only the frequency loop may be operated. As a result, the ability to recover from disturbance can be improved.

The charge pump means of the first and second embodiments draws in a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle as shown in FIG. Alternatively, the discharge may be performed for a predetermined time.

The charge pump means of the first and second embodiments outputs a current proportional to the cycle error signal output from the cycle comparison means for a predetermined time every predetermined cycle as shown in FIG. It can be one.

The charge pump means of the first and second embodiments draws in a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle as shown in FIG. Alternatively, the discharging may be performed by controlling the time width in proportion to the absolute value of the cyclic error signal.

The phase comparison means 2 delays the binary signal in proportion to the output of the oscillation cycle detection means and the cycle detector 12 which outputs a signal proportional to the oscillation cycle of the oscillation means as shown in FIG. For comparing the phase difference between the output of the delay unit 13 and the output of the pulse gate circuit and the pulse gate circuit 14 for outputting the clock edge information of the oscillation output only when there is a binary signal input. And a phase difference detector 15 for generating two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference.
A signal obtained by allowing the pulse gate circuit 14 to output the clock of the oscillating means 5 only when there is an edge input of the value signal and delaying the binary signal by, for example, a half cycle of the oscillation clock by the delay device 13, The phase difference detector 15 compares the phases of the oscillation clocks. The delay amount of the delay device 13 is controlled in proportion to the oscillation cycle of the oscillating means so that the detection window of the phase difference detector 15 is maximized. By doing so, the detection offset and detection of the phase difference detector 15 are performed. Since the dead zone can be eliminated, the phase synchronization range can be maximized.

The delay amount of the delay device 13 may be controlled in proportion to the oscillation cycle of the oscillation means 5 as shown in FIG. 16 and can be held by an external signal. It is possible to prevent the phase error signal from being disturbed by holding the delay amount of the delay device 13 by a detection signal such as a defect on the disk. Further, the delay amount of the delay device 13 may be controlled in proportion to the oscillation cycle of the oscillating means 5 as shown in FIG. 16, and can be switched to a predetermined delay amount by an external signal. The phase error signal can be prevented from being disturbed by setting the delay amount of the delay device 13 to a predetermined value by a detection signal such as a defect on the disk.

Further, the delay amount of the delay unit 13 may be controlled in proportion to the current or voltage proportional to the oscillation period of the oscillating means 5 which is reduced and filtered by the filter means 16 as shown in FIG. By performing low-pass filtering, it is possible to prevent the delay amount from changing unnecessarily with respect to disturbance.

The phase comparison means 8 is proportional to the digital-analog converter 17 for outputting a current or voltage proportional to the count value of the specific pattern width detector as shown in FIG. 18, and the output of the digital-analog converter 17. And a pulse gate circuit 14 for permitting the output of the clock of the oscillating means 5 only when there is an edge input of a binary signal, and only when there is an edge input of a binary signal. Oscillating means output: pulse gate means for outputting clock edge information, delay device 13 output, and pulse gate circuit 1
The phase difference detector 15 is configured to compare the four phase differences of the four outputs and generate two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference. Delay device 1
The delay amount of 3 is controlled in proportion to the count value of the specific pattern width detector so that the detection window of the phase difference detector 15 spreads to the maximum, and by doing so, the detection offset of the phase difference detector 15, Since the detection dead zone can be eliminated, the phase synchronization range can be maximized.

Further, the phase comparison means 8 may have a configuration other than the above as long as it can realize the phase comparison operation.

In the first and second embodiments, the CLV-recorded disc has been described, but any other recording method, such as a recording system, can be used as long as the reproduction linear velocity information of the disc can be obtained from the recorded data. It may be CAV recording.

The charge pump means of the first and second embodiments has been described as a current drive type charge pump which outputs a current in response to a phase error signal. A voltage drive type configuration that outputs a voltage may be used.

Further, in the first embodiment, the binarizing means for binarizing the reproduction signal of the optical disk is used, but waveform equalization for reducing the intersymbol interference of the reproduction signal and improving the signal-to-noise ratio is performed. Needless to say, it may be binarized after being played.

[0082]

As described above, according to the present invention, the oscillation period of the oscillating means and the time width of the specific pattern included in the binary signal are detected even when the phase lock loop is out of the lock-in range. The frequency loop is constructed by performing feedback control of the above, and an effective effect that the pulling operation can be performed at high speed, reliably and smoothly is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a data detection device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the data detection device according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of a frequency / phase locked loop.

FIG. 4 is a block diagram of charge pump means independent of a frequency loop and a phase loop.

FIG. 5 is a block diagram of charge pump means capable of switching loop operations.

FIG. 6 is a block diagram of specific pattern detection means.

FIG. 7 is a diagram showing input / output signals of a loop control means.

FIG. 8 is a block diagram of a data detection device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an operation sequence of a frequency / phase locked loop.

FIG. 10 is a diagram showing an example of an operation sequence when a disturbance occurs.

FIG. 11 is a diagram showing an example of an operation sequence when a disturbance occurs.

FIG. 12 is a diagram showing an output signal during operation of the charge pump means.

FIG. 13 is a diagram showing an output signal during operation of the charge pump means.

FIG. 14 is a diagram showing an output signal during operation of the charge pump means.

FIG. 15 is a block diagram of phase comparison means.

FIG. 16 is a diagram showing input / output signals of a delay device.

FIG. 17 is a block diagram connecting a delay device and an oscillating means.

FIG. 18 is a block diagram of phase comparison means.

FIG. 19 is a block diagram of a conventional data detection device.

FIG. 20 is a diagram for explaining the operation of the conventional data detection device.

FIG. 21 is a characteristic diagram showing an example of input voltage versus output frequency characteristics of the oscillating means.

FIG. 22 is a diagram for explaining the operation of the phase comparison means.

FIG. 23 is a circuit diagram of charge pump means.

FIG. 24 is a circuit diagram of low-pass filter means.

FIG. 25 is a diagram showing a motor control process until phase synchronization.

FIG. 26 is a diagram for explaining the motor control operation.

[Explanation of symbols]

1 2 value conversion means 2 Phase comparison means 3 Charge pump means 4 Low-pass filter means 5 oscillation means 6 Specific pattern width detection means 7 Oscillation cycle detection means 8 period comparison means 9 Loop control means 10 synchronization means 11 Pattern detection device 12 Cycle detection means 13 Delay device 14 pulse gate circuit 15 Phase difference detector 16 low pass filter 17 Digital-analog converter 18 optical disc 19 disk motor 20 Optical pickup 21 Motor control means

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyuki Miyaji 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-3-230619 (JP, A) JP-A-6- 338790 (JP, A) JP 5-250818 (JP, A) JP 4-192810 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/14 351 H03L 7/08

Claims (5)

(57) [Claims] 1. An apparatus for reproducing digital information modulated and recorded with a discrete recording length, which comprises a binarizing means for binarizing a reproduced signal at a predetermined level and outputting a binary signal, and an input signal. By comparing the binary signal and the clock signal with an oscillating unit that outputs a clock signal of a proportional frequency, a first difference signal indicating a phase difference between the binary signal and the clock signal is generated. The phase comparison means for outputting and the fixed time width of the specific pattern included in the binary signal are fixed.
A specific pattern width detection unit that outputs the first information indicating either the reproduction cycle or the reproduction frequency by counting with the lock ; and the oscillation cycle or the oscillation frequency by detecting the cycle of the clock signal. By comparing the first information and the second information with the oscillation period detecting means that outputs the second information indicating one of the two, the information between the first information and the second information is compared. A cycle comparison unit that outputs a second difference signal indicating a difference, a calculation unit that performs a calculation according to the first difference signal and the second difference signal, and the oscillation by limiting the band of the output of the calculation unit. Filter means for outputting as an input signal of the means, and the clock signal is phase-synchronized with the changing point edge of the binary signal by the oscillating means, the phase comparing means, the calculating means and the filter means. The clock cycle becomes substantially the same as the reproduction cycle by the phase-locked loop that operates as described above, the oscillating means, the specific pattern width detecting means, the oscillation cycle detecting means, the cycle comparing means, the calculating means, and the low-pass filter means. An apparatus , characterized in that it shares a frequency loop which operates in the same manner. 2. The oscillation cycle detecting means counts a cycle, which is obtained by dividing a clock signal output from the oscillation means by n (n is a natural number), with the fixed clock. Equipment . 3. The calculating means is a voltage generating means for receiving the first difference signal and the second difference signal and outputting a voltage in accordance with the first difference signal and the second difference signal. An apparatus according to claim 1, characterized in that 4. The charge pump means for receiving the first difference signal and the second difference signal and discharging or sucking a current according to the first difference signal and the second difference signal. The device of claim 1 wherein: 5. The oscillation period detecting means counts a period obtained by dividing a clock signal by n (n is a natural number) by a clock obtained by dividing the fixed clock by k (k is a natural number). The device according to claim 2 .