JP3505923B2 - Information processing device and information recording device - Google Patents

Description

Detailed Description of the Invention

The present invention relates to automatic adjustment of an analog signal processing process, and more particularly to automatic adjustment of a processing process of a signal in which digital information is input as an analog waveform.

[0002]

2. Description of the Related Art The conventional information storage device is classified into several types and the relationship with a booster of a reproducing circuit will be described. First, considering a magnetic storage device, a floppy disk drive (hereinafter referred to as FDD) does not need a booster in the first place because the information recording density is not so high. On the other hand, a hard disk drive (hereinafter referred to as HDD) has a higher information recording density than FDD and requires a booster, but since the system is closed as a storage device, the boost level is optimal for each HDD. There was no problem if I fixed the value.

Further considering the optical storage device,
In a storage device of the type that detects the contrast of reflected light, such as Compact Disc (hereinafter referred to as CD) and phase change recording, it is not necessary to add a booster because the S / N is high, or even if it is, a boost level A fixed value was sufficient.

On the other hand, a magneto-optical recording type storage device has a booster indispensable because the S / N is not as high as that of the above-mentioned optical storage device.
In most cases, a recording method called itPosition Modulation recording (hereinafter referred to as PPM recording) is used.

This PPM recording is a recording method in which "1" of the recording information 100 is associated with the center position of the recording pit 101 as shown in FIG. 16, and the peak position of the read analog signal is detected during reproduction. Good. The detection principle is
While obtaining the zero-cross point of the differential waveform 104 of the reproduction signal, the original reproduction signal is compared at a certain level to obtain a gate signal, and the peak detection signal 106 is obtained from the gate signal and the zero-cross signal 105. When this method is used, even if the reproduction signal 102 shown by the solid line in FIG. 16 has a small modulation degree, the reproduction signal 1 shown by the dotted line is generated.
Even if the amplitude is increased by the booster as in 03, the peak detection signal 106 can be obtained without any problem. Because the difference in boost level at this time is only related to the magnitude of the pulse width of the gate signal, even if the level slightly fluctuates, it does not affect the peak position indicated by the peak detection signal 106. Because.

As described above, the information storage device of this type conventionally does not require a booster or, even if there is a booster, does not require automatic adjustment of the boost level.

On the other hand, a filter is inserted to remove high frequency noise of the reproduced signal, but S /
When N is sufficiently secured, it is not necessary to switch the cutoff frequency in the first place. Alternatively, even if the S / N cannot be sufficiently secured, the linear velocity is constant (hereinafter CL
The frequency of the reproduced signal is constant in the case of performing the V.) reproduction or the constant angular velocity (hereinafter referred to as CAV) reproduction, and even in the CAV reproduction of the zone format, the recording density of each zone is known in advance. Then, it is easy to switch the cutoff frequency of the filter.

Therefore, it is not necessary to switch the cutoff of the filter, or even automatic adjustment thereof is not necessary.

[0009]

However, the above-mentioned conventional technique has the following problems. First,
In a magneto-optical recording type storage device, it has become necessary to increase the linear recording density as the storage capacity increases. For this reason, the Pit Width Modulator different from the conventional technology is used.
Ion recording (hereinafter referred to as PWM recording) has begun to be adopted. Since this PWM recording is a recording method in which "1" of the recording information 100 is made to correspond to both edges of the recording pit 107 as shown in FIG. 17, a detection circuit different from the PPM recording is necessary. A method of comparing the reproduced signal at a certain level near the amplitude center to detect both edges of the pit, a method of detecting both edges of the pit by a zero-cross point of a signal obtained by second-order differentiation of the reproduced signal, and the like are considered. When these detection methods are used, in both cases, the fluctuation of the boost level appears as it is as the time fluctuation of both edge positions of the pit, so when the boost level deviates from the optimum value, the edge detection signal shifts. As a result, problems such as lack of stability of the reproduction system phase locked loop (hereinafter referred to as PLL) and deterioration of the error rate occur. In particular, in the above-mentioned detection method of the comparator system, the position shift of the edge detection signal becomes remarkable with respect to the fluctuation of the boost level,
It has a great impact on the regeneration system. In the example shown in FIG. 17,
Since the reproduced signal 109 has an appropriate boost level, the correct edge detection signal is obtained.
Since the boost level is small, the edge position has shifted. As described above, in the PWM recording, there is a problem that the fluctuation of the boost level immediately affects the data detection system.

In recent years, large-capacity and removable recording media have been introduced even in magnetic storage devices, but it is difficult to ensure compatibility of recording media having different recording densities with the prior art. This is because when the head type, gap length, flying height, etc. differ, the frequency characteristics of the reproduced signal obtained at the head output also differ, so different recordings are performed with a magnetic storage device optimized for a certain recording density. This is because when reproducing a recording medium having a high density, there will be optimum values with different boost levels. This corresponds to the need for reducing the light spot diameter of the optical storage device as the recording density increases. Therefore, in the conventional storage device, if a recording medium with a high recording density is released in the future, there is a problem that it cannot cope with it.

Further, considering the cutoff frequency of the filter, a problem still arises when reproducing recording media having different recording densities. This is because the maximum frequency of the signal obtained at the time of reproduction changes because the modulation code used differs depending on the recording density or the linear recording density itself changes. In particular,
When a high-density recording medium is reproduced by an information storage device compatible with a low recording density, the reproduction signal amplitude of the high-density recorded portion becomes small, and the error rate deteriorates, or finally the detection of data fails. The problem arises that it will be possible.

Recently, C based on CLV reproduction is used.
Even with a recording medium such as a D-ROM, there is a demand for variable-speed reproduction in order to increase the transfer rate, and it is implemented. However, even in such a case, the maximum frequency of the reproduction signal changes, so the above is also the case. You run into problems similar to those mentioned. This problem is due to the relatively low recording density of CDs,
Although it is possible to suppress the effect to a small level when reproducing a recording medium with a sufficient S / N ratio,
When reproducing a recording medium having a high recording density such as Versatile Disc (hereinafter referred to as DVD), it has a great influence.

The present invention is intended to solve the above problems, and automatically corrects the boost level and the cutoff frequency of an information storage device to improve the reliability of the device.
Its main purpose is to ensure compatibility of recording media in the future.

[0014]

Means for Solving the Problems The constitution of the present invention for solving the above problems is as follows: 1) A booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform. In the information storage device, the booster of the booster is provided based on an output signal of the amplitude detection means, which includes both an amplitude detection means for detecting the amplitude of the boosted analog waveform and a sample timing signal generation means for giving a timing of amplitude detection. It is characterized in that the level is automatically adjusted.

2) In the information storage device, the boost level is controlled by sampling and comparing the amplitude of the random recording pattern with the repeating pattern of the highest frequency arranged in the format of the recording medium. Is characterized by.

3) An information storage device having a booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform, is provided with a boost level abnormality detecting means and detects an abnormality. The configuration is such that the boost level setting is changed only when the boost level is changed.

4) The information storage device is characterized in that the boost level is judged to be abnormal when the phase synchronizing circuit of the data synchronizer is asynchronous.

5) In the information storage device, the boost level is judged to be abnormal when the number of error corrections exceeds a predetermined fixed level, or when an error correction impossible flag is set. Characterize.

6) An information storage device provided with a filter for reading a modulated signal digitally recorded on a recording medium as an analog waveform and removing high frequency noise of the analog waveform, comprising a frequency detecting means of a reproduced signal, and the frequency detecting means. The cutoff frequency of the filter is automatically adjusted based on the output signal of the means.

7) The information storage device is characterized in that the frequency detecting means is constituted by a filter having a known frequency characteristic and an amplitude detecting means for detecting the output signal amplitude of the filter.

8) The information storage device is characterized in that the frequency is detected by using the oscillation frequency of the voltage controlled oscillator in the phase synchronization circuit of the data synchronizer.

9) A unique recording pattern that does not appear in the user information recording area in an information storage device equipped with a filter for reading a modulated signal digitally recorded on a recording medium as an analog waveform and removing high frequency noise of the analog waveform. And a pattern detecting means for detecting, and is configured to automatically adjust the cutoff frequency of the filter according to the time interval of the detection signal obtained by the pattern detecting means or the number of detection signals detected in a unit time. And

10) In an information processing apparatus equipped with a booster for amplifying a specific frequency of the analog waveform by inputting digital information as an analog waveform and a filter for removing high frequency noise of the output of the booster, the analog after boosting The amplitude detection means for detecting the amplitude of the waveform, the sample timing signal generation means for giving the timing of the amplitude detection, and the frequency detection means for the reproduced signal, which is regarded as the equivalent signal to the digital data detected from the analog waveform, are combined. The boost level of the booster is automatically adjusted based on the detection result of the detection means, and the cutoff frequency of the filter is automatically adjusted based on the detection result of the frequency detection means. 11) In an information storage device including a booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform, and a filter for removing high frequency noise of the output of the booster, after boosting Of amplitude detecting means for detecting the amplitude of the analog waveform, sample timing signal generating means for giving the timing of amplitude detection, and frequency detecting means for the reproduction signal which is regarded as an equivalent signal to the record data detected from the analog waveform. The boost level of the booster is automatically adjusted based on the output detection result of the amplitude detection means, and the cutoff frequency of the filter is automatically adjusted based on the detection result of the frequency detection means.

12) In an information storage device comprising a booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform, and a filter for removing high frequency noise of the output of the booster. , An amplitude detecting means for detecting the amplitude of the analog waveform after boosting, a sample timing signal generating means for giving a timing of the amplitude detection, and a peculiarity which does not appear in a user information recording area physically arranged on the recording medium. A detection pattern of a unique recording pattern obtained by the pattern detecting means, which automatically adjusts the boost level of the booster based on the detection result of the amplitude detecting means. Depending on the number of unique recording patterns detected in a cycle or unit time Characterized in that it automatically adjusts the cutoff frequency of the filter Te.

[0025]

DETAILED DESCRIPTION OF THE INVENTION

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a reproducing circuit when the present invention is applied to a magnetic storage device, and FIG. 2 is an explanatory diagram of reproduced waveforms. First, the relationship between the recording information and the reproducing head output will be described. FIG. 2 shows an example of head output when a magnetic coil type head is used as a reproducing head and head output when a magnetoresistive type head is used. At this time, since the recording state 25 corresponding to the recording information 24 is obtained as the differential output from the magnetic coil type head output 26, the reproducing circuit detects the peak position of this head output.
In the following, the case where this magnetic coil type head is used will be assumed and the discussion will proceed.

The preamplifier 1 in FIG. 1 amplifies the head output as it is, and outputs it as a Variable Gain Am.
to the printer (hereinafter referred to as VGA). VGA
2, the head type, gap length, or flying height,
There is a role of standardizing the head output, which fluctuates due to various factors such as the linear velocity, to a constant level and sending it to the subsequent stage, and for this reason there is a feedback loop. In the feedback loop, the output of the amplifier 6 at the final stage is passed through the full-wave rectifier 10, the peak level and the target reference level are compared by the comparator 12, and the current is charged / discharged in a capacitor (not shown) to the VGA 2. It is a voltage feedback. However, this is a function of keeping the amplitude of the entire reproduced signal at a constant level, and does not correct the level of a specific frequency of the reproduced signal. The next stage booster 3 realizes this.

The signal output from the VGA 2 is input to the booster 3 and the amplitude of a high frequency signal having a small amplitude in the reproduced signal is
Raise the level to almost the same level as other signal levels. At this time, the boost level is determined by the boost control voltage 22 given from the outside. In this embodiment, as a means for automatically controlling the boost control voltage 22, an amplitude detecting means 17 surrounded by a dotted line in FIG. 1 is used.
And an example using the sample timing signal generation means 11, the A / D converter 14, the CPU 15, and the D / A converter 16.

Specifically, it is as described below. First, let's assume that booster 3 has not been boosted at all. The state of the waveform at this time is shown in FIG.
The raw signal that is not boosted passes through the booster 3 and the filter 4 and reaches the final stage amplifier 6. When high density recording is performed, the amplifier output 18 obtained by the amplifier 6 at the final stage
Has a small amplitude in the closest recording area 31. Next, this signal is full-wave rectified by the full-wave rectifier 10 to obtain the full-wave rectified waveform 19 shown in FIG. On the other hand, the sample timing signal generating means 11 outputs the sample timing signal 20 in order to sample the peak level 28 of the full-wave rectified waveform 19 in the closest recording area 31 and the random recording area 32, respectively. The sample timing signal 20 is a signal as shown in FIG. 3 that performs sampling in at least two locations of a SYNC area (generally, the closest recording repeating pattern) written for locking the PLL and a user data recording area. Should be output.
Alternatively, when the same pattern as the closest recording area 31 may be written in the user data recording area in advance, the sample timing signal 20 for sampling in the ID area indicating the ID of the sector is output instead of the user data recording area. You may. In any case, it is an indispensable area for organizing the recorded information in the information storage device,
It is easy to open the gate at these timings.
Further, a reset signal 29 as shown in FIG. 3 is inserted between each sample timing of the sample timing signal 20 so that the peak level 28 can be surely captured at each timing. All of these processes are performed by the amplitude detecting means 17 in FIG. 1, and the sampling signal 21 indicating each amplitude value is then sent to the A / D converter 14,
/ D converted. In the CPU 15, the A / D converter 14
The digitized data is stored in a RAM (not shown) or the like, and the boost level is determined by comparing the amplitude values of the closest recording area 31 and the random recording area 32. The determined boost level is fed back to the booster 3 as the boost control voltage 22 through the D / A converter 16. As a result, the amplitude of the close-packed recording area 31 having a small amplitude is increased, and the same amplitude as that of other areas having a low recording density can be obtained. Further, as shown in FIG. 3, the amplitude also increases in the closest recording portion of the random recording area 32, so that the correction waveform 30 having the same amplitude can be obtained over the entire recorded area.

On the other hand, when the boost level is too large and the amplitude of the densest recording area is larger than that of the other areas, sampling is performed with exactly the same operation and timing as in the case described above, and the obtained amplitude value is used. In comparison, the CPU 15 may perform control in the opposite direction to the above. According to this structure, the difference is automatically corrected regardless of whether the amplitude of the densest recording area is smaller or larger than that of the other area, and a correction waveform having the same amplitude is obtained in any recording pattern. . At this time, the amplitude value of the close-packed recording portion to be targeted by the correction waveform may be the same as the amplitude value of the other area where the recording density is low as described above, for example, 90% thereof.
May be determined so that These controls are CPU15
Since it is performed by the calculation of, the setting can be freely determined. Further, the control described above can be executed as long as the SYNC area and the random recording area are included. Therefore, if it is repeatedly executed using a resynchronization pattern after a sector or a servo area, more accurate automatic adjustment can be performed. .

The correction waveform 30 thus obtained is
First, in order to detect the peak position, it is differentiated by the differentiator 5, and the zero-cross comparator 7 detects the zero-cross point of the differentiated waveform. On the other hand, the correction waveform 30
Goes through the final stage amplifier 6 and the hysteresis comparator 8
, A gate signal that opens the gate only when the amplitude exceeds a certain level. At this time, if the amplifier output is a signal having an amplitude different depending on the recording density, the gate will not open or the gate opening period will be too long. However, if the amplifier output obtained here has the correction waveform 30 by the control described so far, there is no concern. By using the zero-cross signal and the gate signal thus obtained, the DATA Qualifier Log is
The peak detection signal 23 from which noise has been removed at ic9 is obtained.

As described above, according to the present embodiment, when the gap length of the head of a removable magnetic storage device is changed due to, for example, high density, the frequency characteristic of the reproduced signal obtained also changes at the same time. On the other hand, since it is automatically corrected and a reproduction signal amplitude of a constant level is always obtained regardless of the recording density, the compatibility of the devices can be maintained. Moreover, since the boost level is automatically controlled, the reliability of the device is improved.

Although a reproducing head in which recorded information is obtained as a differential output has been described here as an example, when a magnetoresistive head is used as the reproducing head, the magnetoresistive head output 27 shown in FIG. A waveform in which the recorded information corresponds to the edge position is obtained. In this case, a reproducing circuit for detecting the edge position instead of the peak position is required. However, the present invention can be applied to this case as well, and the reproducing circuit can perform information recorded in the optical storage device by PWM recording. Since it is the same as the reproducing circuit of FIG.

(Embodiment 2) Another embodiment of the present invention will be described with reference to the drawings. In this embodiment, a reproduction circuit of a recording medium in which PWM recording is performed is taken up even in an optical storage device. Here, as described in the section of the prior art, there are roughly two methods for reproducing the recorded information that is PWM-recorded, but the explanation will be made by taking the comparator detection method, which is considered to have the greatest effect of the present invention, as an example. To do.

FIG. 4 is a block diagram of a reproducing circuit when the present invention is applied to the above-mentioned optical storage device. An edge position is detected by a comparator detection method, and a reproducing circuit using a Dual PLL for independently detecting front and rear edges is taken as an example. A description will be given below with reference to the drawings. First, in the optical storage device, a head amplifier 33 that converts a current signal from the photodiode into a voltage signal is mounted instead of the preamplifier of the magnetic storage device. On the other hand, the reproduction circuit after that is almost the same, VGA2 which has in common,
The booster 3, the filter 4, etc. have exactly the same functions. Furthermore, although the final stage amplifier 6 and the differentiator 5 are also common, this time it is necessary to detect the edge position of the reproduction signal, so the amplifier output 18 of the final stage amplifier 6 is input to the zero cross comparator 7 and the zero cross signal is input. 38, and the differential signal is input to the hysteresis comparator 8 to generate a gate signal, so that the operation is the reverse of that of the first embodiment. These signals are DATA Qualifier Logi
The edge position detection signal from which noise is removed is obtained at c9, but here, the rising edge (hereinafter referred to as the front edge) and the falling edge (hereinafter referred to as the rear edge) of the zero-cross comparator are separately detected and output. Then, these front and rear edge detection signals are separately PLL-processed,
It is a mechanism that will be combined later. The front edge and the rear edge are detected separately when the comparator level of the zero-cross comparator 7 is a fixed value and the comparator level is not the optimum value as shown in FIG. This is for avoiding the problem that the PLL is not locked and the problem that the error rate sharply deteriorates because 40 shifts in the opposite direction. In this way, by using the front and rear edge independent detection method, it is possible to eliminate the edge shift of a fixed length in each pit.

However, even if this method is adopted,
The boost level of booster 3 directly affects the error rate. It is because the boost level control affects the front and rear edge positions of the high frequency component of the recording signal, but does not affect the front and rear edge positions of the low frequency component, and independent front and rear edge detection that eliminates edge shift of a certain length of the pit. This is because the correction is completely independent of the method. Similarly, even if the boost level changes, the edge position does not change in the repeating pattern of the high frequency signal. Therefore, in the case of the recording waveform of FIG. 5, only the edge position indicated by * is affected by the boost level. Hereinafter, automatic control of the boost level will be described.

The automatic adjustment of the boost level is basically the same as in the first embodiment. The components common to the first embodiment are
Sample timing signal generation means 11, sample hold circuit 13, A / D converter 14, CPU 15, D /
The A converter 16. These functions are as described above, but there are a few points to note. First, since the sector information of the optical storage device is obtained as pre-mastered pit information in advance, the sampling timing with the sample timing signal should be in the area where the user actually recorded, avoiding this. Also, note that unlike magnetic recording, the area in which the closest packing pattern is written is generally called VFO instead of SYNC. That is, it suffices that the sampling timing be performed in this VFO area where the user actually recorded and the user data recording area.
Subsequent operations are the same as those in the first embodiment, and the description thereof will be omitted.

The element different from the first embodiment is that a peak detector 34, a bottom detector 35, and an amplitude calculation circuit 36 are added instead of the full-wave rectifier. The reason why the full-wave rectifier is not used to detect the amplitude is that the amplitude center value of the recording pattern most closely recorded does not always match the amplitude center value of another recording pattern having a low recording density, as shown in FIG. (Hereinafter referred to as a reproduction signal asymmetry). this is,
It is caused by thermal interference during recording and is a phenomenon unique to optical storage devices. Therefore, without using the full-wave rectifier, peak detection and bottom detection of the amplifier output 18 of the final stage amplifier 6 are performed separately, and the amplitude of the reproduction signal is obtained by the amplitude calculation circuit 36 from these. After that, the amplitude of the closest recording area is compared with the amplitude of the random recording area by sampling at least twice, and the boost control voltage 22 may be controlled. The peak detector 34 and the bottom detector 35
Is also used to determine the comparator level of the zero-cross comparator 7, and the center value calculation circuit 37 determines the amplitude center value to be the comparator level from these output signals. At this time, the amplitude center value is obtained in the VFO area described above in consideration of the asymmetry of the reproduced signal,
After that, it is preferable to perform control to hold the level.

As described above, finally, the leading edge detection signal 39 and the trailing edge detection signal 40 are separately obtained, independently PLL, and then combined to obtain the edge detection signal. With this edge detection signal, not only the problem of a certain amount of edge shift is solved by the function of the Dual PLL, but also the edge shift of each recording pattern can be suppressed by the automatic boost adjustment function. Therefore, in the optical storage device to which the present embodiment is applied, the edge detection accuracy of the reproduction signal is improved regardless of the frequency component of the recording signal, and the reliability of the device is improved. In addition, the optimum boost level is automatically set even when recording media having different recording densities are reproduced, which is effective for ensuring compatibility of the recording media.

(Embodiment 3) An embodiment of the present invention will be described with reference to the drawings. In this embodiment, an abnormality in the boost level is detected, and the boost control voltage is controlled only when the abnormality is detected. A specific example will be described below. As a specific example, an optical storage device using the comparator detection method as in the second embodiment is taken as an example, but here, a reproduction circuit for automatically controlling the comparison level is taken as an example. Therefore, D
The edge detection signal indicating both edge positions of the pit is directly obtained without using the ual PLL.

FIG. 6 is a block diagram of the reproducing circuit of this embodiment. Here, the feedback loop to the VGA 2 is not different from that in the above-described embodiments and is therefore omitted in this figure. The signal from the head is sent to the head amplifier 33,
From the VGA 2, the booster 3, the filter 4 to the amplifier 6 and the differentiator 5 at the final stage, these parts are also the same as the functions and paths described so far, and the description thereof will be omitted. First, the auto slice level control circuit taken up for the first time in this embodiment will be described. Therefore, consider slice level control of the reproduced waveform 61 that has already been boosted in the recorded information 60 as shown in FIG. In order to simplify the explanation, the case where the initial slice level 52 is deviated upward from the amplitude center value (ideal value) of the VFO area is taken as an example. At this time, the zero-cross signal 38 obtained from the zero-cross comparator 7 is shifted from the ideal edge position, and the edge detection signal 41 is also shown in FIG.
You can get the shifted one. The phase comparator 43 compares the phases of the edge detection signal 41 and the reference clock 42 and outputs a pulse having a phase difference. When the edge detection signal 41 is ahead of the reference clock 42 in phase, the UP signal 44, and when the edge detection signal 41 is behind, the DOWN signal 45.
Output as. One of these UP signal 44 and DOWN signal 45 is sent to a charge pump (not shown),
It is used to form a so-called data synchronizer PLL that supplies a control voltage to a voltage controlled oscillator (hereinafter referred to as VCO) through a low pass filter and generates a reference clock 42. On the other hand, both signals are also sent to the conversion Logic 46. The conversion Logic 46 converts the input pulse by adopting the configuration shown in FIG. 8, for example. In this example, both pulses of the UP signal 44 and the DOWN signal 45 are added and output as a Charge signal 47.
No pulse is output to the Discharge signal 48. At this time, the UP signal 44 and the DOWN signal 4 are important.
5. If the phase relationship of the zero-cross signal 38 does not mesh well, the pulse may disappear, or a pulse may appear in a signal opposite to the pulse signal that should be originally output. Particular attention must be paid to the input signal of the AND gate of. Then, these two output signals drive the charge pump 49 at the next stage, and the voltage smoothed by the loop filter 50 is fed back to the comparator level calculator 51 to output the slice level 52.
It is a mechanism to lower. In this example, Ch
Since the charge pump 49 is charged by the charge signal 47, the voltage fed back after the loop filter 50 tends to increase, and therefore the slice level calculator 51 needs to be a calculation circuit as shown in FIG. 9A. There is. On the other hand, the phase comparator 43 and the conversion Logic 46
In some cases, the charge pump 49 may be discharged even if the initial slice level is higher than the ideal value. In such a case, the slice level calculator 51 as shown in FIG. good. In either case, the slice level, which was larger than the ideal value, is corrected to approach the ideal value.

Conversely, when the slice level 52 is smaller than the ideal value, almost the same signal as above is obtained up to the phase comparator 43, but the output of the conversion Logic 46 remarkably changes. According to the previous example, the Charge signal 47 becomes a signal without a pulse as shown by the dotted line in FIG.
Since the charge signal 48 becomes a signal including a pulse, the charge pump 49 is discharged. Therefore, the voltage fed back after the filtering also moves in the opposite direction, and the slice level 52 is controlled to increase.
By doing so, the edge detection signal 41 is automatically controlled in the direction in which the edge detection signal 41 is synchronized with the reference clock 42, and as a result, automatic control can be performed such that the slice level 52 approaches the ideal value.

Although a simple phase comparator has been taken as an example here, in order to eliminate the dead zone of phase comparison, a constant pulse width is used for both the UP signal 44 and the DOWN signal 45 even when the phases are aligned. The phase comparator that outputs the pulse of and then controls the pulse width is often used. Of course, the present embodiment can be applied to such a case. Also, since only one example is shown for the conversion Logic 46, different logic circuits are naturally required depending on the output signal of the phase comparator 43. However, it should be added that even in such a case, the conversion Logic 46 can be configured without any problem.

In the reproducing circuit as described above,
Several methods can be considered for boost abnormality detection. For example, as shown in FIG. 6, two circuits for sample-holding the output of the amplitude calculation circuit 36 are provided, the amplitude of the random recording pattern is used in the first sample-hold circuit 53, and the closest density is used in the second sample-hold circuit 54. The amplitude of the recording pattern is sampled. Since the output of the first sample hold circuit 53 is attenuated by resistance voltage division, for example, the resistance 55, the resistance 56, and the resistance 57.
When the ratio is 1: 1: 8, the amplitude of 90% of the peak level of the random recording pattern is input to the inverting input of the first comparator 58 and the random recording pattern is input to the non-inverting input of the second comparator. An amplitude of 80% of the peak level of will be input. At this time, when the amplitude of the closest packing pattern exceeds 90%, the output of the first comparator 58 goes high to notify the CPU 15 of the abnormality, and the amplitude of the closest packing pattern falls below 80%. In this case, the output of the second comparator 59 goes high to notify the CPU 15 of the abnormality. When the signal received from the comparator shows a high level, the CPU 15 determines that it is abnormal, sends data to the D / A converter 16 according to the bit in which the abnormality is detected, and controls the boost control voltage 22. In this way, this control is continued until the amplitude of the closest recording pattern enters from 80% to 90%. On the contrary, if the amplitude of the closest recording pattern is within the specified value (80% to 90% in this case), the outputs of the two comparators are both at the low level, and the CPU 15 does not have to do anything. By doing so, the occupancy of the CPU 15 is reduced with respect to the automatic adjustment of the boost level, so that efficient adjustment is possible.

Since the above-mentioned attenuation ratio can be freely set, the range of the specified value can be made small or the range itself can be vertically shifted when precise control is required. . For example, if the range is narrowed, the probability of being judged to be abnormal by the monitoring result increases, but there is also control such as cumulative counting of normal and abnormal judgment results and updating the boost level when the difference exceeds a certain value. I can.

(Embodiment 4) Next, another embodiment for detecting abnormality will be described. It is premised that the reproducing circuit is equipped with the auto slice level control circuit by the compare detection method described above. For example, consider the case where the boost level is low as shown in FIG.
At this time, even if the slice level 52 is an ideal value, the edge detection signal 41 cannot detect an accurate edge position at the position marked with * in the reproduced waveform 61. As a result, C
A signal in which a pulse appears is output to both the charge signal 47 and the discharge 48. This means that the first two * marks are instructed to increase the slice level, and the latter two * marks are instructed to decrease the slice level. However, in reality, these signals are smoothed by the filter and the slice level 52
Has no effect on On the other hand, in this state, the phase of the edge detection signal 41 and the reference clock 42 in the PLL of the data synchronizer will never match, so that the PLL is not locked. Therefore, the abnormal boost level can be detected by detecting the unlock of the PLL of the data synchronizer. As a specific control, the CPU may send data to the D / A converter after detecting the PLL unlock and control the boost control voltage. However, in this abnormality detection method, it is unclear whether boosting up or boosting down is required, so it is necessary to perform either or both operations until the PLL locks. Further, the unlock detection of this PLL is also applicable to a detection method using a Dual PLL and a reproducing circuit using a second-order differential detection method.

As another method of detecting an abnormality, a method of utilizing error correction of a decoder can be considered. This is because the PLL of the data synchronizer is locked when the boost level is too high or too low,
Since the position of the edge of the reproduction signal is shifted and detected, the fact that an error occurs at the time of decoding becomes high is utilized. Specifically, it counts the number of errors when it is corrected, and if it exceeds a certain level, it is judged as a boost level abnormality,
When an uncorrectable error occurs, it is judged as abnormal and C
The abnormality detection signal is sent to the PU, and the control described so far may be performed thereafter.

(Embodiment 5) An embodiment of the present invention will be described with reference to the drawings. As the reproducing circuit, the one related to the magnetic memory device described in the first embodiment will be taken as an example. 11, blocks having the same functions as those in FIG. 1 are designated by the same reference numerals. Therefore, the head output passes through the preamplifier 1, the VGA 2, the booster 3, and the filter 4, reaches the differentiator 5 and the final stage amplifier 6, and is amplified. In addition, the amplifier output 18 at the final stage passes through the full-wave rectifier 10 to VGA.
2 and the output of the zero cross comparator 7 and the hysteresis comparator 8 are DATA.
The process of inputting to the Qualifier Logic 9 and obtaining the noise-removed peak detection signal 23 is exactly the same.

Here, in particular, the components of the frequency detecting means and the method of automatically controlling the cutoff frequency of the filter 4 using the output signal thereof will be described. The frequency detecting means 64 comprises a filter 62 having a known frequency characteristic and an amplitude detecting means 63 for detecting the amplitude after filtering. Filter 62 having a known frequency characteristic
Prepares a filter having a frequency characteristic as shown in FIG. This filter has frequency characteristics selected so that the amplitude detection means 63 in the subsequent stage can detect the amplitude not only when the frequency band of the reference reproduction signal is input, but also when the signals of the frequencies on both sides thereof are input. Then, the amplitude of the filtered signal is detected by the amplitude detecting means 63 in the subsequent stage. According to this structure, the detected signal amplitude changes depending on the frequency of the reproduction signal input to the filter 62 having a known frequency characteristic, so that frequency / voltage conversion can be performed. In the case of the filter shown in the above example, the detected signal amplitude 66 becomes smaller as the frequency becomes higher, and this value becomes A /
It is sent to the CPU 15 through the D converter 14. C
The PU 15 controls the D / A converter 16 according to the magnitude of the received amplitude value, and the control voltage 67 that determines the cutoff frequency is fed back to the filter 4. As a guideline at this time, it is desirable to set the frequency which is about 1.5 to 2 times the maximum frequency of the reproduced signal as the cutoff frequency. From this, the filter 62 having a known frequency characteristic does not center the frequency band of the reproduction signal as shown in FIG. 12A, but centers the cutoff frequency of the target reproduction signal. You may prepare the filter like FIG.12 (b) which has a frequency characteristic. At this time, as a concrete control method, if the cutoff frequency of the filter matches the target value, the signal amplitude 66 obtained by the amplitude detecting means 63 should be the output of the VGA 2 × gain: k. If the obtained value is larger than this, the cutoff frequency may be lowered, and if the actually obtained value is smaller than this, the cutoff frequency may be raised.

By doing so, the cutoff frequency of the filter can be automatically set according to the frequency of the reproduction signal, so that high-frequency noise is efficiently removed even during variable speed reproduction, and the reliability of the apparatus is improved. It can be done.

Although some specific examples have been described so far, it should be added that other configurations are possible. First, there is a type of filter having a known frequency characteristic. However, since it is sufficient that the monotonicity for amplitude detection is maintained, a high-pass filter is used in addition to the low-pass filter shown in FIG. It can also be used. In this case, since the voltage level of the detected signal amplitude 66 increases as the frequency of the reproduction signal input to the filter 62 increases, the reverse operation to the control described above may be performed. Further, when handling a plurality of modulated signals in the same reproducing circuit, it may be necessary to set a plurality of cutoff frequencies. In such a case, the frequency characteristic of the filter 62 may be changed by the control signal 65. And so on. Further, although the magnetic storage device of the first embodiment has been described here as a specific example, it goes without saying that the magnetic storage device of the first and second embodiments can also be applied.

(Embodiment 6) An embodiment of the present invention will be described below with reference to the drawings. Figure 1
The digital data in 3 is a signal corresponding to the output signal of the DATA Qualifier Logic described above, and can be regarded as a signal equivalent to so-called recorded data in which the position corresponding to “1” is detected from the reproduction signal. . On the other hand, the phase comparator 68, the charge pump 69, the loop filter 70, and the VCO 71 are a very general configuration of the PLL of the data synchronizer. The operation is to detect the phase difference between the digital data and the reference clock 77 from the VCO, drive the charge pump 69, and apply the filtered voltage to the VCO 71 to change the oscillation frequency of the VCO 71. At this time, since the reference clock 77 of the VCO 71 is fed back to the phase comparator 68, the phase difference between the reference clock 77 and the digital data is controlled so as to disappear. As a result, when the PLL of the data synchronizer is locked, the digital data is exactly a constant multiple of the oscillation frequency of the VCO 71.

Therefore, in this embodiment, a method of obtaining the frequency of the reproduced signal by counting the oscillation frequency of the VCO 71 when the PLL of the data synchronizer is locked by the counter 72 is adopted. Specifically, it is as described below. First, the crystal 76 oscillates at a certain fixed frequency. Here, if the oscillation frequency of the crystal is f [Hz], the counter 75 counts the clock from the crystal until the count value reaches M. When the count value reaches M, the counter 75 latches the count value of the counter 72 and simultaneously resets its own count value. If the count value of the counter 72 latched at this time is N, the frequency of the reference clock 77 of the VCO 71 can be calculated by the following equation.

(Channel bit rate) = (frequency of reference clock) ≈f × N / M [Hz] On the other hand, the maximum frequency of the reproduction signal varies depending on the modulation method at the time of recording, but in the case of CD or DVD, for example. , The minimum value of Run Length of the recorded modulation signal is limited to 2, so 1/3 of the channel bit rate
Corresponds to the maximum frequency. That is, (maximum frequency of reproduced signal) = 1/3 × f × N / M [H
z]. Next, regarding the relationship between the maximum frequency of the reproduction signal and the cutoff frequency of the filter 74, for example, when the cutoff frequency of the filter 74 is set to 1.5 times the maximum frequency of the reproduction signal, the cutoff frequency of the filter 74 is Can be expressed as (cutoff frequency) = 1/2 × f × N / M [Hz]. Here, the frequency of the crystal 76:
Since f and the count value M of the counter 75 when sending the latch signal are both determined, the cutoff frequency of the filter is determined only by the count value N of the counter 72 at the time of latching.

In order to make the explanation more comprehensible, description will be given below with reference to specific numerical values. First, the maximum frequency of the reproduced signal is assumed, but here it is assumed that the modulation system of CD or DVD is assumed, and it is assumed to be 8 [MHz]. On the other hand, the oscillation frequency of the crystal is 24 [MHz]. Further, the number of bits of the counter 72 and the D / A converter 73 is set to 8 and 0
It is assumed that counting up to 255 and D / A conversion are possible. The clock of the crystal 76 is counted up to 127 by the counter 75, and the count value of the counter 72 at this time is latched. Then, when the count value at that time is 127 as in the case of the counter 75, the cutoff frequency of the filter is configured to be the maximum frequency of the signal × 1.5 times = 12 [MHz]. On the other hand, if the count value of the counter 72 at the time of latching is smaller than 127, it means that the frequency of the reproduction signal is also lower than the expected value, and accordingly the cutoff frequency is set lower than 12 [MHz]. On the other hand, if the count value of the counter 72 at the time of latching is larger than 127, it means that the frequency of the reproduction signal is high.
Accordingly, the cutoff frequency may be set higher than 12 [MHz].

FIG. 14 shows the relationship between the set value of the D / A converter 73 and the cutoff frequency of the filter 74, which realizes the above specific example. Although the reference value of the D / A converter 73 is 127 here, the counter 7
By shifting this value together with the count value of 5, the detection range of the reference clock 77 can be changed. Also,
The number of bits of the counter 72 and the D / A converter 73 is not limited to this specific example and can be set freely.

With the above-described structure, the reproduction signal frequency is obtained from the clock synchronized with the PLL, so that an accurate frequency can be obtained regardless of the quality of the analog signal, and as a result, the cutoff frequency of the filter is also set strictly. Is possible.

(Embodiment 7) An embodiment of the present invention will be described below with reference to the drawings. Figure 1
In FIG. 5 (a), the data synchronizer 78 outputs the reproduced data sequence 84 and the synchronous clock 85, and the pattern detection means 79 compares the reproduced data sequence 84 with the detected pattern. Here, the detection pattern is a unique pattern that does not appear in the user information recording area. For example, a SYNC pattern added when forming a sector corresponds to this. The pattern detection means 79 compares the reproduction data sequence 84 with the detection pattern, and only when the both match, the coincidence detection pulse 8 is detected.
6 is generated. Then, the timer 80 measures the time between two coincidence detection pulses and sends the result to the CPU 81. At this time, if only the format of the recorded data is known in advance, the maximum frequency of the reproduction signal can be estimated by measuring the time between the coincidence detection pulses. That is, the CPU 81 obtains the maximum frequency of the reproduction signal from the result received from the timer 80, sends data to the D / A converter 82 to set the optimum cutoff frequency, and is digital / analog converted by the D / A converter. The analog signal is fed back to the filter 83.

On the other hand, after performing the pattern detection, FIG.
It is also possible to set the cutoff frequency of the filter 83 by the configuration shown in (b). According to this configuration, the function is the same as that described above until the pattern detecting means 79 compares the reproduction data sequence 84 received from the data synchronizer 78 with the detection pattern. The difference from the above-mentioned configuration is that a counting means 87 is used to count how many coincidence detection pulses 86 are detected within a constant time given by a timer 88. Therefore, this time CPU
The information obtained at 81 is not the time information between the detection patterns but the detection number information of the detection patterns. However, in any case, the maximum frequency of the reproduced signal can be easily estimated if only the format of the recorded data is known. That is, from here, data is sent to the D / A converter 82 in the same manner as described above, and the filter 8 is converted into an analog signal which is digital / analog converted by the D / A converter.
Adjust the cutoff frequency of 3 to the optimum value.

The configuration as described above has the following advantages. Since the detection pattern described above is a signal such as a SYNC pattern that must be detected in the first place, the function originally existing can be shared and used. That is, it can be said that it can be realized without a large additional circuit.

(Embodiment 8) An embodiment of the present invention will be described below. The embodiment described here is a combination of booster boost level and automatic adjustment of the filter cutoff frequency. Therefore, basically, by combining the above-described embodiments, both can be automatically adjusted.

Specifically, the boost level is automatically adjusted by the amplitude detecting means for detecting the amplitude of the boosted analog waveform and the sample timing signal generating means for giving the timing, and in addition, the frequency detecting means for the reproduced signal is provided. Therefore, the cutoff frequency of the filter is automatically adjusted. The frequency detecting means at this time may be the filter + amplitude detection shown in the fifth embodiment, or the PLL of the data synchronizer shown in the sixth embodiment. Furthermore, it is also possible to set the cutoff frequency by using the pattern detecting means shown in the seventh embodiment.

In such a combination, an example will be described below in which the functions are shared by both parties.
That is, the sample timing signal used when the boost level is automatically adjusted is also used as the timing signal that determines the cutoff frequency of the filter.

That is, the sample timing signal when the sample timing signal generating means instructs sampling of the closest recording area in the recording data is used as the sample timing signal of the amplitude detecting means which constitutes the frequency detecting means in the fifth embodiment. Is also used. By doing so, the reproduction signal detected by the amplitude detecting means has a single frequency, so that strict detection is possible. Further, the sample timing signal when the sampling of the closest recording area in the recording data is instructed is the PLL of the data synchronizer.
Since it is also a timing signal for locking, the frequency detection according to the sixth embodiment can be performed with this timing signal, and accurate frequency detection can be performed in this case as well.

As described above, if the boost level and the cutoff frequency are automatically adjusted at the same time, the reproduced signal is always processed in an analog signal in the optimum state, so that the noise and the jitter are small and the reliability is high. Highly sensitive data can be detected. This improves the reliability of the information storage device and, at the same time, helps maintain compatibility between the devices.

[0065]

As described above, according to the present invention, 1) even if the characteristics of the reproducing head of a removable information storage device are changed by increasing the density, the reproducing signal amplitude is always at a constant level regardless of the recording density. Therefore, the compatibility of the device can be maintained. This means that the reproduction compatibility can be secured even if a high density recording medium is released in the future. Further, since the boost level can be automatically controlled and the optimum reproduction signal for data detection can always be obtained, it is possible to provide a device that is resistant to changes over time and changes in environmental temperature.

2) Even in the information storage device in which the PWM recording is performed, the boost level is automatically adjusted without depending on the asymmetry of the reproduction signal, the edge detection accuracy of the reproduction signal is improved, and the reliability of the device is improved. .

3) Abnormality of the boost level is monitored and the boost level is updated only when there is an abnormality, thereby reducing the load on the CPU and enabling efficient setting change.

4) By substituting the PLL of the data synchronizer and the monitoring of the correction flag for error correction for the abnormality detection of the boost level, the boost level can be automatically adjusted without any special additional circuit.

5) Since the cutoff frequency of the filter can be automatically set in accordance with the band of the reproduced signal, high frequency noise is efficiently removed and the reliability of the device is increased.

6) The reproduction signal frequency is obtained from the clock synchronized with the PLL, and the cutoff frequency of the filter is automatically adjusted according to the value, so that more strict setting is possible.

7) By sharing the originally required pattern detection function, the filter can be adjusted without a large additional circuit.

8) Since both the boost level of the booster and the cutoff frequency of the filter are automatically adjusted, the reproduced signal is always analog signal processed in the optimum state, and highly reliable data detection can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a magnetic storage device according to a first embodiment of the present invention.
It is a block diagram showing a schematic structure of a reproducing circuit.

FIG. 2 is an explanatory diagram of head output waveforms for each type in the magnetic storage device taken up in Example 1 of the present invention.

FIG. 3 shows a magnetic storage device according to the first embodiment of the present invention.
FIG. 3 is a timing chart showing waveforms at various points in the circuit block diagram.

FIG. 4 is a block diagram showing a schematic structure of a reproducing circuit in an optical storage device according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram for supplementing the description of the reproducing circuit in the optical storage device according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic structure of a reproducing circuit in an optical storage device according to a third embodiment of the present invention.

FIG. 7 is a waveform diagram for supplementing the description of the reproducing circuit in the optical storage device according to the third embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a detailed circuit of conversion Logic in the optical storage device according to the third embodiment of the present invention.

FIG. 9 shows an example of a detailed circuit of a comparator level calculator in an optical storage device according to a third embodiment of the present invention,
6A is a circuit diagram in which a signal from a loop filter is subtracted, and FIG. 7B is a circuit diagram in which a signal from a loop filter is added.

FIG. 10 shows an optical storage device according to a fourth embodiment of the present invention,
FIG. 6 is a waveform diagram for supplementing the explanation of boost level abnormality detection.

FIG. 11 is a block diagram showing a schematic structure of a reproducing circuit in a magnetic memory device according to a fifth embodiment of the present invention.

FIG. 12 shows an example of a filter used for frequency detecting means in a magnetic memory device according to a fifth embodiment of the present invention,
FIG. 6A is a diagram showing a frequency characteristic of a filter based on a reproduction signal band, and FIG. 6B is a diagram showing a frequency characteristic of a filter based on a target cutoff frequency.

FIG. 13 is a block diagram showing a configuration of frequency detecting means in an information storage device according to a sixth embodiment of the present invention.

FIG. 14 is a characteristic diagram showing a specific relationship between the D / A converter and the cutoff frequency of the filter in the information storage device according to the sixth embodiment of the present invention.

FIG. 15 is an example of a circuit for setting the cutoff frequency of the filter by the pattern detection means in the information storage device of the seventh embodiment of the present invention, in which (a) is a type for feeding back the time between coincidence detection pulses, and (b) ) Is a block diagram of a type that feeds back the number of detections of coincidence detection pulses.

FIG. 16 is a waveform diagram for explaining a process of peak detection of a reproduction signal recorded in PPM in a conventional optical storage device.

FIG. 17 is a waveform diagram for explaining a process of edge detection of a reproduction signal PWM-recorded in a conventional optical storage device.

[Explanation of symbols]

1 preamplifier 2 VGA 3 boosters 4, 62, 74, 83 filters 5 Differentiator 6 final stage amplifier 7 Zero cross comparator 8 Hysteresis comparator 9 DATA Qualifier Logic 10 full-wave rectifier 11 Sample timing signal generation means 12 comparator 13 Sample and hold circuit 14 A / D converter 15, 81 CPU 16, 73, 82 D / A converter 17, 63 Amplitude detection means 18 amplifier output 19 Full wave rectified waveform 20 sample timing signal 21 Sampling signal 22 Boost control voltage 23, 106 Peak detection signal 24, 60, 100 Recorded information 25 recording status 26 Magnetic coil type head output 27 Magnetoresistive head output 28 peak level 29 Reset signal 30 corrected waveform 31 Closest recording area 32 random recording area 33 head amplifier 34 Peak detector 35 Bottom detector 36 Amplitude calculation circuit 37 Center value calculation circuit 38, 105 Zero cross signal 39 Front edge detection signal 40 Rear edge detection signal 41 Edge detection signal 42, 77 Reference clock 43, 68 Phase comparator 44 UP signal 45 DOWN signal 46 Conversion Logic 47 Charge signal 48 Discharge signal 49, 69 Charge pump 50, 70 loop filter 51 Comparator level calculator 52 slice level 53 First sample and hold circuit 54 Second sample and hold circuit 55, 56, 57 resistance 58 First Comparator 59 Second comparator 61 Playback waveform 64 frequency detection means 65 control signal 66 signal amplitude 67 Control voltage 71 VCO 72,75 counter 76 crystal 78 Data Synchronizer 79 pattern detection means 80, 88 timer 84 Playback data string 85 Synchronous clock 86 Match detection pulse 87 counting means 101 and 107 recording pits 102, 103, 108, 109 playback signal 104 differential waveform

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 5/00-5/24 G11B 5/09 G11B 20/10-20/16

Claims (3)

(57) [Claims] 1. An information processing apparatus comprising: a booster for inputting digital information as an analog waveform, amplifying a specific frequency of the analog waveform; and a filter for removing high-frequency noise of the output of the booster. The amplitude detection means for detecting the amplitude of the waveform, the sample timing signal generation means for giving the timing of the amplitude detection, and the frequency detection means for the reproduced signal, which is regarded as the equivalent signal to the digital data detected from the analog waveform, are combined. An information processing apparatus, wherein the boost level of the booster is automatically adjusted based on the detection result of the detection means, and the cutoff frequency of the filter is automatically adjusted based on the detection result of the frequency detection means. 2. An information storage device comprising a booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform, and a filter for removing high-frequency noise of the output of the booster. An amplitude detecting means for detecting the amplitude of the analog waveform after boosting, a sample timing signal generating means for giving a timing of amplitude detection, and a frequency detecting means for a reproduced signal which is regarded as an equivalent signal to the record data detected from the analog waveform. The boost level of the booster is automatically adjusted based on the detection result of the amplitude detection means, and the cutoff frequency of the filter is automatically adjusted based on the detection result of the frequency detection means. Information storage device. 3. An information storage device comprising a booster for reading a modulated signal digitally recorded on a recording medium as an analog waveform and amplifying a specific frequency of the analog waveform, and a filter for removing high frequency noise of the output of the booster. An amplitude detecting means for detecting the amplitude of the analog waveform after boosting, a sample timing signal generating means for giving a timing of the amplitude detection, and a peculiarity which does not appear in a user information recording area physically arranged on the recording medium. A detection pattern of a unique recording pattern obtained by the pattern detecting means, which automatically adjusts the boost level of the booster based on the detection result of the amplitude detecting means. Depending on the number of unique recording patterns detected in a cycle or unit time Information storage apparatus characterized by automatically adjusting the cutoff frequency of the serial filter.