JP2007299448A - Wide capture circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wide capture circuit of a digital data reproducing device, configured to improve the frequency error detecting accuracy for wide capturing with a circuit configuration suitable to the PRML signal system, to achieve high-speed frequency pull-in and phase pull-in and to reduce the seek time when reproducing digital data recorded on an optical disk medium. <P>SOLUTION: This wide capture circuit has a first wide capture section 1030a to detect synchronization pattern length and to output the frequency errors between the oscillation frequency of ICO9 and the reproduction clock frequency of the reproduced signal, a second wide capture section 1030b to detect the cycle of the synchronized pattern and to output the frequency errors between the oscillation frequency of ICO9 and the reproduction clock frequency of the reproduced signal, a frequency error output section 1031 to selectively output the binary information of the frequency errors or the multi-value information of the frequency errors, a phase comparator 104, and a switch section 105. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wide capture circuit of an apparatus for reproducing a signal from an optical disc, and more particularly, using a phase-locked loop such as a PLL (Phase-Locked Loop) to extract a synchronized clock signal and a multi-valued signal, and PRML ( The present invention relates to a wide capture technique in an apparatus capable of reproducing a signal in a Partial Response Maximum Likelihood) circuit.

  As a conventional example, for example, in Japanese Patent Application Laid-Open No. 2005-135579 (Patent Document 1), at the time of CLV (constant linear velocity) reproduction, the length of a specific pattern is counted by a fixed clock, and a reproduction clock, a reproduction digital signal, A so-called wide capture method is described in which the VCO is controlled so that frequency control is performed up to a region where synchronization is possible.

Further, in a conventional optical disk reproducing apparatus, a multi-bit digital signal is sampled and PRML (Partial Response Maximum Likelihood) combining a partial response method and a Viterbi decoder which is one of the maximum likelihood decoding methods (maximum like-liqued). Signaling schemes have been proposed. For example, as described in Japanese Patent Laid-Open No. 2003-36612 (Patent Document 2), this PRML signal method is designed to intentionally add waveform interference along with an increase in recording density in the linear recording direction. This is a system that realizes a reproduction system that does not require components and improves the quality of reproduction data by probability calculation in consideration of waveform interference.
JP 2005-135579 A JP 2003-36612 A

  However, the first problem in the above conventional example is that Patent Documents 1 and 2 cannot cope with the CAV method. In the conventional wide capture method of Patent Document 1 or 2, the synchronization pattern is counted with a high-frequency fixed clock, and therefore can only be used with the CLV method of reproducing with a fixed clock. It cannot be used in a CAV system with a constant angular velocity that is 2.5 times different in frequency from the inner circumference to the outer circumference.

  The second problem is that the method of Patent Document 1 has low detection accuracy and cannot be used for a high-speed digital PLL. In Patent Document 1, the length of a specific pattern, in the case of a CD, 11T period detection means and 6T (000111 or 111000) recording patterns are counted. 1T indicates one channel clock period. When the channel clock frequency is used, the accuracy is 1 / 11T = 9% and 1 / 6T = 16%, respectively. When using twice the clock, they are 4.5% and 8%, respectively. Since the 16-times speed of DVD-ROM is 418.56 MHz, it is difficult to use a clock that is twice or three times the channel clock in order to increase accuracy.

  In an analog type PLL circuit that discharges and absorbs a constant current according to the phase error voltage and converts the output current of the charge pump into a voltage by a loop filter, the reproduction data has the clock frequency of the voltage controlled oscillator. If the clock frequency is about ± 5%, phase synchronization pull-in is possible.

  However, the digital PLL has a narrower phase pulling range than the analog type due to the delay of the loop delay FF (flip-flop), and is 0.5 to 2%. The delay time of digital type PLL and the limit of ωn and damping factor ζ that stabilize the loop are described in the document “JW M Bergmans,“ Effect of Loop Delay on Stability of Time PLL, ”IEEE trans. , Vol.42, No. 4, Apr. 1995 ". As the delay time increases, ωn decreases, the open gain cannot be increased, and the capture range cannot be expanded. In the wide capture of the digital PLL, it is necessary to increase the frequency pulling accuracy.

  The third problem is that frequency pull-in cannot be performed at high speed for a read-only disk without wobble. On the writing disk, a recording guide groove wobble (Wobble) periodically wobbling the disk is written, and this wobble is read to generate a recording clock (wobble clock) necessary for writing. If the wobble clock is used as a reference clock, it is possible to know how much the recovered clock is shifted, and it is possible to output a frequency error to the loop filter and to pull it in at high speed.

  However, since there is no wobble in the CD-ROM and DVD-ROM, it is impossible to detect how much the deviation is from the reference clock. Since the greatest feature of the optical disk apparatus is random access, it is necessary to speed up the PLL synchronization at the time of high-speed seek.

  In addition, it is necessary to support playback-only discs such as BD (Blu-ray Disc) and HD DVD, which are said to be DVD next-generation discs.

  The fourth problem is that in the DVD-RAM disk having a format different from that of the ROM disk, the old type drive writes user data not in wobble clock synchronization but in fixed clock synchronization (referred to as crystal light). . The clock frequency of the PID part in which the address is written in advance and the newly written user data part are different by 0.5% to 2%. Therefore, a case where ID1 to ID4 of the PID part cannot be read occurs. For this reason, it is necessary to pull in different frequencies of the crystal-written DVD-RAM disk at high speed so that the PID can be read.

  Accordingly, the present invention has been made to solve the above-described problems. In reproducing digital data recorded on an optical disc medium, the present invention has a circuit configuration suitable for the PRML signal system, and a wide capture frequency error. It is an object of the present invention to provide a wide capture circuit of a digital data reproducing apparatus having a circuit configuration in which detection accuracy is improved, high-speed frequency acquisition and phase acquisition are possible, seek time is shortened, and these characteristics are taken into consideration. In particular, the present invention is applicable to CLV and CAV ROM-type discs.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A wide capture circuit according to the present invention is a wide capture circuit in an optical disc apparatus that reproduces information of an optical disc on which a synchronization signal having a predetermined sync pattern length and a digital signal is recorded. The reproduction signal reproduced from the optical disk detects the synchronization pattern length of the code bit sampled based on the reproduction clock, and the oscillation clock whose oscillation frequency changes according to the output value of the loop filter and the reproduction clock possessed by the reproduction signal A first frequency pull-in unit that outputs a frequency error with respect to the frequency, and a period in which the synchronization pattern of the sign bit exists, and a frequency error between the oscillation frequency of the oscillation unit and the reproduction clock frequency of the reproduction signal is output. Two frequency pull-in sections, a first frequency pull-in section and a second frequency pull-in Based on the frequency error output from the memory unit, binary information indicating whether the recovered clock frequency is slow or fast, or multi-value information indicating how slow or fast the recovered clock frequency is, can be selected. A first frequency error output unit that outputs, a phase comparison unit that compares the phases of the reproduction clock and the reproduction signal, and outputs a phase error, an output of the first frequency error output unit, and an output of the phase comparison unit And a switch unit that outputs to the loop filter.

  Further, the wide capture circuit according to the present invention detects a wobble signal that is a periodic meandering signal from an optical disc having a recording guide groove that meanders periodically, and outputs a clock synchronized with the wobble signal. A wide capture circuit in an optical disc apparatus for recording or reproducing information on an optical disc, wherein a reproduction signal reproduced from the optical disc detects a synchronization pattern length of a code bit sampled based on a reproduction clock, and loops The first frequency pull-in unit that outputs a frequency error between the oscillation frequency of the oscillation unit whose oscillation frequency varies depending on the output value of the filter and the reproduction clock frequency of the reproduction signal, and the period in which the code bit synchronization pattern exists is detected. The frequency error between the oscillation frequency of the oscillator and the recovered clock frequency of the recovered signal A second frequency pulling unit that outputs, a third frequency pulling unit that outputs a frequency error between the wobble clock of the wobble signal processing unit and the reproduction clock frequency of the reproduction signal, a first frequency pulling unit, a second Based on the frequency error output from the frequency pull-in unit and the third frequency pull-in unit, binary information indicating whether the reproduction clock frequency is slow or fast, or how late or fast the reproduction clock frequency is A first frequency error output unit that selects and outputs multi-value information to be displayed, a phase comparison unit that compares the phases of the recovered clock and the recovered signal, and outputs a phase error; an output of the frequency error output unit; And a switch unit that switches the output of the comparison unit to output to the loop filter.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the reproduction of digital data recorded on an optical disk medium, it is possible to increase the frequency error detection accuracy of wide capture, enable high-speed frequency acquisition and phase acquisition with a circuit configuration suitable for the PRML signal system, and shorten the seek time. it can. In particular, the present invention is applicable to CLV and CAV ROM-type discs.

  Further, different frequency pull-in of the wobble clock synchronization unit and the crystal clock synchronization unit of the crystal-written DVD-RAM disk can be performed at high speed, and both PID and user data can be read.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<Configuration of optical disc apparatus including wide capture circuit>
With reference to FIG. 1, the configuration of an optical disc apparatus including a wide capture circuit according to Embodiment 1 of the present invention will be described. FIG. 1 is a configuration diagram showing the configuration of an optical disc apparatus including a wide capture circuit according to Embodiment 1 of the present invention.

  In FIG. 1, an optical disk device including a wide capture circuit includes an optical disk 1 such as a DVD-ROM, a spindle motor 2, an optical head (PU) 3, an I / V converter 4, a wobble processing unit 5, an RF data processing unit 6, A first offset correction unit 7, an A / D converter 8, a current control oscillation unit (ICO) 9, a PLL unit 10 that operates with a 1 / n clock of the channel bit rate, a demodulated signal processing unit 11, a control unit 12, Crystal oscillator (X'tal) 51, 1 / n frequency divider 52 that divides the wobble clock or X'tal clock by 1 / n, auto gain control (AGC) unit 61, high-pass filter (HPF) unit 62, equalizer (EQ) section 63, serial / parallel conversion section 101, second offset correction section 102, a plurality of wide capture sections 1030a to 1030c, frequency The difference output section 1031, a phase comparator 104, the switch unit 105 for switching a phase locked loop or a frequency-locked loop, and a loop filter unit 106, D / A converter 107.

  Further, the current control oscillation unit (ICO) 9 and the PLL unit 10 constitute a wide capture circuit.

  The optical disk 1 is held and rotated by a spindle motor 2, and the optical head 3 forms a semiconductor laser that emits laser light for recording or reproducing information, and light from the semiconductor laser is formed as a light spot on the disk surface. And an optical detector for performing light spot control such as information reproduction and autofocus and track tracking using reflected light from the optical disk 1, and recording information on the optical disk 1, Information on the optical disc 1 is reproduced.

  The optical disk apparatus is connected to a host computer (hereinafter referred to as “host 13”) such as a personal computer or a workstation, and receives instructions and information data from the host 13 through a control unit 12 including a microcomputer or the like. Perform recording, playback, and seek operations (moving the head to the target track).

<Operation of playback processing>
Next, referring to FIGS. 1 and 2, the operation of the reproduction process of the optical disc apparatus including the wide capture circuit according to the first embodiment of the present invention will be described. FIG. 2 is an explanatory diagram for explaining the operation of the reproducing process of the optical disc apparatus including the wide capture circuit according to the first embodiment of the present invention, and shows an outline of the PR (1, 2, 2, 1) pattern. Yes.

  First, the host 13 issues a reproduction start instruction to the control unit 12 and receives a signal from the optical head 3. The I / V converter 4 converts the current / voltage converted reproduction signal into the wobble processing unit 5 and the RF data. Output to the processing unit 6.

  The wobble processing unit 5 extracts a wobble signal corresponding to the wobbling recording guide groove wobbled periodically on the disc, and outputs a wobble clock as a binary signal synchronized with this signal. Further, it is possible to generate a clock obtained by dividing the clock of the crystal oscillation unit (X′tal) 51 by 1 / n.

  The RF data processing unit 6 includes an auto gain control (AGC) 61, a high pass filter (HPF) 62, an equalizer (EQ) 63, and the like. The AGC 61 controls the gain so that the amplitude of the signal from the I / V converter 4 becomes constant. The HPF 62 is provided to eliminate low-frequency DC fluctuations included in the reproduction signal. The EQ unit 63 corrects the attenuation of the high frequency component due to the optical characteristics.

  A channel clock is generated by the PLL unit 10, and the A / D converter 8 samples the reproduction data by the channel clock (see FIG. 2).

  The center input DC value of the A / D converter 8 is 0 at the output. In consideration of the input range of the A / D converter 8 at the center of 0 (zero), the standard input to the A / D is determined. When the A / D converter is 7 bits, the A / D output takes values from −64 to +63 when expressed in two's complement.

  The PLL unit 10 generates a reproduction clock for reproducing address data and user data from the RF signal that has passed through the RF data processing unit 6. Here, the reproduction clock is a channel bit rate clock (CK) for sampling the data of the A / D converter 8 and a channel bit rate 1 / n clock for operating the digital circuit in the PLL 10. The channel bit rate clock (CK) is also used when the serial / parallel converter 101 converts data from channel bit rate serial data to n parallel data.

  The reproduction signal is reduced in offset by the first offset correction unit 7, quantized into a multi-bit digital signal by the A / D converter 8, further reduced in offset by the second offset correction unit 102, and demodulated. It is reproduced by the signal processing unit 11. The demodulated signal processing unit 11 is reproduced by a PRML signal system that combines a Viterbi decoder, which is one of a partial response system and a maximum likelihood decoding system (maximum live-cliff).

  In the PRML signal system, since the sampled multi-bit digital signal value is meaningful in Viterbi decoding, it is important that the phase of the recovered clock is synchronized with the phase of the clock component of the recovered signal. In addition, it is necessary to output the reproduction clock stably without the PLL unit 10 being unlocked due to disturbances such as scratches and noise.

  The PLL unit 10 that generates the reproduction clock is a digital PLL that controls the frequency of the oscillator by a digital value by the D / A converter 107. From the signal offset-corrected by the second offset correction unit 102, a phase error before and after the zero cross point is extracted by the phase comparator 104, noise is removed by the loop filter unit 106, and the signal is passed through the D / A converter 107. Thus, the ICO 9 is oscillated to generate a sampling clock for the A / D converter and a 1 / n clock for data reproduction.

  Here, the second offset correction unit 102 will be described.

  The offset correction has an important meaning for the PLL unit 10. If there is an offset in the input signal, the phase error signal is not correctly output and the worst lock occurs.

  Further, since it is impossible to detect a synchronization signal used in a wide capture described later, it is impossible to lock the frequency. In order to eliminate the DC offset as much as possible, the second offset correction unit 102 is necessary.

  The second offset correction unit 102 is also called duty feedback (DFB). The integral signal that is the output of the IIR filter is subtracted from the output of the D / A converter, and is output to the demodulated signal processing unit 11 and the phase comparator 104 in the next stage. The signal input to the A / D converter is offset-corrected by the second offset correction unit 102 so that the DSV (Digital Sum Value) becomes zero.

  The phase comparator 104 multiplies the output of the A / D converter 8 by multiplying the sign bit delayed by 1 clock and the data without the sign bit, and the result of multiplying the code bit by the data without the sign bit delayed by 1 clock. Can be expressed as an amplitude error (see FIG. 2).

  Next, wide capture will be described.

  When the frequency of the clock component included in the reproduction signal is significantly different from the frequency of the reproduction clock generated by the PLL, phase synchronization cannot be pulled in (cannot be locked). Or pseudo-lock to a different frequency.

  In order to avoid this, the recovered clock generated by the PLL by the wide capture is brought close to the frequency of the clock component of the recovered signal and pulled to the frequency within the predetermined capture range (frequency lock), and then phase locked. I can do it.

  The first wide capture 1030a and the second wide capture 1030b detect the width or period of the synchronization signal, count whether the reproduction clock is earlier or later than the reproduction data, and calculate the frequency error in the next stage. This is output to the frequency error output unit 1031 and the recovered clock is frequency-locked to the recovered signal.

  The third wide capture 1030c compares the wobble clock serving as the reference signal with the reproduction clock, counts the frequency error, outputs the frequency error to the frequency error output unit 1031 at the next stage, and uses the reproduction clock as a reproduction signal. Lock it.

  The third wide capture can be applied to a disc having a guide groove (Wable), but cannot be applied to a disc having no guide groove (Wobble). The wobble clock shown here is a clock obtained by dividing the wobble period written in advance on the disk.

  The frequency error output unit 1031 outputs a binary value indicating whether the frequency of the ICO is faster or slower than the clock of the reproduction data to the loop filter (binary control), or according to the detected frequency error. It is possible to select whether to output a multi-value considering the accuracy to the loop filter (multi-value control).

  The first wide capture 1030a is a method for detecting a synchronization pattern as shown in the conventional wide capture method of Patent Document 1 described above. In the conventional example of Patent Document 1 described above, the synchronization pattern width is counted with a high-frequency fixed clock, but it cannot cope with high-speed and CAV.

  This circuit counts the synchronization pattern with the recovered clock and outputs a frequency error. This frequency error signal controls the ICO 9 via the loop filter unit 106 and the D / A converter 107.

  In order to improve the accuracy, the second wide capture 1030b counts the synchronization pattern period and outputs the frequency error to the loop filter with high accuracy. A frequency error is output in accordance with the accuracy of the frequency error, and the frequency can be pulled in at a high speed within a range of 0.1 to 1% depending on the set value. Further, the gain ratio can be switched between the first wide capture 1030a and the second wide capture 1030b, and the drawing can be performed at a higher speed.

  The sign bit (binarized signal) DC-corrected by the second offset correction unit 102 after AD is input to the first wide capture 1030a and the second wide capture 1030b. The synchronization pattern and period included in this signal are detected.

  In the case of CD, the rising edge is a synchronous pattern from 11T + 11T pattern falling edge or rising edge once in 588T.

  In the case of DVD, the synchronization pattern 14T + 4T appears once in 1488T. When the interval from the rising edge to the falling edge, or from the falling edge to the rising edge is 14T, it is a synchronous pattern.

  By detecting these patterns and measuring the length of the synchronization pattern and the period of the synchronization pattern, the frequency error can be detected. When this pattern is detected, it is determined whether or not the frequencies match each time the number of times of reproduction data edge count (interval period) is reached.

  The third wide capture 1030c shown in FIG. 1 compares the frequency of the regenerated clock generated by the PLL with the wobble clock or fixed clock output from the reference wobble processing unit, and compares the regenerated clock frequency with the reference clock frequency. To match (frequency lock).

(Embodiment 2)
<Configuration of wide capture circuit>
The configuration of the wide capture circuit according to the second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the wide capture circuit according to the second embodiment of the present invention.

  In FIG. 3, the difference from the first embodiment is that the output of the demodulator 112 that performs PRML processing, error correction, etc. on the code bit 115 and demodulates it into a highly reliable binarized signal and the same delay as the demodulator time The delay circuit 113 having time is switched by the switch 114 and input to the wide capture.

  The delay circuit 113 is configured by a shift register, for example, by matching the number of flip-flops with the demodulator. By matching the delay time in this way, when the demodulator and the delay circuit are switched, there is no contradiction in the reproduced data string, and the PLL operates stably. After detecting SYNC in the second SYNC synchronous wide capture, the counter detects the SYNC cycle. Therefore, malfunction of the count value is prevented when the changeover switch 114 is switched.

  After selecting the delay circuit 113 output and locking the PLL, the demodulator is operated stably, and then the demodulator 112 output is selected, and the first and second SYNC synchronous wide capture provides high quality reproduction data. SYNC width and SYNC cycle can be detected.

  In particular, it is possible to input a code bit 115, which is a good binarized signal after error correction processing, to a SYNC wide capture for a disk with a very bad reproduction signal, and control so that the lock is not released. Reference numeral 1033 denotes a frequency lock determination unit, and 1034 denotes a phase error / frequency error switch switching unit.

  Although not shown, the binarized signal output from the DFB (offset correction unit) 102 may be input to the 114 switch without a delay circuit.

  In this case, when the switch 114 is switched, there is a mechanism for holding the recovered clock without checking the SYNC width and the SYNC period for a certain period, so that no malfunction occurs at the time of switching.

<Wide capture sequence using synchronization pattern>
Next, a wide capture sequence using a synchronization pattern by the wide capture circuit according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a wide capture sequence using a synchronization pattern by the wide capture circuit according to the second embodiment of the present invention.

  First, coarse control of the reproduction clock frequency is performed in the first wide capture, detailed control is performed in the second wide capture, the reproduction clock is drawn into the phase lock range, and the reproduction clock is phase-locked to the reproduction data.

  It has a lock-in function and a lock-out function to increase the reliability of frequency lock determination.

  When the first wide capture SWC1 detects the synchronization pattern width the number of times set by the number of lock-ins, the lock-in is performed. After the SWC1 lock-in, the transition is made to the second wide capture SWC2, and the period of the synchronization pattern is detected. Lock-in is performed when the synchronization pattern cycle is detected the number of times set by the lock-in count. After SWC2 lock-in, the frequency error output becomes 0, and the phase shifts from the phase comparator to the phase system in which the phase error is output to the loop filter.

  Lockout occurs when the synchronization pattern period is detected for the number of times set by the number of lockouts. If the SLOCK indicating whether or not the synchronization pattern is taken in the demodulated data after error correction does not fall to Low, the phase system is not switched to the frequency system. If SLOCK is High, it can be determined that demodulation is performed normally. Even if the quality of the binarized signal input to the wide capture is poor, if it is saved by PRML or the like, the phase lock is not intentionally removed. This is because once the phase lock is released, it takes several sync frames until the phase shifts to the phase lock again.

<First and Second Wide Capture Operations Using Binary Control Synchronization Pattern>
Next, a wide capture operation in the case where the frequency error output unit 1031 of the wide capture circuit according to Embodiment 2 of the present invention is binary control will be described with reference to FIGS. FIG. 5 is a flowchart showing the operation of the first wide capture SWC1 of binary control using the DVD-ROM synchronization pattern of the wide capture circuit according to the second embodiment of the present invention, and FIG. 6 shows the second embodiment of the present invention. FIG. 7 is a flowchart showing the operation of the second wide capture SWC2 of binary control using the DVD-ROM synchronization pattern of the wide capture circuit, and FIG. 7 shows the first for each medium of the wide capture circuit according to the second embodiment of the present invention. FIG. 8 is a diagram showing the detection accuracy and interval period of the wide capture SWC1 of FIG. 8. FIG. 8 is a diagram showing the detection accuracy of the second wide capture SWC2 for each medium of the wide capture circuit according to Embodiment 2 of the present invention. When the first and second wide captures of the wide capture circuit according to the second embodiment of the present invention are in binary control, Of a graph showing the calculation result of frequency pull-response. In FIGS. 9A to 9C, the horizontal axis indicates the absolute time, and the vertical axis indicates the recovered clock frequency. In FIGS. 9D to 9F, the horizontal axis indicates the number of samplings in the loop filter operation clock, and the vertical axis indicates the reproduction clock frequency.

(1) First wide capture operation (binary control)
First, the operation of the binary control first wide capture SWC1 using the DVD-ROM synchronization pattern of the wide capture circuit will be described.

  When frequency control is performed, the frequency does not match at first, and therefore, one sync frame time cannot be set accurately. Therefore, a period called an interval period is determined, and synchronization pattern detection is performed in the period. The interval period was determined as the time to reach a certain count value by counting the number of rises and falls of the reproduction signal waveform. To increase the synchronization pattern detection accuracy, the number of intervals is set, and to increase the lock-in accuracy, the number of lock-ins is specified. Also, specify the number of lockouts.

  In the first wide capture sequence flow (binary control), as shown in FIG. 5, first, the length of the synchronization pattern is determined for each number of intervals using the reproduction clock. Since the synchronization pattern is the longest pattern included in the RF signal, the longest pattern of the interval period is stored, and the shortest pattern is assumed to be the synchronization signal (SYNC) during the number of intervals (S100).

  Then, counting is performed with the reproduction clock (S101), and the synchronization pattern width (14T) is detected from the count value (S102). When the synchronization pattern width is not detected in S102, the frequency error is − n is output (S103), and if the reproduction clock is slow, + n is output as a frequency error (S104).

  For the frequency error output in S103 and S104, the numerical value of the frequency error output output after the channel clock is set from the host 13 via the control unit 12. For example, when an integer value of 2 is set and the reproduction clock is fast, -2 is output as a frequency error. When the reproduction clock is slow, +2 is output as a frequency error.

  Then, every time the loop filter operates, the binary value of + n or −n is added by the integrator of the loop filter as a frequency error output.

  This value is input to the loop filter unit 106 via the switch unit 105 and controls the ICO 9 via the D / A converter 107.

  The frequency lock determination unit 1033 determines whether the reproduction clock is fast or slow at every interval.

  If the synchronization pattern width is detected in S102, it is determined that SYNC has been detected (S105), and a transition is made to the second wide capture sequence SWC2 (S106).

  The detection accuracy and interval period of the first wide capture SWC1 for each medium are as shown in FIG. 7, and the reproduction pattern frequency can be roughly controlled by counting the synchronization pattern width with the reproduction clock as in the DVD-ROM.

(2) Second wide capture operation (binary control)
Next, the operation of the second wide capture SWC2 of binary control using the DVD-ROM synchronization pattern will be described.

  As shown in FIG. 6, the synchronization pattern period is counted by the reproduction clock (S200), and if the period is detected within a predetermined range for the designated number of times, the frequency system is shifted to the phase system (S201 to S204).

  The synchronization pattern period of the DVD-ROM is 1488T. If it is in the range of 1488 ± 8, a frequency error of 0 is output to the loop filter (S202).

  In this case, frequency control can be performed with an accuracy of 8/1488 = about 0.5%. In the case of a DVD-ROM, the detection accuracy can be changed by setting m of 1488 ± m from a control microcomputer not shown.

  The numerical value of the frequency error output output after the channel clock is set from the host 13 via the control unit 12. For example, when an integer value of 2 is set, -2 is output when the reproduction clock is fast (S205), and +2 is output when the reproduction clock is slow (S206).

  This value is input to the loop filter unit 106 via the switch unit 105 and controls the ICO 9 via the D / A converter 107. It is determined whether the reproduction clock is fast or slow every SYNC appearance period.

  Every time the loop filter operates, two values of + n or -n are added by the integrator of the loop filter as a frequency error output. When the reproduction clock detects the synchronization pattern period, it is determined that the SYNC period is detected, and the phase shifts to the phase system.

  Here, the detection accuracy of the second wide capture SWC2 for each medium is as shown in FIG. 8, and the detection accuracy can be varied according to the synchronization pattern period.

  In FIG. 8, the pull-in of 1%, 0.5%, and 0.25% is summarized. As in the DVD-ROM, the synchronization pattern period is counted by the reproduction clock, and the reproduction clock frequency can be finely controlled. The frequency detection accuracy can be selected according to the phase system capture range.

  Further, the calculation result of the frequency pull-in response when the first and second wide captures are binary control is as shown in FIG. 9, and in FIGS. 9A to 9C, the horizontal axis indicates the absolute time. In FIGS. 9D to 9F, the horizontal axis indicates the number of samplings in the loop filter operation clock, and the vertical axis indicates the recovered clock frequency.

  In FIG. 9, the frequency error output value is set to ± 1, and the loop filter gain is varied in three ways. The frequency pulling changes linearly, but if the loop filter gain is increased too much, the frequency pulling cannot be performed. Although not shown, even if the loop filter gain is too low, the phase may not be locked depending on the setting of the number of intervals.

  For this reason, the loop filter gain, the frequency error output value, the number of intervals, and the like are set to optimum values by calculation and actual machine consideration, and the phase is locked.

  Although it is necessary to perform frequency pull-in as fast as possible, fast binary control with a slow frequency has its limitations.

  Specifically, an example of the specification of the capture time for wide capture will be described.

  An example of the wide capture specification in the case of DVD-ROM CAV playback can be calculated as follows.

  The average rotation waiting time for address search is determined by the inner circumference length / linear velocity / 2, and is 21.5 ms from an inner radius of 24 mm and a linear velocity of 3.49 m / s. In the case of CAV, the average rotation waiting time for searching the innermost and outermost addresses is the same.

  If the pick movement time is not taken into consideration, the wide capture frequency pull-in time specification that satisfies 21.5 ms (= inner peripheral length / linear velocity / 2) within DVD 1 × speed playback is obtained. When this specification is converted into a 10% frequency pull-in time specification, 0.86 ms (= 21.5 ms / 25) is obtained.

  In the wide capture pull-in time for detecting the sync signal width and the sync signal period when the frequency is changed by 10% by the binarization control shown in FIG. 9, if the loop gain is increased, pull-in cannot be performed, so this specification cannot be satisfied. .

  As means for improving this, multi-value control is provided for outputting a frequency error and a frequency error corresponding to accuracy to the loop filter.

<First and Second Wide Capture Operations Using Multilevel Control Synchronization Pattern>
Next, a wide capture operation in the case where the frequency error output unit 1031 of the wide capture circuit according to Embodiment 2 of the present invention is multi-level control will be described with reference to FIGS. FIG. 10 is a flowchart showing the operation of the first wide capture SWC1 of multi-value control using the DVD-ROM synchronization pattern of the wide capture circuit according to the second embodiment of the present invention, and FIG. 11 shows the second embodiment of the present invention. FIG. 12 is a diagram showing a frequency error output table of the first wide capture SWC1 for detecting the DVD-ROM synchronization pattern width of the wide capture circuit, and FIG. 12 shows the DVD-ROM synchronization pattern of the wide capture circuit according to the second embodiment of the present invention. FIG. 13 is a flowchart showing the operation of the second wide capture SWC2 of the multi-value control used, and FIG. 13 shows the frequency error of the second wide capture SWC2 of the DVD-ROM synchronization pattern period detection of the wide capture circuit according to the second embodiment of the present invention. FIG. 14 shows an output table, and FIG. 14 shows a wide according to the second embodiment of the present invention. First and second wide capture Yapucha circuit is a diagram showing a calculation result of frequency pull response when the multi-value control.

(1) First wide capture operation (multi-value control)
The frequency error output in the first wide capture having a large frequency error and low accuracy may be set to a relatively large value because of coarse control. However, after the transition to the second wide capture, if the value is not set to a relatively small value, an overshoot occurs, so that a value corresponding to the frequency error is automatically output to the loop filter.

  As shown in FIG. 10, the operation of the first wide capture SWC1 of the multi-value control using the DVD-ROM synchronization pattern is different from the binary control shown in FIG. 5 with respect to the synchronization pattern width 14T of the DVD-ROM. The difference is that the difference is detected, the difference is multiplied by the gain, and output to the loop filter (S301 to S303).

  In addition, if there is too much frequency error, the transition to the second wide capture may not be possible, so a limiter is provided.

  FIG. 11 shows a first wide capture SWC1 frequency error output table for DVD-ROM synchronization pattern width detection. FIG. 11 shows how much the pattern width, which is regarded as SYNC, is different from 14T.

  For example, if 15T, the frequency error is + 7% (= (15T-14T) / 14T * 100), and if 16T, the frequency error is + 14% (= (16T-14T) / 14T * 100). In FIG. 11, the limit setting is 21 or less, and the gain setting is 1/2 or 2 times. If the frequency error is output to the loop filter in accordance with the difference from 14T, the frequency pull-in can be performed much faster than the binary control in the case of coarse control.

(2) Second wide capture operation (multi-value control)
Next, the operation of the second wide capture SWC2 of multi-value control using the DVD-ROM synchronization pattern will be described.

  As shown in FIG. 12, the difference from the binary control shown in FIG. 6 is that a difference from the synchronous pattern period 1488T of the DVD-ROM is detected, the difference is multiplied by a gain, and output to the loop filter. (S401 to S403). In addition, if there is too much frequency error, it may not be possible to transition to the phase system, so a limiter is provided.

  FIG. 13 shows a second wide capture SWC2 frequency error output table for DVD-ROM synchronization pattern period detection. FIG. 13 shows how much difference the synchronization pattern period is from 1488T. In the case of 1488 ± 8T (accuracy 0.5%), the frequency error is zero.

  For example, if 1504 (= 1488 + 16), the frequency error is + 1%, and if 1512T (= 1488 + 24), the frequency error is + 2%. A frequency error corresponding to the accuracy is detected and output.

  Limit value can be set in consideration of frequency overshoot. The limit setting is 5 or less, and the gain setting is ½ times or 2 times. Since we want to pull in with high accuracy with the second wide capture after pulling in with the first wide capture, the limit value of the second wide capture is set to a smaller value according to the accuracy than the limit value of the first wide capture. To do. If a frequency error is output to the loop filter in accordance with the difference from 1488T, in the case of fine control, it is possible to perform frequency pull-in more accurately than binary control.

  Further, the calculation result of the frequency pull-in response when the first and second wide captures are multilevel control is as shown in FIG. 14, and the loop filter gain can be made higher than that of the binary control, and the high speed Because the frequency can be drawn with high accuracy, it is possible to quickly shift to the phase system.

  The first wide capture can be set to multi-value control, and the second wide capture can be set to binary control. When the frequency changes greatly, the control is performed by multi-value control, the frequency is drawn at high speed, and in the case of the second wide capture with high accuracy, the gain may be set to an appropriate value and may be pulled in by binary control. A dotted line portion in FIG. 14 is a frequency pull-in response for binarizing the second wide capture.

<Third wide capture (wobble synchronization) operation>
The third wide capture 1030c shown in FIG. 1 compares the wobble clock output from the reference wobble processing unit with the reproduction clock frequency generated by the PLL, and passes the frequency error output unit 1031 to the loop filter. Output frequency error. When operating at high speed, 1 / n clocks may be compared to reduce power consumption. Control is performed so that the channel clock frequency coincides with the wobble clock that is the reference frequency, and the reproduction clock that is the PLL output is locked to the wobble clock at a high speed.

  As shown in FIG. 1, the third wide capture 1030 c is controlled by the switch unit 105 that selects the frequency loop and the phase loop so that the frequency error is output to the loop filter unit 106. After drawing the frequency, the switch unit 105 outputs not the frequency error but the phase error to the loop filter unit 106 by a signal (frequency lock signal) indicating that the frequency has been drawn. Transition from the frequency system to the phase system. After locking the frequency, the phase comparator 104 locks the phase.

  Here, an outline of the third wide capture will be described with reference to FIGS. 15 and 16. FIG. 15 is an explanatory diagram for explaining an outline of the third wide capture of the wide capture circuit according to the second embodiment of the present invention, and FIG. 16 is a third diagram of the wide capture circuit according to the second embodiment of the present invention. It is a figure which shows the frequency error output table of a wide capture.

  As shown in FIG. 15, in the third wide capture, a difference between a reproduction clock counter and a counter using a wobble clock as a reference clock is output as a frequency error.

  A clock obtained by dividing the wobble clock can be used as a reference clock. In the case of accuracy of 1% increments, for example, when using a wobble clock, when using a wobble clock divided by 1/4, n = 4, so m = 25 (= 100/4) is set. When using a wobble clock that does not divide, since n = 1, m = 100 is set.

  The reference clock counter counts up to a value of m, compares the period width (count number) of m with the reproduction clock period (count number), and evaluates whether the frequency of the reproduction clock is faster or slower than the reference clock. . The difference between the values of the reproduction clock counter is output as a frequency error. When it is within ± 1%, the frequency error output is 0 output.

  When the recovered clock is fast, a negative value is output as the frequency error. When the reproduction clock is slow, a positive value is output.

  The frequency error output unit 1031 can select binary control or multi-value control.

  In the case of binary control, a fixed value of + n or -n is output.

  In the case of multi-value control, a value corresponding to the frequency error is output.

  As shown in FIG. 16, when the accuracy is set to 1%, when the frequency error is 0 to ± 1%, the frequency error output is 0, and when the frequency difference is 1 to 2%, the frequency error output is ± When 1 is output and the frequency difference is 2 to 3%, the frequency error output is ± 2. Limit setting and gain setting are provided, and the pull-in time can be varied.

  In order to increase the reliability, the lock-in function assumes that the frequency error is within ± 1% if the frequency lock is continued for a predetermined number of times during frequency evaluation. Further, if the frequency error ± 1% does not continue for a predetermined number of times after locking by the lockout function, it is considered that the lockout has occurred.

  The lock accuracy can be varied. For accuracy of 1%, the count number of the reproduction clock is set to 100 counts. When the accuracy is 0.5%, it can be varied by setting the count number of the reproduction clock to 200 counts. When the reproduction 200 count reference is set, if the deviation is +1 from the reference clock, the reproduction clock is shifted by 0.5% compared to the reference clock.

  The control (microcomputer) unit 12 controls the switch unit 105 to determine which wide capture is used for the frequency pull-in. The first and second wide captures using the synchronization signal are used in the case of an optical disc medium (DVD-ROM, CD-ROM, etc.) in which no wobble exists. It can be used not only for CLV but also for a reproduction method in which the speed of the reproduction clock increases from the inner circumference to the outer circumference, such as CAV reproduction.

  When the recovered clock from the inner periphery to the outer periphery is constant in CLV regeneration, the frequency of the recovered clock is pulled in by inputting a fixed reference clock in advance instead of the third wide capture FIG. 15 wobble clock signal input. Can be. Even in CAV reproduction, when the address is known in advance, a clock obtained by dividing or multiplying the fixed reference clock can be used.

(Embodiment 3)
<Configuration and Operation of Optical Disc Device Including Wide Capture Circuit>
The configuration and operation of the optical disc apparatus including the wide capture circuit according to the third embodiment of the present invention will be described with reference to FIG. FIG. 17 is a block diagram showing the configuration of an optical disc apparatus including a wide capture circuit according to Embodiment 3 of the present invention.

  In FIG. 17, the optical disc apparatus including the wide capture circuit includes a fourth wide capture unit 1030d, a second frequency error output unit 1031a, and an integrator 106a in addition to the configuration shown in FIG.

  In this embodiment, the frequency error output interval is shorter than in the third wide capture using the wobble clock in the second embodiment. Also, by adding the frequency error of the fourth wide capture to the loop filter output integrating the phase error, a special ID such as writing a user data after reading a pre-written ID such as DVD-RAM media. It corresponds to various formats.

  In the second embodiment, in the third wide capture, the accuracy of 1% can be obtained with 100 counts, but the frequency error output is 0 within ± 1%. Therefore, when the clock frequency of the DVD-RAM PID and the user data is shifted by less than 1%, for example, 0.8%, reading of the PID may fail.

  If the phase system capture range is wide, it can be pulled in at high speed if the frequency shift is about 1%. However, in the case of a digital type PLL having a narrow capture range, it may be difficult to pull in at high speed.

  Normally, user data is written with wobble clock synchronization. However, older types of drives have disks written with fixed clock synchronization. Therefore, the clock frequencies of the data in the PID part and the user data part are different by about 0.5% to 2%.

  The wobble synchronization period immediately before the PID is 35B (560T). In the third wide capture, the frequency error is updated every 100 counts in the case of 1% accuracy. Therefore, the frequency error is updated only 5 times in the wobble synchronization period immediately before the PID, and the frequency error is output below 1%. First, it becomes 0 output.

  In a short period (560T), it is necessary to match the reproduction clock to the wobble clock and read the PID. In order to speed up the frequency acquisition, a separate integrator is provided without using a loop filter, and the output value is directly output to the D / A. The accuracy is reduced by 12.5% (= 1 / 8T), and the frequency error is updated and output every short period (8T).

  The second frequency error output unit 1031a can select multi-value output or binary output as the frequency error, and control the gain.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third embodiments, the DVD disk has been described as an example. However, the scope of application of the present invention is not limited to devices such as DVD-RAM, DVD ± R / RW, and DVD-ROM. The same PLL method can be adopted in recording / reproducing apparatuses such as HD DVDs and Blu-ray discs.

  The present invention relates to a wide capture circuit of an apparatus for reproducing a signal from an optical disc, and more particularly, using a phase-locked loop such as a PLL (Phase-Locked Loop) to extract a synchronized clock signal and a multi-valued signal, and PRML ( (Partial Response Maximum Likelihood) circuit is applicable to an apparatus capable of reproducing a signal.

1 is a configuration diagram showing a configuration of an optical disc device including a wide capture circuit according to a first embodiment of the present invention. It is explanatory drawing for demonstrating the operation | movement of the reproduction | regeneration processing of the optical disk apparatus containing the wide capture circuit based on Embodiment 1 of this invention. It is a block diagram which shows the structure of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the sequence of the wide capture using the synchronous pattern by the wide capture circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of 1st wide capture SWC1 of binary control using the DVD-ROM synchronous pattern of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of 2nd wide capture SWC2 of binary control using the DVD-ROM synchronous pattern of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the detection accuracy and interval period of 1st wide capture SWC1 for every medium of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the detection accuracy of 2nd wide capture SWC2 for every medium of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the calculation result of the frequency pull-in response in case the 1st and 2nd wide capture of the wide capture circuit which concerns on Embodiment 2 of this invention is binary control. It is a flowchart which shows operation | movement of 1st wide capture SWC1 of multi-value control using the DVD-ROM synchronous pattern of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the frequency error output table of 1st wide capture SWC1 of DVD-ROM synchronous pattern width detection of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a flowchart which shows operation | movement of 2nd wide capture SWC2 of multi-value control using the DVD-ROM synchronous pattern of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the frequency error output table of 2nd wide capture SWC2 of the DVD-ROM synchronous pattern period detection of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the calculation result of the frequency pull-in response in case the 1st and 2nd wide capture of the wide capture circuit which concerns on Embodiment 2 of this invention is multi-value control. It is explanatory drawing for demonstrating the outline of the 3rd wide capture of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a figure which shows the frequency error output table of the 3rd wide capture of the wide capture circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the optical disk apparatus containing the wide capture circuit based on Embodiment 3 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Spindle motor, 3 ... Optical head, 4 ... I / V converter, 5 ... Wobble process part, 6 ... RF data process part, 7 ... 1st offset correction part, 8 ... A / D conversion 9 ... Current controlled oscillator (ICO), 10 ... PLL unit operating with 1 / n clock, 11 ... Demodulated signal processor, 12 ... Control unit, 13 ... Host computer, 51 ... Crystal oscillator (X'tal) ), 52... 1 / n frequency division unit, 61... Auto gain control (AGC) unit, 62... High-pass filter (HPF) unit, 63. Offset correction unit, 1030... Wide capture unit, 1030a... First wide capture (SYNC width detection wide capture), 1030b... Second wide capture (SYNC cycle) Detection wide capture), 1030c... Third wide capture (wobble or X'tal synchronous wide capture), 1030d... Fourth wide capture, 1031, 1031a. ... Phase comparator, 105 ... Switch unit, 106 ... Loop filter unit, 107 ... D / A converter.

Claims (10)

A wide capture circuit in an optical disc apparatus for reproducing information on an optical disc on which a synchronization signal and digital information in which a synchronization pattern configured with a predetermined synchronization pattern length is present at a constant cycle interval is recorded,
The reproduction signal reproduced from the optical disc detects the synchronization pattern length of the code bit sampled based on the reproduction clock, and the reproduction signal has the oscillation frequency of the oscillation unit whose oscillation frequency changes according to the output value of the loop filter. A first frequency pull-in unit that outputs a frequency error from the clock frequency;
A second frequency pull-in unit that detects a period in which the synchronization pattern of the code bits exists and outputs a frequency error between an oscillation frequency of the oscillation unit and a reproduction clock frequency of the reproduction signal;
Based on the frequency error output from the first frequency pull-in unit and the second frequency pull-in unit, binary information indicating whether the reproduction clock frequency is slow or fast, or how late the reproduction clock frequency is A first frequency error output unit that selects and outputs multi-value information indicating whether it is fast;
A phase comparator that compares the phase of the recovered clock and the recovered signal and outputs a phase error;
A wide capture circuit comprising: a switch unit that switches between an output of the first frequency error output unit and an output of the phase comparison unit and outputs the same to the loop filter. The wide capture circuit of claim 1,
The first frequency pull-in unit includes a first frequency detection unit that roughly detects a frequency error accuracy for detecting a synchronization pattern length, and the first frequency pull-in unit completes the frequency pull-in, A first frequency determination unit that outputs a first frequency matching signal indicating that the oscillation frequency of the oscillation unit matches the reproduction clock frequency of the reproduction signal within the accuracy of the frequency pull-in unit of After completion of the frequency pull-in by the first frequency pull-in unit, a second frequency pull-in is started by the first frequency match signal,
The second frequency pull-in unit has a second frequency detection unit that detects frequency error accuracy in detail for detecting the synchronization pattern period, and the second frequency pull-in unit completes the second frequency pull-in. A second frequency determination unit that outputs a second frequency matching signal indicating that the oscillation frequency of the oscillation unit matches the reproduction clock frequency of the reproduction signal;
The switch unit is controlled by the second frequency coincidence signal and outputs a frequency error when performing the frequency pull-in. After the frequency pull-in is completed and the frequency coincides, the phase error output is output to the loop. A wide capture circuit that outputs to a filter. The wide capture circuit according to claim 2,
When the first frequency acquisition unit and the second frequency acquisition unit complete the second frequency acquisition and the first frequency match signal indicates that the frequency is not acquired, the first frequency acquisition unit and the second frequency acquisition unit 1 frequency acquisition is started again, or the first frequency acquisition is performed, and the frequency matching signal of the second frequency determination unit is the oscillation frequency of the oscillation unit and the reproduction clock frequency of the reproduction signal. The wide capture circuit is characterized in that the second frequency pull-in is started again when it indicates that the two do not match. The wide capture circuit according to claim 3,
The optical disc is recorded with data modulated by a predetermined modulation rule,
A demodulation unit that determines whether demodulation is performed normally by a demodulation unit that demodulates the modulated data, and includes a demodulation lock output unit that outputs a lock signal indicating whether demodulation is performed normally,
After completing the first frequency pull-in and the second frequency pull-in, the switch unit outputs a phase error output to the loop filter, and after the demodulation is normally performed, from the demodulation lock output unit When the lock signal indicates that the demodulation is not performed normally, the output is switched to the frequency error output, and the lock signal from the demodulation lock output unit indicates that the demodulation is performed normally. Is a wide capture circuit that outputs the phase error even when the first frequency determination unit or the second frequency determination unit indicates that the frequencies do not match. A wobble signal processing unit that detects a wobble signal that is a periodic meandering signal from an optical disc having a recording guide groove meandering periodically and outputs a clock synchronized with the wobble signal. A wide capture circuit in an optical disc apparatus for recording or reproducing,
The reproduction signal reproduced from the optical disc detects the synchronization pattern length of the code bit sampled based on the reproduction clock, and the reproduction signal has the oscillation frequency of the oscillation unit whose oscillation frequency changes according to the output value of the loop filter. A first frequency pull-in unit that outputs a frequency error from the clock frequency;
A second frequency pull-in unit that detects a period in which the synchronization pattern of the code bits exists and outputs a frequency error between an oscillation frequency of the oscillation unit and a reproduction clock frequency of the reproduction signal;
A third frequency pulling unit that outputs a frequency error between the wobble clock of the wobble signal processing unit and the reproduction clock frequency of the reproduction signal;
Binary information indicating whether the reproduction clock frequency is slow or fast based on the frequency error output from the first frequency acquisition unit, the second frequency acquisition unit, and the third frequency acquisition unit, or the reproduction clock A first frequency error output unit that selects and outputs multi-value information indicating how slow or fast the frequency is;
A phase comparator that compares the phase of the recovered clock and the recovered signal and outputs a phase error;
A wide capture circuit comprising: a switch unit that switches between an output of the frequency error output unit and an output of the phase comparison unit and outputs the same to the loop filter. The wide capture circuit according to claim 5,
A fourth frequency pull-in unit that outputs a frequency error between the wobble clock frequency of the wobble signal processing unit and the reproduction clock frequency of the reproduction signal to the loop filter;
The fourth frequency pull-in unit is
The frequency error detection interval is shorter than that of the third frequency pull-in unit,
Based on the frequency error output from the fourth frequency pull-in unit, binary information indicating whether the reproduction clock frequency is slower or faster than the wobble clock, or how much the reproduction clock frequency is slower or faster. A second frequency error output unit that selects and outputs multi-value information indicating
An integrator for integrating the output of the second frequency error output unit;
A switch / adder for switching the output of the loop filter and the output of the integrator, or adding the output of the integrator to the loop filter;
The output of the switching / adding unit controls the oscillating unit. The wide capture circuit according to claim 6.
A wide capture circuit comprising an input signal switching unit that switches between the wobble clock and the reproduction signal as an input signal to the fourth frequency pulling unit. The wide capture circuit according to any one of claims 5 to 7,
The first frequency error output unit and the second frequency error output unit are:
A wide adjustment unit having a gain adjustment unit that performs gain adjustment of N times or 1 / N times (N: positive integer) when outputting binary information indicating whether the reproduction clock frequency is slow or fast. Capture circuit. The wide capture circuit according to any one of claims 5 to 7,
The first frequency error output unit and the second frequency error output unit are:
A gain that adjusts the gain by N times or 1 / N times (N: positive integer) according to the frequency error accuracy when outputting multi-level information indicating how slow or fast the recovered clock frequency is An adjustment unit;
A wide capture circuit, comprising: a limiter limiting unit that limits output of the multilevel information when the frequency error is large. The wide capture circuit according to claim 2,
2. The wide capture circuit according to claim 1, wherein the second frequency detection unit includes an accuracy varying unit that varies an entrainment accuracy according to a synchronization pattern period.

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