JP2007109349A - Digital information recording or reproducing apparatus and digital phase locked loop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve stability of pull-in time and pull-in operation of a PLL at the head of an RUB (recording unit block). <P>SOLUTION: This apparatus includes a zero-cross detection means, a period counter which starts operation at the pass-through timing of the zero-cross detection means and outputs a counting value, and a phase error detector for acquisition which predicts zero-cross timing of a reproduction signal from a pass-through direction information output from the zero-cross detection means and the counting value and outputs a primary phase error. The zero-cross detection means detects the zero-cross point of the rising or falling edge of a specific pattern included in a preamble area, makes a period counter of a prescribed period from the detected zero-cross point operate, predicts the zero-cross point predicted from a specific pattern in the preamble area, and outputs a phase error for acquisition. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital information reproducing apparatus and a digital PLL circuit for reproducing original digital information from an analog signal reproduced from a recording medium.

  When recording original digital information on an optical disk or magnetic disk medium, a run length limit code (hereinafter referred to as RLL code) is often used. By using the RLL code, it is possible to detect the phase error information contained in the reproduction signal at a predetermined frequency and generate a reproduction clock. This is called so-called self-clock reproduction. In order to perform this self-clock recovery, a PLL (phase locked loop) circuit is usually used. In recent years, PRML signal processing combining partial response equalization and Viterbi decoding has been used as a method for reproducing original digital information recorded on a medium. Partial response equalization can improve S / N compared to conventional Nyquist equalization by giving known intersymbol interference to a reproduction signal. Viterbi decoding is effective when there is a correlation before and after the code, and a combination with partial response equalization is effective. A read channel that combines the above-described self-clock reproduction and PRML signal processing has been developed.

  As shown in FIG. 1, the read channel has a waveform equalization circuit 1 having an equalizing function with a low-pass filter, an A / D converter 2, an FIR filter 3, a Viterbi decoder 4, and a phase error from the quantized reproduction signal. It comprises a phase comparator 5 for detection, an LPFLF 6 for low-pass processing of phase errors, a D / A converter (DAC) 7 and a voltage controlled oscillator (VCO) 8. In the conventional example of FIG. 1, a method for detecting a phase error from the output signal of the A / D converter 2 has been described. However, a method for obtaining a phase error from the determination result of the FIR filter 3 or the Viterbi decoder 4 is also used.

  In such a read channel, a multistage digital circuit exists from the A / D converter 2 to the control voltage of the VCO 8, and the circuit delay is large, so that the gain of the loop filter cannot be increased. Therefore, there is a problem that the capture range is narrow and it takes a long time to pull in the initial phase.

  In particular, a rewritable optical disk (for example, a rewritable optical disk such as a DVD-RAM) places importance on random access performance, and is a standard that can be recorded in a predetermined recording area without the need for continuous recording and additional recording from the inner periphery to the outer periphery. It has become. Since a recording area and an unrecorded area exist on the medium, a single frequency preamble pattern (VFO) is provided for PLL phase acquisition according to the standard. The PLL increases the gain in the VFO region and decreases the gain in the data region, and switches the gain so that the initial PLL phase pull-in can be realized as soon as possible. Furthermore, it is also known to use a phase comparison circuit system that uses a single frequency preamble pattern and that uses a phase error detection method different from that of a normal recording area.

Japanese Patent Laid-Open No. 8-315517 (Patent Document 1) has a zero phase start circuit and a signal pattern output means for outputting an expected value data series according to PR equalization, and is expected to be a reproduction signal in the preamble region. The phase comparison with the signal pattern is performed, and the initial phase pull-in is realized at first. In Japanese Patent No. 3485822 (Patent Document 2), a zero-cross point of a reproduction signal is detected, a counter having a period set by a specific pattern in the VFO region is operated from the detection position, and phase error information is predicted from the count value. The initial phase pull-in is realized in a short VFO region. Furthermore, if the VFO area is deteriorated due to repeated recording, or if the immediately preceding recording area is unrecorded, the DC component of the reproduction signal varies greatly. The DC component is removed by the low-frequency component suppression circuit so that the phase error can be correctly detected even when the DC fluctuation occurs in the reproduced signal. FIG. 2 is a diagram showing the operation of the acquisition phase comparator in the VFO region disclosed in Japanese Patent No. 3485822 (Patent Document 2). FIG. 2A shows a signal pattern in the VFO pattern region, which is a repetitive pattern of eight cycles of a channel clock (T is a cycle). The cycle counter is operated from the changing point of the signal indicating the acquisition operation start position in FIG. The period counter outputs a counter value as shown in FIG. Data as shown in FIG. 2D is input to the acquisition phase comparator. Specific data is output as a phase error from the count value of the period counter as shown in FIG. Specifically, when the counter value of the period counter is 3, the phase comparator input is directly used as a phase error. When the oscillation frequency of the VCO of the PLL is higher than the frequency of the reproduction signal, a negative phase error signal is output as shown in FIG. The phase error signal passes through the LPF, becomes the control voltage of the VCO, and is controlled to lower the oscillation frequency. Similarly, when the oscillation frequency of the VCO is low, a positive phase error signal is output as shown in FIG. 4, and control is performed to increase the oscillation frequency of the VCO.
JP-A-8-315517 (Formula (2)) Japanese Patent No. 3485822 (FIGS. 1, 3, 4, 5, and 6)

  A rewritable or recordable Blu-Ray disc, a so-called BD-RE disc, or a BD-R disc has a format as shown in FIG. Recording is performed in units of user data of 64 Kbytes. As shown in FIG. 5, the minimum recording unit is called a recording unit block (hereinafter referred to as RUB), and is composed of user data of 64 Kbytes, a predetermined length of RUN-IN, and a predetermined length of RUN-OUT. RUN-IN has a preamble area, and a specific pattern is repeatedly recorded. RUN-OUT has a postamble area, and the same specific pattern is repeatedly recorded. The specific pattern is a pattern of a total of 20 channel clock lengths of 3T / 3T / 2T / 2T / 5T / 5T, and has two recording codes as shown in FIG. 6 depending on the polarity. BD-RE and BD-R are standards that can be recorded at any location on the disc, and recorded RUBs and unrecorded RUBs may exist alternately. When reading user data from a recorded RUB, it is necessary to perform bit synchronization and PLL pull-in operation at the head of the RUB. In other words, PLL pull-in must be started in the preamble area where the specific pattern is recorded. The phase comparator used in the user area has a problem that the pull-in range of the PLL is narrow, and the pull-in of the PLL cannot be completed only by the RUN-IN area having a predetermined length. Further, since the specific pattern is not a single frequency, there is a problem that the acquisition phase comparator disclosed in Patent Document 2 cannot be used. A digital information recording / reproducing apparatus according to the present invention includes a level passage detecting means for detecting an edge of a specific pattern included in a preamble pattern, a period counter, and a phase comparator for acquisition in a preamble area in which a specific pattern not having a single frequency is recorded. In order to improve the PLL pull-in time at the head of the RUB and the stability of the pull-in operation.

  A digital information recording / reproducing apparatus of the present invention is an apparatus for reproducing user data from a recording medium recorded in a predetermined format, and an A / D conversion means for converting a reproduction signal into quantized data at the timing of a reproduction clock; A low-frequency suppression circuit that removes a DC component contained in the quantized data output from the A / D conversion means, a timing at which the output signal of the low-frequency suppression circuit passes through a zero level, and a zero cross timing flag And zero cross detection means for outputting passage direction information, a period counter that starts operation in accordance with the passage timing of the zero cross detection means, counts at a predetermined period and outputs a count value, and the passage output from the zero cross detection means From the direction information and the count value of the period counter, the timing at which the quantized data zero-crosses is determined. An acquisition phase error detector that outputs an initial phase error from the output signal of the low-frequency suppression circuit, a tracking phase error detector that outputs a phase error from the output signal of the low-frequency suppression circuit, and the acquisition Selector means for switching the phase error signal output from the phase error signal output from the initial phase error signal output from the phase error detector for tracking and the phase error signal output from the tracking, and using the phase error of the selector means Reproducing clock extracting means for generating a reproducing clock is provided, the initial phase error signal output from the acquisition phase error detector is used in the head region of the recording unit, and the tracking phase error detector is used in regions other than the specific pattern. The phase of the recovered clock is controlled using the phase error signal output from That.

  Also, the zero cross detection means of the digital information recording / reproducing apparatus of the present invention detects the zero cross point of the rising or falling edge of the specific pattern included in the preamble area, and outputs a zero cross timing flag. A period counter having a predetermined period is operated from the detected zero cross point, the next zero cross point predicted from the specific pattern is predicted, and a phase error for acquisition is output from the predicted zero cross point.

  The digital PLL circuit of the present invention includes an A / D conversion means for converting a reproduction signal obtained from a recording medium into quantized data at the timing of the reproduction clock, and a quantized data output from the A / D conversion means. A low-pass suppression circuit that removes a DC component contained therein; a zero-cross detection unit that detects a timing at which an output signal of the low-pass suppression circuit passes through a zero level; and outputs a zero-cross timing flag and passing direction information; and the zero-cross detection From the period counter that starts the operation in accordance with the passage timing of the means, counts at a predetermined period and outputs a count value, the passing direction information output from the zero cross detection means, and the count value of the period counter, the quantized data Predicts the timing of zero crossing and outputs the initial phase error from the output signal of the low-frequency suppression circuit A phase error detector for acquisition, a phase error detector for tracking that outputs a phase error from the output signal of the low-frequency suppression circuit, an initial phase error signal output from the phase error detector for acquisition, and the phase for tracking A selector means for switching the phase error signal output from the error detector to output a phase error; and a reproduction clock extracting means for generating the reproduction clock using the phase error of the selector means; Uses the initial phase error signal output from the acquisition phase error detector, and controls the phase of the recovered clock using the phase error signal output from the tracking phase error detector in a region other than the specific pattern. It has a configuration.

  Further, the zero cross detection means of the digital PLL circuit of the present invention detects the zero cross point of the rising edge or the falling edge of the specific pattern included in the preamble area, and outputs a zero cross timing flag. A period counter having a predetermined period is operated from the detected zero cross point, the next zero cross point predicted from the specific pattern is predicted, and an acquisition phase error is output from the predicted zero cross point.

  The effect of the present invention is that even when a specific pattern is repeatedly recorded in the preamble area, a digital PLL having a wide pull-in range can be configured, and the pull-in time can be shortened and the PLL pull-in operation can be performed stably. In addition, even if the recording medium has a different preamble area format, switching the acquisition phase comparator enables PLL operation, realizing an inexpensive device that can handle many media without increasing the circuit scale. it can.

(Embodiment 1)
Embodiment 1 of the digital information reproducing apparatus and digital PLL circuit of the present invention will be described. FIG. 7 shows a configuration diagram.

  A reproduction signal is obtained from the optical disk by an optical head. The reproduction signal passes through the preamplifier and is input to the waveform equalization circuit 9 as an RF signal. The waveform of the RF signal is shaped by the waveform equalization circuit 9 by removing noise components and emphasizing a predetermined frequency band. The waveform equalization output signal is quantized by the reproduction clock in the A / D converter 10. The low frequency component contained in the signal is removed from the quantized reproduction signal by the low frequency component suppression circuit 11. The RF signal from which the low frequency component has been removed is input to a process of reproducing the original digital information by PRML and a process of extracting a reproduction clock included in the reproduction signal and obtaining bit synchronization. First, in the PRML signal processing, the signal is input to the FIR filter 12. Adaptive equalization is performed by the FIR filter 12 so as to achieve predetermined partial response equalization. From the predetermined PR equalized reproduction signal, the Viterbi decoder 13 outputs the most likely binary data. The binarized data is demodulated by a modulation / demodulation circuit and then subjected to error correction processing to obtain user data. On the other hand, in the bit synchronization processing, a phase error is detected from the reproduction signal output from the low frequency component suppression circuit 11. In the preamble area of a predetermined length at the beginning of the RUB, PLL pull-in is performed. First, the zero cross detection means 14 detects a predetermined pattern in the preamble. Since the preamble pattern of the BD-R / RE disc is a repetition of 3T / 3T / 2T / 2T / 5T / 5T, 5T / 5T, which is the maximum mark / space combination, is detected. This is because the 5T / 5T reproduction signal amplitude of the maximum mark and space pattern is the largest and is easy to detect. The zero cross detection means 14 outputs a zero cross timing flag to the period counter 15 as a detection result. The cycle counter 15 operates a counter of 20 cycles in accordance with the zero cross timing flag, and outputs the count value to the acquisition phase comparator 16. The reproduction signal output from the low frequency component suppression circuit 11 is input to the acquisition phase comparator 16. The timing at which the next zero cross point is obtained is predicted from the count value input from the period counter 15, and an acquisition phase error signal is obtained from the input reproduction signal and output. The acquisition phase error signal is input to the reproduction clock extraction means 18. The regenerative clock extracting means 18 comprises a selector means 19, an LPF 20, a D / A converter 21 and a VCO 22. When performing a PLL pull-in operation in the preamble region, the acquisition phase error signal is selected by the selector means 19 and input to the LPF 20. After LPF processing, it is input to the D / A converter 21. The D / A converter output becomes the control voltage of the VCO 22 and controls the oscillation frequency of the VCO 22. The recovered clock output from the VCO 22 is input to the A / D converter 10. When the PLL pull-in operation is completed in the preamble region, the tracking phase error signal output from the tracking phase comparator 17 is selected by the selector means 19 and input to the LPF 20. The tracking phase comparator 17 detects the zero cross point of the reproduction signal output from the low-frequency component suppression circuit 11, and obtains and outputs a tracking phase error signal. Based on the reproduction signal quantized by the A / D converter 10 as described above, the phase error signal of the acquisition phase comparator 16 is used in the preamble region at the head of the RUB, and the tracking phase comparison is performed in the user data region. A digital PLL is realized by switching the phase error signal of the device 17 and controlling the oscillation frequency of the reproduction clock of the VCO 22.

  Next, the acquisition operation of the PLL of the digital information recording / reproducing apparatus of the present invention will be described in detail. FIG. 8 shows a timing chart of the acquisition operation. FIG. 8A shows a format layout of the BD-R / RE disc. The RUB includes a RUN-IN having a predetermined length, a physical cluster in which user data is recorded, and a RUN-OUT having a predetermined length, and the RUN-IN includes a preamble area. A repetition of a specific pattern is recorded in the preamble area. FIG. 8B shows a specific pattern (3T / 3T / 2T / 2T / 5T / 5T). When such a specific pattern is reproduced, a reproduction signal shown in FIG. 8C is obtained. The reproduction signal is sampled with the reproduction clock, and the outputs of the low-frequency component suppression circuit 11 are denoted as S0 to S25. Depending on the polarity of the recording code, the reproduced signal shown in FIG. When the acquisition operation start gate signal becomes valid (high level in FIG. 8 (e)), the zero cross detecting means 14 detects the zero cross point of the falling edge of 5T / 5T as shown in FIG. 8 (c), or FIG. The zero cross point of the rising edge of 5T / 5T as shown in (d) is detected, and the zero cross timing flag as shown in FIG. 8 (f) is output. When the zero cross timing flag becomes High level, the cycle counter 15 having a 20-channel clock cycle starts counting in 20 cycles and outputs a count value as shown in FIG. 8G to the acquisition phase comparator 16. The acquisition phase comparator 16 receives the reproduced signals S0 to S25 quantized from the low-frequency component suppression circuit 11. When the count value of the period counter 15 is 0, 5, 8, 11, 13, 15, it can be predicted that a zero cross point is detected. A phase error is obtained from the reproduction signal input at this time. From the passing direction information output from the zero cross detecting means 14, in the case of the reproduced signal as shown in FIG. 8C, the acquisition phase comparator 16 detects the falling edge zero cross point as shown in FIG. When the counter values predicted are 0, 8, and 13, the signs of the input signals S0, S8, and S13 are inverted and output as phase errors. When the counter values at which the rising edge zero-cross point is predicted are 5, 11, and 15, the input signals S5, S11, and S15 are output as phase errors. Similarly, in the case of the reproduced signal as shown in FIG. 8D, the acquisition phase comparator 16 has a counter value for predicting the zero-cross point of the rising edge as shown in FIG. In this case, the input signals S0, S8, and S13 are output as phase errors. When the counter values at which the falling edge zero-cross point is predicted are 5, 11, and 15, the signs of the input signals S5, S11, and S15 are inverted and output as phase errors. By using the phase comparison method as described above, the acquisition phase comparator 16 has an error curve as shown in FIG. 9A when paying attention to the zero cross point of the 2T / 2T falling. On the other hand, the tracking phase comparator 17 has an error curve with a comparison range of ± 180 degrees as shown in FIG. Therefore, the acquisition phase comparator 16 can widen the phase comparison range by predicting the zero cross point from the specific pattern. In the first embodiment of the digital information reproducing apparatus and digital PLL circuit of the present invention, the preamble pattern of the BD-R / RE disc is a repetition of 3T / 3T / 2T / 2T / 5T / 5T, and therefore the zero-cross detection means 14 Is detected as 5T / 5T, which is the largest combination of mark and space, but even when (5 ± 1) T / 5T or 5T / (5 ± 1) T is detected, by outputting a zero cross timing flag, Even when the signal quality deteriorates, the PLL pull-in operation can be reliably performed in the preamble region.

(Embodiment 2)
Embodiment 2 of the digital information recording / reproducing apparatus and digital PLL circuit of the present invention will be described. FIG. 10 shows a configuration diagram. In addition to the first acquisition phase comparison means 23, which comprises a zero cross detection means 14 for pulling in a PLL in a specific pattern in the preamble area for BD-R / RE, a period counter 15, and an acquisition phase comparator 16. Second acquisition phase comparison means 24 for a DVD-RAM or HD-DVD as a recording medium is provided. DVD-RAM and HD-DVD have a VFO area in which a repeating pattern of an 8-channel clock period is recorded at the head of the sector. The second acquisition phase comparison means includes a second zero cross detection means 25 for detecting a zero cross point in the VFO region, a second period counter 26 for counting an 8-channel clock period, and a second period counter 26. It is configured from a second acquisition phase comparator 27 that predicts the timing at which the zero cross point is detected from the input count value, and obtains and outputs an acquisition phase error signal from the input reproduction signal. When reproducing a BD-R / RE, the phase error signal of the first acquisition phase comparison means 23 is used. When reproducing a DVD-RAM or HD-DVD, the second acquisition phase comparison means. By switching to use 24 phase error signals, a stable digital PLL with a short pull-in time can be realized even when the recording medium has a different recording format and the recording pattern of the preamble area is different.

  The digital information recording / reproducing apparatus and the digital phase locked loop circuit according to the present invention have a phase comparator for a specific pattern, and can be used not only as an optical disk apparatus but also as a reproducing apparatus for a magnetic recording medium such as a VTR and a reading apparatus for a magnetic card. Useful.

Block diagram of a conventional digital information recording / reproducing apparatus using the PRML system Time chart of conventional acquisition phase comparator The figure which shows the mode of operation | movement when the oscillation frequency of VCO of the conventional phase comparator for acquisition is high. The figure which shows the mode of operation | movement when the oscillation frequency of VCO of the conventional phase comparator for acquisition is low. BD-R / RE RUB format explanatory diagram Explanatory drawing of the specific pattern recorded on the preamble area of BD-R / RE Configuration diagram of Embodiment 1 of digital information recording / reproducing apparatus and digital PLL circuit of the present invention Time chart of phase detector for acquisition for BD-R / RE of the present invention The figure which shows the phase error detection characteristic of the phase comparator for acquisition for BD-R / RE of this invention Configuration diagram of Embodiment 2 of digital information recording / reproducing apparatus and digital PLL circuit of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,9 Waveform equalization circuit 2,10 A / D converter 3,12 Adaptive equalization filter 4,13 Viterbi decoder 5 Phase comparator 6,20 LPF
7,21 D / A converter (DAC)
8,22 Voltage controlled oscillator (VCO)
DESCRIPTION OF SYMBOLS 11 Low frequency component suppression circuit 14 Zero cross detection means 15 Period counter 16 Acquisition phase comparator 17 Tracking phase comparator 18 Reproduction clock extraction means 19 Selector means 23 First acquisition phase comparison means 24 Second acquisition phase comparison Means 25 Second zero cross detection means 26 Second period counter 27 Second acquisition phase comparator

Claims (10)

A digital information recording / reproducing apparatus that performs recording medium management in a predetermined recording unit and reproduces the recording medium in which a specific pattern is repeatedly recorded in a head area of each recording unit,
A / D conversion means for converting the reproduction signal from the recording medium into quantized data at the timing of the reproduction clock;
A low-frequency suppression circuit that removes a DC component contained in the quantized data output from the A / D converter;
Zero cross detection means for detecting the timing and direction in which the output signal of the low-frequency suppression circuit passes through the zero level, and outputting a zero cross timing flag and passing direction information;
A period counter that starts operation in accordance with the passage timing of the zero-cross detection means, counts at a predetermined period, and outputs a count value;
From the passing direction information output from the zero-cross detection means and the count value of the period counter, a phase error detector for acquisition that predicts the timing at which the output signal of the low-frequency suppression circuit zero-crosses and outputs an initial phase error;
A tracking phase error detector that outputs a phase error from the output signal of the low-frequency suppression circuit;
Switch between the initial phase error signal output from the acquisition phase error detector in the start area of the recording unit and the phase error signal output from the tracking phase error detector in areas other than the start area of the recording unit. Selector means for outputting a phase error by
Regenerated clock extracting means for generating the regenerated clock using the phase error of the selector means,
The zero-cross detection means compares the output signal of the low-frequency suppression circuit with a zero level, detects a predetermined pattern consisting of the maximum run length combination included in the specific pattern from the comparison result, and outputs a zero-cross timing flag The digital information recording / reproducing apparatus, wherein the period counter outputs a counter value at the period of the specific pattern, and the acquisition phase error detector outputs an initial phase error from the predicted zero cross point. The timing signal extraction means includes a low-frequency suppression circuit that smoothes the initial phase error signal and the phase error signal, a D / A converter that converts an output of the low-frequency suppression circuit into an analog signal, and the analog signal 2. The digital information recording / reproducing apparatus according to claim 1, wherein the digital information recording / reproducing apparatus is composed of an oscillator that generates a clock having a predetermined frequency. The zero-cross detection means compares the output signal of the low-frequency suppression circuit with a zero level, and a predetermined pattern comprising a combination of a 5T mark and a 5T space (T is a channel clock period) included in the specific pattern based on the comparison result. 2. The digital information recording / reproducing apparatus according to claim 1, wherein a zero cross timing flag is output. The digital phase error detector according to claim 1, wherein the acquisition phase error detector switches a period of the period counter and a timing at which the quantized data predicted from the count value of the period counter crosses zero according to a recording medium to be reproduced. Information recording / reproducing apparatus. The acquisition phase error detector compares the output signal of the low-frequency suppression circuit with a zero cross level, and from the comparison result, m predetermined consecutive patterns consisting of a combination of maximum run lengths included in the specific pattern The zero cross detection means is a combination of consecutive m ± 1 '0's and consecutive n' 1's, or '0' and consecutive n '1's (m, n is an integer greater than or equal to 2) 2. The digital information recording / reproducing apparatus according to claim 1, wherein a zero cross timing flag is output even when a combination of consecutive m "0" s and consecutive n ± 1 "1" s. A / D conversion means for converting the reproduction signal from the recording medium into quantized data at the timing of the reproduction clock;
A low-frequency suppression circuit that removes a DC component contained in the quantized data output from the A / D converter;
Zero cross detection means for detecting the timing and direction in which the output signal of the low-frequency suppression circuit passes through the zero level, and outputting a zero cross timing flag and passing direction information;
A period counter that starts operation in accordance with the passage timing of the zero-cross detection means, counts at a predetermined period, and outputs a count value;
From the passing direction information output from the zero-cross detection means and the count value of the period counter, a phase error detector for acquisition that predicts the timing at which the output signal of the low-frequency suppression circuit zero-crosses and outputs an initial phase error;
A tracking phase error detector that outputs a phase error from the output signal of the low-frequency suppression circuit;
Switch between the initial phase error signal output from the acquisition phase error detector in the start area of the recording unit and the phase error signal output from the tracking phase error detector in areas other than the start area of the recording unit. Selector means for outputting a phase error by
Regenerated clock extracting means for generating the regenerated clock using the phase error of the selector means,
The zero-cross detection means compares the output signal of the low-frequency suppression circuit with a zero level, detects a predetermined pattern consisting of the maximum run length combination included in the specific pattern from the comparison result, and outputs a zero-cross timing flag In the digital PLL circuit, the period counter outputs a counter value at the period of the specific pattern, and the acquisition phase error detector outputs an initial phase error from the predicted zero cross point. The timing signal extraction means includes a low-frequency suppression circuit that smoothes the initial phase error signal and the phase error signal, a D / A converter that converts an output of the low-frequency suppression circuit into an analog signal, and the analog signal 7. The digital PLL circuit according to claim 6, comprising an oscillator that generates a clock having a predetermined frequency. The zero-cross detection means compares the output signal of the low-frequency suppression circuit with a zero level, and a predetermined pattern comprising a combination of a 5T mark and a 5T space (T is a channel clock period) included in the specific pattern based on the comparison result. 7. The digital PLL circuit according to claim 6, wherein a zero cross timing flag is output. The digital phase error detector according to claim 6, wherein the acquisition phase error detector switches a period of the period counter and a timing at which the quantized data predicted from the count value of the period counter crosses zero depending on a recording medium to be reproduced. PLL circuit. The acquisition phase error detector compares the output signal of the low-frequency suppression circuit with a zero cross level, and from the comparison result, m predetermined consecutive patterns consisting of a combination of maximum run lengths included in the specific pattern The zero cross detection means is a combination of consecutive m ± 1 '0's and consecutive n' 1's, or '0' and consecutive n '1's (m, n is an integer greater than or equal to 2) 7. The digital PLL circuit according to claim 6, wherein a zero-cross timing flag is output even for a combination of consecutive m '0's and consecutive n ± 1' 1's.

Images