JP3926779B2 - Digital phase locked loop circuit - Google Patents

Description

  The present invention relates to a digital phase-locked loop circuit, and more particularly to a digital phase-locked loop circuit used for reproducing a clock for reproducing digital data recorded on an optical disk medium, a magneto-optical disk medium, a magnetic medium, or the like.

  In general, an optical disk device is well known as one of devices for recording and reproducing digital data. Conventionally, a phase-locked loop (PLL) circuit is used to synchronize the phase of a clock component of a reproduction signal with the phase of a reproduction clock when reproducing digital data in an optical disc apparatus. In particular, on a rewritable optical disc medium, there are a plurality of unit blocks called sectors each composed of a header portion in which address information and the like are written and a data portion for actually recording digital data. The phase-locked loop performs phase synchronization for each sector. In order to perform such intermittent reproduction normally, as shown in FIG. 8, a synchronous lead-in pattern (hereinafter referred to as a VFO pattern) 23a through a single frequency is formed in the header part and data part of the sector. 23d exists.

  In this VFO pattern area, the response characteristic of the phase-locked loop circuit is accelerated to perform high-speed and stable phase synchronization, and the response characteristic of the phase-locked loop is delayed before the end of the VFO pattern area. By reducing this, the synchronization state is maintained and data reproduction is performed. In FIG. 8, SM24 is a sector mark indicating the start position of the sector, AM25 is an address mark indicating the start position of the address information, ID26 is address information indicating the address of the sector, and PA27 is each of the header portion and the data portion. The postamble DM28 indicating the end point is a data mark indicating the start position of the recording data 29.

  An example of a block configuration of a digital data reproducing circuit in the optical disc apparatus is shown in FIG. On the optical disk medium 30, digital data in which the number of consecutive 0s or 1s is regulated to 3 or more and 14 or less as in the 8-16 modulation method, for example, is recorded. The reproduction signal obtained by reproducing by the reproducing means 31 is provided with the waveform equalizing means 1 because the amplitude of the waveform having a high frequency component is attenuated by interference as the recording data increases in the linear direction in the linear direction. The waveform equalizing means 1 performs correction so as to emphasize the high frequency component of the reproduction signal. The reproduction signal emphasized by the high frequency by the waveform equalizing means 1 is binarized at a predetermined slice level by the binarizing means 32 and converted into a binary digital signal.

  The phase-locked loop circuit 33 is controlled so as to be synchronized with the phase of the clock component of the binary digital signal from which the phase of the recovered clock, which is the free-running frequency, is obtained. That is, the phase-locked loop circuit 33 compares the recovered clock with the phase of the binarized signal by the phase comparator 34, and loops so that the phase error is minimized based on the phase error information output as a result. The phase of the recovered clock is changed by a filter 35, an amplifier 36, and a VCO (voltage controlled oscillator) 37. The response characteristic of the phase locked loop circuit 33 is switched by the loop gain switch 38. Then, the reproduction clock synchronized with the binarized signal is input to the demodulation circuit 39 to demodulate the digital data.

  Incidentally, the VFO pattern areas 23a to 23d in FIG. 8 on the optical disk medium 30 may have a limited range that can be normally reproduced by a defect, servo processing, signal processing, or the like. In order to perform reliable phase-synchronization even in such a case, for example, a method for detecting a defect, the sector mark 24, the address mark 25, and the data mark 28 shown in FIG. 8 are detected, and all the VFO pattern areas are maximized. Measures such as use for the limit are taken.

  The above-mentioned digital data reproduction circuit is suitable for a method of demodulating the digital data by binarizing and discriminating the recorded / reproduced signal, but the signal-to-noise ratio of the reproduced signal is significantly deteriorated as the line density increases. When it came, there was a problem that the quality of the reproduction data deteriorated. Therefore, as the recording density in the linear direction increases, a signal processing system called partial response maximum lye hood (hereinafter referred to as PRML), which is a signal processing system suitable for high-density recording / reproduction in the linear direction, is used. There is a tendency to be adopted. The above PRML signal processing method is the most reliable in accordance with the known interference rules after intentionally promoting waveform interference in the reproduced signal, equalizing the reproduced signal to a band limited so as to suppress noise enhancement as much as possible. In this method, data is demodulated by a maximum likelihood decoder that demodulates a new sequence.

  In the case of adopting the PRML signal processing method as described above, data sampled in multiple bits must be generated by a reproduction clock synchronized with the phase of the clock component of the reproduction signal. However, since the conventional phase-locked loop circuit 33 is composed of analog elements, it is a system in which analog circuits and digital circuits are mixedly mixed, and is not suitable for integration. In addition, the analog circuit is subject to variations in characteristics and changes over time due to the analog elements constituting the analog circuit, and it is necessary to sufficiently consider quality control and compensation circuits. For this reason, there has been a problem that the cost of the digital data reproducing apparatus is increased.

  On the other hand, if a phase-locked loop circuit that performs clock recovery is to be realized with a digital circuit, the amount of delay in the loop increases as the transfer rate increases. There was a problem that the range was reduced. When phase error information is obtained from an analog signal, continuous time error amounts can be handled, whereas when phase error information is obtained from sampled digital data, it is near zero crossing. This is because the phase error information must be estimated from the amplitude value of the signal, so that a sufficient continuous region of the phase error signal cannot be secured.

  Further, the VFO pattern area is short, and in the case of a rewritable disc, there is a high possibility that the first half of the VFO pattern area deteriorates with the number of writing times or the DC offset position is greatly shifted. For this reason, if the frequency of the recovered clock and the frequency of the clock component of the recovered signal are far apart, phase synchronization pull-in is not completed only in the VFO pattern area, and burst errors during playback increase, resulting in data quality degradation. There was a problem of inviting.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a digital phase-locked loop circuit that has a wide range of capture ranges and can synchronously pull in the phase of the recovered clock and the phase of the clock component of the recovered digital signal at high speed. is there.

  Another object of the present invention is that, in addition to the above-described object, synchronization pull-in is also performed for digital data in which there is no pattern signal composed of a single frequency in the data format of digital information recorded on a recording medium. It is to provide a digital phase locked loop circuit capable of performing the above.

  Yet another object of the present invention is to provide a digital phase-locked loop circuit that is easy to integrate, highly reliable, and low in cost in addition to the above objects.

The invention according to claim 1 is a digital phase-locked loop circuit that generates a reproduction clock for reading digital data recorded in a predetermined data format on a recording medium and obtaining a reproduction digital signal,
A loop gain controller for outputting a loop gain control gate signal for increasing the phase pull-in capability for a predetermined period from the start of the phase pull-in;
An analog-to-digital converter that samples the digital data into a multi-bit digital data signal using a recovered clock;
When predicting the zero-crossing position of random data in the sampled multi-bit digital data signal, the random data of four clocks continuous with the reproduction clock as a reference clock is converted into a binary signal based on the reference level. A zero-cross position predictor that generates timing information obtained by conversion, and
An acquisition phase error detector for detecting phase error information of the random data from the output signal of the zero cross position predictor and the multi-bit digital data signal;
A zero-cross detector that detects a position where the sampled multi-bit digital data signal crosses a zero level and outputs a zero-cross flag;
A tracking phase error detector for detecting a phase error of the multi-bit digital data signal based on the zero cross flag;
A switcher for switching the phase error signal output from the acquisition phase error detector and the tracking phase error detector by the loop gain control gate signal;
A loop filter for filtering the output signal of the switch;
A digital-to-analog converter for converting the output signal of the loop filter into an analog signal;
An oscillator that generates the recovered clock based on an analog output of the digital-analog converter ;
The zero cross position predictor is
First delay means for delaying an input signal to the zero cross position predictor by one clock of the recovered clock;
First addition means for adding the input signal to the zero-cross position predictor and the output signal of the first delay means;
Conversion means for outputting 1 if the polarity of the output signal of the first addition means is positive, and outputting 0 if the polarity is negative;
Second delay means for delaying the output signal of the conversion means by one clock of the recovered clock;
Third delay means for delaying the output signal of the second delay means by one clock of the recovered clock;
Fourth delay means for delaying the output signal of the third delay means by one clock of the recovered clock;
A second adding means for adding the output signal of the converting means, the output signal of the second delay means, the output signal of the third delay means, and the output signal of the fourth delay means;
For identifying the zero-cross position of the input signal to the zero-cross position predictor based on the five-stage level information output from the second adding means and detecting the phase error signal in the acquisition phase error detector Output timing signal
In the prediction of the zero cross position of the random signal area of the digital data, the timing information is generated from the continuous input signal for 4 clocks using the recovered clock as a reference clock, and based on the phase error information obtained from the timing information, The phase of the reproduction clock and the phase of the clock component of the reproduction digital signal are synchronized.

By using the above phase error information obtained from the prediction of the zero crossing position in the random signal domain of the digital data, the phase error curve is continuous even for digital data in which no single frequency signal exists in the random signal domain and data format. The area is expanded. As a result, the capture range is greatly expanded, and the phase synchronization of the phase of the recovered clock and the phase of the clock component of the recovered digital signal can be performed at high speed and stably.

By the action of the zero cross position predictor, the zero cross position of random data in the sampled multi-bit digital data signal is predicted, and by using the phase error information obtained from the prediction of the zero cross position , the random signal region and The continuous region of the phase error curve is extended even for digital data in which no single frequency signal exists in the data format. As a result, the capture range is greatly expanded, and the phase synchronization of the phase of the recovered clock and the phase of the clock component of the recovered digital signal can be performed at high speed and stably.

  According to the present invention, in a pattern region constituted by a single frequency, an accurate phase error can be detected even when a DC component is present in the reproduction signal. The continuous area of the error curve can be expanded, the capture range is greatly expanded, and even when the frequency of the recovered clock and the frequency of the clock component of the recovered signal are far apart, the phase of the recovered clock and the recovered digital are stable. The phase of the clock component included in the data can be synchronized.

  In addition, according to the present invention, by using the zero cross position predictor, the continuous region of the phase error curve can be expanded even for digital data in which no single frequency signal exists in the data format, so the capture range is greatly increased. Not only can the phase of the recovered clock be synchronized with the phase of the clock component of the recovered digital data at a high speed and stably, but also the redraw time can be shortened when the phase is redrawn due to defects etc. Thus, it is possible to minimize degradation of reproduction data quality due to a burst error or the like.

  Furthermore, digitizing the phase-locked loop facilitates integration when implemented as an IC, which not only leads to cost reduction, but also enables clock recovery suitable for the PRML signal processing method. A system suitable for high-density recording / reproduction can be provided.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 1 shows one embodiment in which the digital phase locked loop circuit according to the present invention is applied to an optical disk apparatus. In FIG. 1, a waveform equalizing means 1 is composed of, for example, a high-order equiripple filter that can arbitrarily set a boost amount and a cut-off frequency, and emphasizes the high frequency of an input optical disk reproduction signal. Make appropriate corrections. The output signal of the waveform equalizing means 1 is supplied to the analog / digital converter 2. The analog / digital converter 2 samples the output signal of the waveform equalization means 1 which is an analog signal into a multi-bit digital signal by using the recovered clock generated by the oscillator 12.

  The multi-bit digital signal sampled by the analog / digital converter 2 is input to a low frequency component suppression circuit 3 that suppresses a low frequency noise component. As the low-frequency component suppression circuit 3, for example, amplitude information near the zero cross of a reproduction signal is input to a low-pass filter, and the obtained low-frequency component is subtracted from the input signal by matching the correlation of data. What has the structure which suppresses area noise can be used.

  The digital phase-locked loop circuit of FIG. 1 includes a gate generator 13 that generates a gate signal indicating whether or not the currently reproduced signal is a VFO pattern. For example, the gate generator 13 starts counting from the head of the sector by a counter using a reproduction clock as a reference signal, and outputs a gate signal for distinguishing the VFO pattern area and the data area at a predetermined location according to the count number. Things can be used. The VFO pattern is a pattern in which a 4T pattern (T is a minimum recording unit) is continuously repeated as in a DVD-RAM (DVD random access memory), for example.

  When the output signal of the gate generator 13 indicates that the VFO pattern is currently being reproduced, the output signal of the low-frequency component suppression circuit 3 is a BPF (band-pass) that removes a DC (direct current) component. Type filter) 4. The BPF 4 is a digital filter that nulls the DC component in accordance with the period of the VFO pattern. As the digital filter, for example, when the VFO pattern is a 4T continuous waveform, as shown in FIG. 2, the delay means 14 for delaying by a time corresponding to 4T and the output of the delay means 14 from the current data are used. What comprises the subtraction means 15 for subtracting can be used.

  The output signal of the BPF 4 is input to the zero cross detector 5. The zero cross detector 5 is a circuit for detecting a position where an input signal crosses a zero level. Therefore, when the output signal of the BPF 4 is input to the zero cross detector 5, the zero cross detector 5 outputs a zero cross flag indicating the zero cross position of the output signal of the BPF 4.

  The zero cross flag obtained by the zero cross detector 5 is supplied to the period counter 6. The period counter 6 continuously counts at an arbitrary period n proportional to the period of the VFO pattern signal, starting from the zero cross flag, and generates a timing for extracting a phase error signal. As shown in FIG. 3, the zero cross detector 5 assumes that the direction crossing the zero level of the reproduction signal alternates between rising and falling every 4T if the VFO pattern is a 4T continuous waveform. In consideration, the polarity when generating the phase error signal from the signal amplitude may be output at the same time.

  The timing signal obtained from the period counter 6 and the output signal of the BPF 4 are input to the acquisition phase error detector 7, and the phase error signal is obtained from the data that should originally be at the zero cross position by the acquisition phase error detector 7. Detected. Here, the acquisition phase error detector 7 has a function of generating a continuous phase error signal of ± 720 ° in a VFO pattern composed of 4T continuous signals, for example, as shown in FIG. ing. On the other hand, in the conventional phase error detector, as shown in FIG. 4B, only continuity of about ± 180 ° is guaranteed.

  Here, FIG. 5 shows a phase error signal output from the acquisition phase error detector 7 when the frequency of the recovered clock is different from the frequency of the clock component of the recovered digital data. As can be seen from FIG. 5, since the sampling data at the zero-cross position can be reliably traced even when the frequency is different at the time of phase synchronization, the continuous region of the phase error signal is expanded.

  On the other hand, when the output signal of the gate generator 13 indicates that data other than the VFO pattern is currently being reproduced, the output signal of the low-frequency component suppression circuit 3 is input to the zero-cross detector 5. Yes. Thereby, the zero cross detector 5 outputs a zero cross flag indicating the zero cross position. At this time, the obtained zero cross flag and the output signal of the low frequency component suppression circuit 3 are input to the tracking phase error detector 8, and the phase error signal is always detected from data in the vicinity of the zero cross.

  The phase error signal output from the acquisition phase error detector 7 and the phase error signal output from the tracking phase error detector 8 are input to the switch 9 and switched according to the output signal of the gate generator 13. , And supplied to the loop filter 10. The loop filter 10 operates using these phase error signals as input signals so that the phase of the recovered clock and the phase of the clock component of the recovered digital signal are synchronized.

  The output signal of the loop filter 10 is converted into an analog signal by the digital / analog converter 11, and this analog signal is supplied to the oscillator 12. The oscillator 12 generates a recovered clock based on the analog signal. Here, the oscillator 12 may be constituted by a VCO (Voltage Controlled Oscillator) that controls the oscillation frequency with voltage, for example, or may be constituted by a digital element except for a digital / analog converter. There may be.

  In the digital phase-locked loop circuit having such a configuration, an accurate phase error can be detected even when a DC component is present in the reproduction signal in the VFO pattern region, so that the VFO pattern region can be used effectively. In addition, since the continuous region of the phase error curve can be expanded, the capture range is greatly expanded. As a result, even when the frequency of the reproduction clock and the frequency of the clock component of the reproduction signal are greatly separated, the phase of the reproduction clock and the phase of the clock component of the reproduction digital data can be synchronized with high speed and stability. Clock reproduction necessary for reproducing digital data recorded on the recording medium can be performed.

(Second Embodiment)
In this embodiment, for example, in the case of data in which a VFO pattern does not exist in a pattern recorded on an optical disk medium such as a DVD-ROM or a CD-ROM, the reproduction signal becomes a random signal. Only, the capture range when synchronizing the phase of the clock component of the recovered signal and the phase of the recovered clock is narrow, and if the two frequencies are far apart, reliable phase synchronization cannot be performed, or immediately after the burst error It also solves the problem that phase synchronization pull-in using the VFO pattern cannot be performed even when the phase synchronization is restored. The configuration of the present embodiment is shown in FIG.

  In FIG. 6, the waveform equalizing means 1, the analog / digital converter 2 and the low frequency component suppression circuit 3 are the same as those described in the first embodiment described in FIG. That is, the waveform equalization means 1 to which the optical disc reproduction signal is input is configured by, for example, a high-order equiripple filter or the like that can arbitrarily set the boost amount and the cutoff frequency. Make corrections that emphasize The output signal of the waveform equalizing means 1 is supplied to the analog / digital converter 2. The analog / digital converter 2 samples the output signal of the waveform equalization means 1 which is an analog signal into a multi-bit digital signal by using the recovered clock generated by the oscillator 12.

  The multi-bit digital signal sampled by the analog / digital converter 2 is input to a low-frequency component suppression circuit 3 that suppresses low-frequency noise. As the low-frequency component suppression circuit 3, for example, the amplitude information in the vicinity of the zero cross of the reproduced signal is input to the low-pass filter as in the first embodiment, and the obtained low-frequency component is matched with the data correlation. Thus, it is possible to use one having a configuration that suppresses low-frequency noise by subtracting from the input signal.

  In the present embodiment, a loop gain controller 16 is provided in an arbitrary section from the start of phase acquisition in order to obtain a strong phase acquisition capability. The loop gain controller 16 supplies a control gate signal for loop gain. As the loop gain controller 16, for example, counting is started from the head of the sector by a counter using a reproduction clock as a reference signal, and an acquisition area in which high-speed pull-in is emphasized and stability is emphasized in a predetermined place according to the count number. A device that outputs a gain control signal for selecting a tracking region can be used. As the loop gain controller 16, it is also possible to use one having a function of performing gain switching by self-detecting that the frequency of the reproduction clock and the frequency of the clock component included in the reproduction digital data are close.

  In this embodiment, when the output signal of the loop gain controller 16 indicates the current acquisition region, the polarity of the output signal of the low-frequency component suppression circuit 3 is determined, and the polarity results at different times. And a zero cross position predictor 17 that outputs a timing signal for determining a position for detecting a phase error signal by predicting data at the original zero cross position based on multi-level level information obtained as a result of adding. . Then, the timing signal obtained from the zero-cross position predictor 17 and the output signal of the low-frequency component suppression circuit 3 are input to the acquisition phase error detector 7 to detect a phase error signal from data that should originally be at the zero-cross position. I am doing so.

Here, for example, as a PRML signal processing method, the zero-cross position predictor 17 converts four consecutive times into a + b * D + b * D ² + a * D ³ (D ⁿ is a signal delayed by nT with respect to the reference time). The PR (a, b, b, a) ML system having the transmission characteristic represented by the equation (1) is used. As the zero cross position predictor 17, when there is no signal of 3T or less as a data format such as DVD and CD, for example, a device having a configuration as shown in FIG. 7 can be used.

  The zero cross position predictor 17 shown in FIG. 7 has a delay means 18 for delaying the input signal by 1T, an adder means 19 for adding the input signal and the delay means 18, and an output signal from the adder means 19. 1 is output if it is positive, 0 if it is negative, delay means 21a, 21b, 21c for delaying the output signal of the conversion means 1T, and conversion means 20 and delay means 21a, 21b. , 21c, and adding means 22 for adding output signals for four consecutive times. The zero-cross position predictor 17 specifies, for example, that the position to be 2 is the zero-cross position based on the five-level level information of 0 to 4 having a correlation with the input signal obtained from the adding means 22, and determines the timing. Output a signal.

  When the output signal of the loop gain controller 16 indicates that the tracking region is currently being reproduced, the zero cross position is determined by inputting the output signal of the low frequency component suppression circuit 3 to the zero cross detector 5. The zero cross flag which is a signal to be obtained is obtained. At this time, the obtained zero-cross flag and the output signal of the low-frequency component suppression circuit 3 are input to the tracking phase error detector 8, and the phase error signal is always detected from data near the zero-cross.

  The phase error signal output from the acquisition phase error detector 7 and the phase error signal output from the tracking phase error detector 8 are input to the switch 9 and output in accordance with the output signal of the loop gain controller 16. It is switched and supplied to the loop filter 10. The loop filter 10 operates with the phase error signal as an input signal so that the phase of the recovered clock is synchronized with the phase of the clock component of the recovered digital signal.

  The output signal of the loop filter 10 is converted into an analog signal by the digital / analog converter 11, and the analog signal is supplied to the oscillator 12. The transmitter 12 generates a reproduction clock based on the analog signal. Here, the oscillator 12 may be constituted by a VCO (Voltage Controlled Oscillator) that controls the oscillation frequency with voltage, for example, or may be constituted by a digital element except for a digital / analog converter. May be.

  According to this embodiment, the continuous area of the phase error curve can be expanded even for digital data in which there is no pattern signal composed of a single frequency in the data format, so that the capture range is greatly expanded and reproduced. Even when the frequency of the clock and the frequency of the clock component of the playback signal are greatly separated, the phase of the playback clock and the phase of the clock component of the playback digital data can be synchronized at high speed and recorded on the recording medium. It is possible to perform clock recovery necessary for reproducing digital data. In addition, it is possible to shorten the re-drawing time when performing phase re-drawing due to a defect or the like, and it is possible to minimize degradation of reproduction data quality due to a burst error or the like.

1 is a block diagram showing a configuration of a first embodiment of a digital phase locked loop circuit according to the present invention. It is a block diagram which shows the structure of BPF of FIG. It is explanatory drawing which shows the relationship between count operation | movement of the period counter of FIG. 1, and a phase error signal. It is explanatory drawing of the continuity of the phase error signal in 1st Embodiment of the digital phase locked loop circuit based on this invention, and the conventional phase locked loop. It is explanatory drawing of the phase error signal output from the phase error detector for acquisition of FIG. 1 on the conditions from which a synchronous frequency differs. It is a block diagram which shows the structure of 2nd Embodiment of the digital phase locked loop circuit based on this invention. It is a block diagram which shows the structural example of the zero cross position predictor of FIG. It is explanatory drawing of the data format inside the sector in an optical disk reproducing | regenerating apparatus (DVD-RAM). It is a block diagram which shows the structure of the conventional optical disk reproducing | regenerating apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Waveform equalization means 2 Analog / digital converter 3 Low frequency component suppression circuit 4 Band pass type filter (BPF)
DESCRIPTION OF SYMBOLS 5 Zero cross detector 6 Period counter 7 Acquisition phase error detector 8 Tracking phase error detector 9 Switcher 10 Loop filter 11 Digital analog converter 12 Oscillator 13 Gate generator 14 Delay means 15 Subtraction means 16 Loop gain controller 17 Zero cross position predictor 18 Delay means 19 Addition means 20 Conversion means 21a-21c Delay means 22 Addition means 23a-23d VFO pattern area 24 Sector mark 25 Address mark 26 Address information area 27 Postamble 28 Data mark 29 Recording data area 30 Optical disk medium 31 Reproduction means

Claims (3)

A digital phase-locked loop circuit for generating a reproduction clock for reading digital data recorded in a predetermined data format on a recording medium and obtaining a reproduction digital signal,
A loop gain controller for outputting a loop gain control gate signal for increasing the phase pull-in capability for a predetermined period from the start of the phase pull-in;
An analog-to-digital converter that samples the digital data into a multi-bit digital data signal using a recovered clock;
When predicting the zero-crossing position of random data in the sampled multi-bit digital data signal, the random data of four clocks continuous with the reproduction clock as a reference clock is converted into a binary signal based on the reference level. A zero-cross position predictor that generates timing information obtained by conversion, and
An acquisition phase error detector for detecting phase error information of the random data from the output signal of the zero cross position predictor and the multi-bit digital data signal;
A zero-cross detector that detects a position where the sampled multi-bit digital data signal crosses a zero level and outputs a zero-cross flag;
A tracking phase error detector for detecting a phase error of the multi-bit digital data signal based on the zero cross flag;
A switcher for switching the phase error signal output from the acquisition phase error detector and the tracking phase error detector by the loop gain control gate signal;
A loop filter for filtering the output signal of the switch;
A digital-to-analog converter for converting the output signal of the loop filter into an analog signal;
An oscillator that generates the recovered clock based on an analog output of the digital-analog converter ;
The zero cross position predictor is
First delay means for delaying an input signal to the zero cross position predictor by one clock of the recovered clock;
First addition means for adding the input signal to the zero-cross position predictor and the output signal of the first delay means;
Conversion means for outputting 1 if the polarity of the output signal of the first addition means is positive, and outputting 0 if the polarity is negative;
Second delay means for delaying the output signal of the conversion means by one clock of the recovered clock;
Third delay means for delaying the output signal of the second delay means by one clock of the recovered clock;
Fourth delay means for delaying the output signal of the third delay means by one clock of the recovered clock;
A second adding means for adding the output signal of the converting means, the output signal of the second delay means, the output signal of the third delay means, and the output signal of the fourth delay means;
For identifying the zero-cross position of the input signal to the zero-cross position predictor based on the five-stage level information output from the second adding means and detecting the phase error signal in the acquisition phase error detector Output timing signal
In the prediction of the zero cross position of the random signal area of the digital data, the timing information is generated from the continuous input signal for 4 clocks using the recovered clock as a reference clock, and based on the phase error information obtained from the timing information, A digital phase locked loop circuit characterized in that the phase of the reproduction clock and the phase of the clock component of the reproduction digital signal are synchronized. 2. The digital phase locked loop circuit according to claim 1 , wherein the timing signal corresponding to the zero cross position corresponds to a center level of the five levels of level information.   2. The digital phase locked loop circuit according to claim 1, wherein the predetermined data format is a data format based on a DVD (Digital Versatile Disc) or a CD (Compact Disc) standard.

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