JP3927561B2 - Reproduction signal processing apparatus and optical disk apparatus - Google Patents

Description

  The present invention relates to a reproduction signal processing apparatus and an optical disk apparatus, and more particularly to an oversampling optical recording / reproduction apparatus for reproducing data digitally recorded on a recording medium of an optical disk. A digital data demodulator that includes a PRML (Partial Response Maximum Live Cliff) signal processing system, which is an effective system for playback, has the feature of being able to simultaneously improve demodulated data quality and playback limit performance. It relates to what I did.

  As a method of recording digital data on an optical disk medium as an information recording medium, the linear velocity is constant as seen in a compact disk (hereinafter referred to as CD) and a DVD (Digital Versatile Disk). A method of making the recording density on the recording medium uniform is often used.

  Conventionally, when digital data is reproduced with respect to an optical disk reproduction signal digitally recorded by performing mark width modulation so that the linear recording density is constant, the phase of the clock component corresponding to the channel bit frequency of the reproduction signal , And phase lock-in is performed by configuring a phase-locked loop. Moreover, in order to improve the reproduction performance of media capable of high-density recording such as DVD-RAM (DVD-Random Access Memory) and BD (Blu-ray Disc), partials effective for high-density recording / reproduction in the linear direction A method of demodulating digital data by digital signal processing using a response maximum likelihood (hereinafter referred to as PRML) signal processing method has also been introduced.

  Conventionally, for example, there is a disk reproduction system as shown in FIG. 17 as one that enables such phase synchronization pull-in and that realizes a digital signal processing method such as a PRML signal processing method.

  In this conventional disc reproducing system, the optical recording medium 1 has a digital recording code (NRZI code; NRZI is an abbreviation of Non Return to Zero Invert) as shown in the uppermost part of FIG. It is recorded. It is assumed that the recorded data is data restricted so that the number of consecutive “0” or “1” is not less than 3 and not more than 14 as in the 8-16 modulation method. Since the optical disc reproduction signal 73 reproduced by the optical reproducing means 2 such as an optical pickup is attenuated in amplitude as the frequency component becomes higher due to interference as the recording density of recording data increases in the linear direction, the preamplifier After the signal is amplified by 3, the waveform equalizing means 4 performs correction to emphasize the high frequency component as shown in the upper part of FIG. 18.

  This high frequency emphasized reproduction signal is multi-bit by an analog / digital converter 5 as means for converting an analog signal into a digital signal using a reproduction clock 64 generated by a VCO (Voltage Controlled Oscillator) 62. The reproduced digital signal 63 is sampled. At this time, if the phase of the reproduction clock 64 and the phase of the clock component of the reproduction signal are synchronized, sampling data as shown in the middle part of FIG. 18 and the lower part of FIG. 18 is obtained. The middle part of FIG. 18 shows a sampling method when binarization determination is performed at an arbitrary level, and the lower part of FIG. 18 shows a sampling method particularly suitable for the PRML signal processing method.

  This PRML signal processing method is a waveform that is intentionally applied by applying a partial response method in a reproduction system in which the amplitude of a high-frequency component deteriorates and the signal-to-noise ratio increases as the recording density in the linear recording direction increases. A reproduction system that does not require high-frequency components is realized by adding interference, and the quality of reproduced data is improved by the maximum likelihood decoding method that estimates the most probable sequence by probability calculation considering the waveform interference. This is a method (see, for example, Patent Document 1).

  The multi-bit reproduction digital signal 63 output from the analog / digital converter 5 is input to the offset correction means 7 so that the offset component contained in the reproduction digital signal, that is, the amplitude from the center level where the code balance is obtained. Correct the direction offset. The reproduced digital signal subjected to the offset correction is demodulated into a digital binarized signal by the PRML signal processing means 17 constituted by a transversal filter and a Viterbi decoder. At this time, by applying partial response equalization, the equalized output signal output from the transversal filter to the Viterbi decoder is multi-valued into five values inside the PRML signal processing means 17 ( (See the lower part of FIG. 18). The five-level equalized output signal is subjected to probability calculation by a Viterbi decoder to generate a binary signal.

The reproduction clock 64 when sampling is performed by the analog / digital converter 5 is generated as follows.
First, using the output signal of the offset correction means 7, the phase synchronization control means 10 constituted by a phase comparator, a loop filter, and a digital / analog converter performs phase synchronization control between the reproduction clock and the reproduction digital signal. A phase control amount is generated. Based on the phase control amount, the VCO 62 is controlled, and a recovered clock 64 is obtained as an output of the VCO 62.

  By such a series of operations, the phase of the reproduction clock and the phase of the clock component of the reproduction digital signal are synchronized, and the digital data recorded on the optical disk medium is stably and accurately applied by applying the PRML signal processing method. It is possible to reproduce well (see, for example, Patent Document 2).

In addition, by using a clock having a frequency faster than the channel bit frequency, an analog / digital converter converts an optical reproduction waveform into a digital reproduction signal, and a digital PLL is configured using an interpolation filter in the phase direction. Some of them generate digital data demodulated by generating synchronized playback digital signals (see, for example, Patent Document 3).
Japanese Unexamined Patent Publication No. 2002-269925 (5th page, 6th page, 12th page-14th page, FIG. 3, FIG. 10, FIG. 27) JP 2000-123487 A (page 4, FIG. 9) Japanese Patent No. 3255179 (5th page, Fig. 1)

  The conventional optical disk reproducing apparatus is configured as described above, and is a multi-bit discrete signal by an analog / digital converter using a channel bit clock synchronized with a channel bit frequency which is a clock component of a reproduction waveform from an optical disk medium. Then, a PLL (Phase Locked Loop) is configured using the signal to perform phase synchronization pull-in control and data demodulation such as PRML signal processing.

  However, when a PLL is configured using a multi-bit discrete signal after an analog / digital converter generated on the basis of a channel bit clock, it also takes time to detect phase error information, etc., so the delay time of the control loop By increasing, the phase synchronization pull-in performance deteriorates. As a result, the quality of the reproduced waveform deteriorates due to the tilt defined by the angle between the vertical axis with respect to the recording surface of the optical disk medium and the incident axis of the laser beam, the reproduction is performed under a poor signal-to-noise ratio, and the top and bottom of the reproduced waveform are asymmetric. The phase synchronization pull-in control first fails for the degradation of local reproduction characteristics that depend on defects such as asymmetry and scratches on the disk surface, dirt, fingerprints, etc., and the effectiveness of the PRML signal processing system is fully There were cases where it could not be demonstrated.

  In addition, in the case where such PLL and PRML signal processing means are used in combination, in addition to the binarized output as the output of the PRML signal processing means, the binarized output obtained by determining the level of the output of the phase comparison means inside the PLL The following two types can be obtained.

  A binarized output (hereinafter referred to as a level discrimination method) obtained by discriminating that the output of the phase comparison means is “1” if it is equal to or higher than the waveform level, and “0” if it is below is generated on the disk surface. Although it is strong against scratches and stable reproduction is possible even if the scratched part is reproduced, the binarized output (hereinafter referred to as the PRML signal processing method) as the output of the PRML signal processing means originally There is an advantage that stable reproduction is possible even when a disc with poor signal quality is reproduced and a disc with poor signal quality is resistant to tilt degradation and the like.

  However, since the level discrimination method and the PRML signal processing method are realized by switching the sampling method, the level discrimination method that is stable against a burst error caused by a defect or the like and the high-density recording / reproduction in the line direction can be used. An effective PRML signal processing method cannot be realized at the same time with maximum accuracy, and therefore, an optimal detection method may not be selected depending on the reproduction state. Furthermore, since the information in the time direction is missing, the detection accuracy of jitter information tends to deteriorate. As a result, when the asymmetry is large, the learning of the cutoff frequency and boost amount in focus servo and waveform equalization may not converge to the optimal values, which may cause the playback performance to deteriorate. .

  On the other hand, since the oversampling clock is used in the one disclosed in Patent Document 3, it is possible to solve the problems such as the tilt deterioration due to the convergence speed of the PLL.

  However, the method of Patent Document 3 is an asynchronous oversampling in which the relationship between channel bit frequency and oversampling is not an integral multiple. In this asynchronous oversampling, a synthesizer is used instead of a VCO having a large circuit scale. In the field of optical discs, in the field of optical discs, a plurality of types of optical discs have been put into practical use in recent years, and a synthesizer is used as an optical disc in order to support various optical disc playback with a single optical disc device. However, there is a problem that the circuit scale increases. Also, this asynchronous oversampling method has a problem that the PRML circuit becomes complicated.

  The present invention has been made in view of such circumstances. When digital data recorded on an optical disk medium is demodulated, the delay time of the PLL can be shortened, the reproduction limit performance can be improved, and the high in the line direction. Not only is the output signal of the PRML signal processing system, which is advantageous for recording density reproduction, improved more than before, but when burst errors frequently occur due to defects etc., the output signal of the level discrimination system is real-time. It is an object of the present invention to provide a reproduction signal processing apparatus excellent in general versatility that can be switched at the same time, and an optical disk apparatus having the same.

  Furthermore, an object of the present invention is to provide a reproduction signal processing apparatus and an optical disk apparatus having the same, which can improve the detection accuracy of jitter and can optimize learning of focus servo and waveform equalization because information in the time direction increases. And

In order to solve the above-mentioned problem, a reproduction signal processing apparatus according to claim 1 of the present invention provides a reproduction waveform obtained by reading a digital signal recorded on an information recording medium by an information reproduction means, as a channel bit clock of the digital signal. A multi-bit discrete signal is converted with an oversampling clock synchronized with a frequency corresponding to N times the frequency (N is a multiple of 2 or more), and the multi-bit discrete signal is synchronized with the frequency of the channel bit clock. Oversampling phase synchronization means for generating first, second, and third digital data having different phases, first demodulation means for demodulating the first digital data, and the second digital data or the first digital data And a digital data demodulating means having a second demodulating means for demodulating the third digital data. A.
Thereby, the loop delay time of the PLL can be shortened by using the oversampling clock, the reproduction limit performance can be improved, and the digital demodulated data by the respective demodulation methods can be parallel from the first demodulation means and the second demodulation means. The effect that it is obtained is obtained.

According to a second aspect of the present invention, there is provided a reproduction signal processing apparatus comprising a reproduction waveform obtained by reading out a digital signal recorded on an information recording medium by an information reproduction means, N times the frequency of a channel bit clock of the digital signal (N Is converted to a multi-bit discrete signal with an oversampling clock synchronized with a frequency corresponding to a frequency corresponding to a multiple of 2 and is different from each other in phase with the multi-bit discrete signal synchronized with the frequency of the channel bit clock. , Oversampling phase synchronization means for generating second and third digital data, and jitter detection means for detecting a jitter component of the reproduced waveform using the first, second and third digital data. It is characterized by that.
Thereby, since the jitter component of the reproduction waveform is detected from the first, second and third digital data whose information in the time direction has increased by using the oversampling clock, the jitter detection accuracy is improved. The effect is obtained.

The reproduction signal processing apparatus according to claim 3 of the present invention is the reproduction signal processing apparatus according to claim 1 or 2, wherein the oversampling phase synchronization means uses the oversampling clock to generate the multi-bits of the reproduction waveform. A phase relationship between the channel bit clock and the oversampling clock, analog / digital conversion means for converting the signal into discrete signals, clock frequency dividing means for generating a channel bit clock by dividing the oversampling clock by N, Phase determining means for uniquely determining, oversampling phase control means for converting the output signal of the analog / digital conversion means into a pre-demodulation processing signal and a control signal based on the output signal of the phase determination means, Output in synchronization with oversampling clock Operating cycle converting means for converting an output signal output from the oversampling phase control means to a signal that operates in synchronization with the channel bit clock; and operating in synchronization with the channel bit clock; And phase synchronization control means for detecting the phase error information from the output of the means and modulating the oversampling clock generated by the clock oscillation means so that the phase error information approaches zero. To do.
This makes it possible to shorten the delay time of the PLL by using the oversampling clock, thereby improving the reproduction limit performance against tilt, noise, asymmetry, defects, etc. Since the channel bit clock is supplied to the portions that are not required, the circuit scale and power consumption can be reduced.

The reproduction signal processing apparatus according to claim 4 of the present invention is the reproduction signal processing apparatus according to claim 3, wherein the phase determining means detects either a rising edge or a falling edge of the channel bit clock. Edge generating means for generating a signal necessary for performing, a reference flag generating means for generating a reference flag for the signal output by the edge generating means at a timing synchronized with the oversampling clock, and the reference flag Reference flag delay means for generating a phase reference signal for uniquely determining the phase relationship between the channel bit clock and the oversampling clock by delaying by an arbitrary clock of the oversampling clock. It is characterized by that.
Thereby, since the relationship between the oversampling clock and the channel bit clock can be uniquely determined, not only the configuration of the apparatus becomes easy, but also the effect of leading to stabilization of the phase synchronization pull-in control can be obtained.

The reproduction signal processing apparatus according to claim 5 of the present invention is the reproduction signal processing apparatus according to claim 3, wherein the oversampling phase control means is configured to synchronize the analog / digital signal with timing synchronized with the oversampling clock. A plurality of reproduction signal delay means for delaying and holding the output signal of the conversion means for each clock, and the output signals of the plurality of reproduction signal delay means at the timing of the phase reference signal generated by the phase determination means A plurality of reproduction signal holding means for holding, a polarity inversion detection means for judging whether or not the polarity is inverted with respect to two predetermined output signals in the output signals of the plurality of reproduction signal delay means; and the polarity inversion detection means And a polarity inversion information holding means for holding the output signal at the timing of the phase reference signal. It is.
Thereby, since the detection time of the phase error information can be shortened, there is an effect that the delay time of the PLL can be shortened.

The reproduction signal processing device according to claim 6 of the present invention is the reproduction signal processing device according to claim 5, wherein the plurality of reproduction signal delay means are represented by a period of 2π (π is a pi). A reproduction signal delay means A for outputting a reproduction signal located at a phase separated from the reference phase of the channel bit clock by a predetermined phase amount, and a reproduction signal located at a phase separated by 2π from the reproduction signal delay means A. Reproduction signal delay means C for outputting, and reproduction signal delay means B for outputting a reproduction signal which is intermediate between the reproduction signal delay means A and the reproduction signal delay means C and is located at a phase separated from the reproduction signal delay means A by π. The plurality of reproduction signal holding means hold reproduction signal holding means A, B, C for holding the output signals of the reproduction signal delay means A, B, C at the timing of the phase reference signal, respectively. The polarity inversion detection means determines whether the polarity is inverted based on the output signals of the reproduction signal delay means A and C among the plurality of reproduction signal delay means, A basic signal for detecting phase error information from the output of the oversampling phase control means is output by the reproduction signal holding means B.
As a result, in the past, it was necessary to interpolate and detect either polarity inversion information or phase error information, but in the present invention, phase inversion information and phase error information can be detected directly without interpolation. By improving the accuracy of the error information, the reproduction limit performance is improved, and an effect that it is particularly effective for asymmetry is obtained.

The reproduction signal processing device according to claim 7 of the present invention is the reproduction signal processing device according to claim 6, wherein the reproduction signal delay means A has a period of 2π among the plurality of reproduction signal delay means. The reproduced signal corresponding to the phase zero of the channel bit clock represented by (π is the pi) is output, and the reproduced signal delay means C is the one of the plurality of reproduced signal delay means. A reproduction signal corresponding to the phase 2π of the channel bit clock is output, and the reproduction signal delay means B outputs a reproduction signal corresponding to the phase π of the channel bit clock among the plurality of reproduction signal delay means. It is what outputs.
As a result, even when the phase error information is processed by the channel bit clock, no time is wasted, so that it is possible to realize an optimum PLL for performance and cost.

The reproduction signal processing apparatus according to claim 8 of the present invention is the reproduction signal processing apparatus according to claim 3, wherein the phase synchronization control means detects zero-cross position information of an output signal of the oversampling phase control means. Zero-cross position detecting means, phase error information detecting means for detecting phase error information between the zero-cross position information and the output signal of the oversampling phase control means, and a loop filter for smoothing the phase error information And operates in synchronization with the period of the oversampling clock.
As a result, the time for generating the phase control signal can be shortened, so that the delay time of the PLL can be shortened.

The reproduction signal processing apparatus according to claim 9 of the present invention is the reproduction signal processing apparatus according to claim 8, wherein the phase error information detection means is the plurality of the plurality of phase error information detection means by the polarity inversion detection means according to claim 6. When the polarity of the output signal of the reproduction signal delay means A and C in the reproduction signal delay means is determined to be inverted and the rising edge or the falling edge of the optical reproduction waveform is detected, The polarity of the output signal of the reproduction signal holding means B in the reproduction signal holding means is controlled and detected as phase error information.
As a result, the number of detections of the phase error information is increased and the detection accuracy is improved, so that the reproduction limit performance is improved.

A reproduction signal processing device according to claim 10 of the present invention is the reproduction signal processing device according to claim 2, wherein the first demodulation means for demodulating the first digital data and the second digital data are provided. Alternatively, digital data demodulating means comprising second demodulating means for demodulating the third digital data is further provided.
As a result, the loop delay time of the PLL can be shortened, the reproduction limit performance can be improved, and the digital demodulated data by each demodulation method can be obtained in parallel from the first demodulator and the second demodulator, and the time direction Since the jitter component of the reproduction waveform is detected from the first, second, and third digital data in which the above information is increased, the effect of improving the jitter detection accuracy can be obtained.

The reproduction signal processing apparatus according to claim 11 of the present invention is the reproduction signal processing apparatus according to claim 1 or 10, wherein the digital data demodulating means is the operation period converting means as the first demodulating means. The PRML (Partial Response Maximum Likelihood) signal processing means for estimating the most probable data sequence using the intentionally added intersymbol interference is used as the second demodulation means, and the operation cycle conversion is performed. Each of which has level discrimination binarization means for binarizing the output signal and performing digital data demodulation based on a center level where the code balance of the output signal of the means is balanced, and operates in synchronization with the channel bit clock. It is characterized by that.
This makes it possible to simultaneously obtain a demodulated signal by a PRML signal processing system effective for high-density recording / reproduction in the linear direction and a demodulated signal by a level discrimination system that is stable against burst errors caused by defects, etc. In combination with the improvement, the effect that the quality of demodulated data can be improved is obtained.

The reproduction signal processing apparatus according to claim 12 of the present invention is the reproduction signal processing apparatus according to claim 11, wherein the PRML signal processing means outputs the output signal of the reproduction signal holding means B according to claim 6. The data is demodulated with respect to the signal whose operation cycle is converted by the operation cycle conversion means.
As a result, by returning the oversampled frequency to the same frequency as the original channel bit frequency, the demodulated signal by the PRML signal processing method can be made meaningful, and it depends on the type, speed, and reproduction method of the optical disk medium. Thus, the effect that the PRML signal processing means can be used at all times is obtained.

The reproduction signal processing apparatus according to claim 13 of the present invention is the reproduction signal processing apparatus according to claim 11, wherein the level discrimination binarization means is the reproduction signal holding means A or C according to claim 6. The data is demodulated with respect to the binarized preprocessed signal obtained by converting the operation cycle of any one of the output signals by the operation cycle conversion means.
As a result, by returning the oversampled frequency to the same frequency as the original channel bit frequency, it is possible to make the demodulated signal based on the level discrimination method meaningful, and conventionally, the PRML signal processing means is selected as the demodulating means. In this case, the demodulated data could not be generated with high accuracy by the level discrimination binarization means, whereas in the present invention, since the two demodulation means operate simultaneously with the maximum accuracy, the type, speed, and reproduction method of the optical disk medium Therefore, it is possible to reproduce with a single control method without depending on the above, so that the structure can be easily obtained.

The reproduction signal processing device according to claim 14 of the present invention is the reproduction signal processing device according to claim 1 or 10, wherein the digital data demodulation means further comprises demodulation data switching means and selection means, The selecting means is characterized by selecting an output signal of either the first demodulating means or the second demodulating means according to a selection signal of the demodulated data switching means and outputting it as demodulated data. .
As a result, an effect is obtained that one of the first demodulating means and the second demodulating means can be automatically selected in accordance with the selection signal generated by the demodulated data switching means.

The reproduction signal processing apparatus according to claim 15 of the present invention is the reproduction signal processing apparatus according to claim 3, wherein the oversampling phase synchronization means reduces an offset component in an amplitude direction from the multi-bit discrete signal. And an offset correction means for outputting to the oversampling phase control means.
Thereby, the effect that the offset component of the amplitude direction contained in a multibit discrete signal can be reduced is acquired.

According to a sixteenth aspect of the present invention, in the reproduced signal processing device according to the fifteenth aspect, the offset correction means includes offset level information in the amplitude direction from the output signal of the oversampling phase control means. Offset level detecting means for detecting the offset level, offset level smoothing means for smoothing the offset level information in the amplitude direction, and offset by subtracting the output signal of the offset level smoothing means from the multi-bit discrete signal It has an offset level subtracting means for reducing the component.
As a result, the delay time of the offset correction control loop can be shortened compared to the conventional case, and the offset correction performance is improved. The effect that performance improves is acquired.

The reproduction signal processing device according to claim 17 of the present invention is the reproduction signal processing device according to claim 16, wherein the offset level detection means is a plurality of reproduction signal holding means according to claim 6. Center level fluctuation information detecting means for detecting fluctuation information of the center level of the reproduction signal from the output signals of the reproduction signal holding means B and the polarity inversion detection means, and the output signal of the plurality of reproduction signal holding means Polarity balance calculation means for detecting polarity balance information by accumulating polarity information from an output signal corresponding to one cycle of the channel bit clock, and the center level variation information and the polarity balance information at a predetermined ratio. And an offset information fusion means for detecting an offset level by addition. It is.
As a result, since the information in the time direction is increased as compared with the prior art, the detection accuracy of the offset level information in the amplitude direction is improved, so that the effect of improving the offset correction performance is obtained.

The reproduction signal processing apparatus according to claim 18 of the present invention is the reproduction signal processing apparatus according to claim 2, wherein the jitter detection means is the reproduction among the plurality of reproduction signal holding means according to claim 6. Jitter element detection means for detecting an absolute value component in the amplitude direction at the zero cross position from the output signals of the signal holding means B and the polarity inversion detection means, and reproduction signal holding means A and C of the plurality of reproduction signal holding means Jitter reference period detecting means for calculating the distance in the amplitude direction from the output signal, and absolute jitter component detection for detecting the jitter component by dividing the output signal of the jitter element detecting means by the output signal of the jitter reference period detecting means Means.
As a result, conventionally, since information necessary for detecting a jitter component has been generated by interpolation, the jitter component cannot be accurately detected. However, in the present invention, the necessary information can be directly detected. Therefore, the detection accuracy of the jitter component is improved. Therefore, since the learning accuracy of servo signal processing is improved, the effect that the quality of the reproduced waveform is stabilized can be obtained.

According to a nineteenth aspect of the present invention, there is provided an optical disc apparatus according to the nineteenth aspect, wherein a spindle motor for rotating the optical disc, an optical pickup for reading a reproduction signal from the optical disc, and a reproduction signal read by the optical pickup are processed. A reproduction signal processing device according to any one of the above, a decoding circuit that demodulates a signal processed by the reproduction signal processing device and performs error processing, a servo control circuit that controls the spindle motor and the optical pickup, And a system controller for performing data communication with the outside and controlling each functional block.
As a result, when demodulating digital data recorded on an optical disk medium, reproduction is performed by reducing the delay time of the PLL by introducing an oversampling clock having a frequency N times the channel bit clock (N is a multiple of 2). The limit performance can be improved. Furthermore, when the PRML signal processing method, which is advantageous for high recording density reproduction in the linear direction, is applied, not only the demodulated data quality is improved more than before, but also burst errors frequently occur due to defects etc. Can be switched to another binarized output signal and has excellent versatility, and the information in the time direction increases, so when performing jitter detection, the detection accuracy is improved, There is an effect that an optical disk apparatus capable of optimizing learning of focus servo and waveform equalization can be obtained.

  According to the present invention, the loop delay time of the PLL can be shortened by the oversampling effect, and the detection accuracy of the phase error information is improved, so that the reproduction limit for tilt, noise, asymmetry, defect, and the like is achieved. Performance is improved. In addition, a demodulated binary signal demodulated by a PRML signal processing system effective for high-density recording / reproduction in the line direction, and a level discrimination binarization capable of stable reproduction when a burst-like error occurs due to a defect or the like It is possible to improve playability by properly using the demodulated binary signal demodulated by the means according to the reproduction state. Furthermore, since the accuracy of jitter detection, which is an index for system optimization, is improved, it is possible to realize stable reproduction performance that does not depend on variations in the apparatus.

(Embodiment 1)
In the first embodiment, when reproducing an optical disk, a channel bit signal and a channel bit clock are synchronized with a PLL to obtain a reproduction signal from the channel, and this is decoded by a Viterbi decoder of the PRML signal processing means. By using an oversampling clock synchronized with the channel bit signal as a reproduction clock, the phase error can be detected within a short time, and the PLL phase synchronization pull-in performance can be improved. Two types of binarized outputs, the binarized output from the signal processing means and the binarized output based on the level discrimination of the output of the phase comparator constituting the PLL, are always in parallel without switching the sampling method. It is intended to be obtained.

  A reproduction signal processing apparatus according to an actual embodiment 1 of the present invention and an oversampling optical recording / reproduction apparatus as an optical disk apparatus having the same will be described below with reference to FIGS.

  The reproduction signal processing device corresponds to claims 1 to 18 of the present invention, and the oversampling type optical recording / reproduction device corresponds to claim 19, respectively. The performance of PLL (Phase Locked Loop) is improved, A PRML (Partial Response Maximum Likelihood) signal process that is advantageous for high-density recording and reproduction in the line direction and a level determination process that is advantageous when a defect occurs can be realized simultaneously and with high accuracy.

  FIG. 1 shows a reproduction signal processing apparatus 200 according to Embodiment 1 of the present invention, which includes a preamplifier 3, waveform equalization means 4, an analog / digital converter (analog / digital conversion means) 5, an offset correction means 7, and an oversampling phase control. From means 8, operation cycle conversion means 9, phase synchronization control means 10, clock oscillation means 11, clock frequency division means 13, phase determination means 15, PRML signal processing means 17, level discrimination binarization means 18, jitter detection means 22 Composed.

  The PRML signal processing means (first demodulating means) 17 and the level discriminating binarizing means (second demodulating means) 18 constitute a digital data demodulating means 19 from the reproduction signal processing device 200 to the preamplifier 3, the waveform equalizing means. 4. The portion excluding the digital data demodulating means 19 and the jitter detecting means 22 constitutes the PLL 100. Further, the part obtained by removing the clock oscillation means 11 from the PLL 100 constitutes the oversampling phase synchronization means 102. The oversampling phase control means 8 and the operation cycle conversion means 9 in the oversampling phase synchronization means 102 constitute a phase comparator (hereinafter referred to as PC) 101.

  In FIG. 1, an optical disk reproduction signal 73 is generated from an optical disk medium (information recording medium) 1 by an optical reproduction means (information reproduction means) 2 such as an optical pickup. In the optical disk reproduction signal 73 generated by the optical reproduction means 2, the amplitude attenuation of the reproduction signal becomes more significant in the high frequency component as the recording density in the linear direction increases according to the pattern of the adjacent recording code. This leads to deterioration of the jitter component. Therefore, the optical disk reproduction signal 73 input to the reproduction signal processing apparatus 200 is corrected in the optical disk reproduction signal by applying a correction that emphasizes the high frequency by the waveform equalization means 4 after the output amplitude is emphasized by the preamplifier 3. Amplify high-frequency component amplitude to improve jitter. Here, the waveform equalization means 4 is configured by a filter that can arbitrarily set the boost amount and the cutoff frequency. This filter may be, for example, a high-order equiripple filter having a frequency characteristic as indicated by a solid line in FIG. In this figure, the characteristic indicated by the dotted line is the frequency characteristic of the waveform equalizing means 4 when high-frequency boost is not performed.

  Next, the output signal of the waveform equalizing means 4 is converted into a multi-bit digital signal (a multi-bit discrete signal; hereinafter) by an analog / digital converter 5 that converts an analog signal into a digital signal using the oversampling clock 12 as a timing reference. (Referred to as a reproduction digital signal). Here, the oversampling clock 12 is generated by the clock oscillating means 11. That is, the oversampling clock 12 is N times the channel bit clock when the signal corresponding to one channel bit of the digital data written on the optical disk medium is reproduced based on the reproduced digital signal 6 (N is the oversampling ratio). And is generated as a clock synchronized with a frequency of a multiple of 2.

  The clock oscillation means 11 is configured, for example, to receive a multi-bit digital signal as a signal for controlling the oscillation frequency, and includes a digital / analog converter for converting the control digital signal into a voltage. A thing provided with VCO (Voltage Controlled Oscillator) which can vary an oscillation frequency by the voltage value converted by the analog converter may be used. Further, in order to generate a clock synchronized with the bit rate of the recording code recorded on the optical disc medium 1, the clock sampling means 13 divides the oversampling clock 12 to a frequency of 1 / N, and the channel bit clock. 14 is generated.

Hereinafter, a case where the oversampling ratio N is N = 4 will be described as an example.
When the oversampling ratio N is 4, the reproduced digital signal 6 converted by the analog / digital converter 5 has a sampling signal four times in the phase direction with respect to one channel bit of the recorded digital data. Yes. Therefore, it is necessary to uniquely determine which phase of the sampling signal in the reproduced digital signal 6 is a signal necessary for digital data demodulation. Therefore, the phase determination means 15 generates a phase reference signal 16 that uniquely determines the phase relationship between the channel bit clock 14 and the oversampling clock 12.

  FIG. 3 shows the configuration of the phase determining means 15 that generates the phase reference signal 16. The phase determining unit 15 includes an edge generating unit 24, a reference flag generating unit 28, and a reference flag delay unit 32. Note that the circuit configuration described in FIG. 3 is merely a basic example, and this circuit configuration may be applied to generate the phase reference signal 16.

First, in the edge generation means 24, a shift register B25 (denoted by Z- ¹ in FIG. 3) that outputs an input signal delayed by one clock in synchronization with the channel bit clock 14, and an output of the shift register B25 A periodic signal 27 is generated by an inverter 26 (indicated as INV in FIG. 3) which inverts the signal and inputs it as a clock to the shift register B25. This periodic signal 27 is obtained by dividing the channel bit clock by two as shown in FIG.

  Next, in the reference flag generating means 28, the periodic signal 27 is output after being delayed by one clock in synchronization with the oversampling clock 12, and the output signal of the shift register A29A and the periodic signal 27 are compared. Then, a reference flag 31 is generated by an exclusive OR circuit (indicated as EXOR in FIG. 3) 30 that outputs “0” when they match, and “1” when they do not match. To do. The reference flag 31 is delayed in the reference flag delay means 32 by a shift register composed of two stages of the shift register A 29 B and the shift register A 29 C, and the reference flag 31 is between the oversampling clock 12 and the channel bit clock 14. The phase reference signal 16 is output at a timing that minimizes the data transfer time.

  Next, the reproduction digital signal 6 sampled by the oversampling clock 12 is input to the offset correction means 7 to obtain the center of the waveform of the reproduction digital signal 6, and the offset component in the amplitude direction included in the reproduction digital signal 6. Correct. The detailed operation of the offset correction means 7 will be described later.

  On the other hand, in order to realize demodulation of digital data, it is necessary to generate an oversampling clock 12 and a channel bit clock 14 synchronized with the phase of the frequency of the clock component included in the reproduced digital signal 6. . In order to realize this, the phase error information is accurately extracted from the output signal of the offset correction means 7, and the phase error information is converted into a phase control signal by a filtering process such as smoothing. It is necessary to configure a PLL (Phase Locked Loop) that controls the clock oscillating means 11 so as to approach zero.

  This PLL (phase-locked loop) 100 synchronizes the phase of a channel bit clock of a digital signal recorded on the optical disk medium 1 and an oversampling clock having a frequency four times that of the digital signal, and an analog / digital converter 5 → offset The correction means 7 → oversampling phase control means 8 → operation cycle conversion means 9 → phase synchronization control means 10 → clock oscillation means 11 → analog / digital converter 5 as the main control loop. Oversampling phase control means 8 → The operation cycle conversion means 9 → phase synchronization control means 10 → clock oscillation means 11 → clock frequency dividing means 13 → phase determination means 15 → oversampling phase control means 8 is used as a sub control loop. The phase synchronization control means 10 has a low-pass filter (smoothing filter) inside.

  First, the oversampling phase control means 8 of the PLL 100 synchronizes with the oversampling clock 12 from the output signal of the offset correction means 7, and among the sampling signals “O” in FIG. ”And zero-cross position information indicating the change position of the polarity appearing at“ D0 ”and“ E0 ”, and phase error information corresponding to“ A2 ”and“ D2 ”are extracted from the sampling signal“ ● ”. After the reference information is detected, the information is held as reproduction holding outputs A, B, and C at the timing of the phase reference signal 16.

  Here, since the PRML signal processing means 17, the level discrimination binarization means 18, and the phase synchronization control means 10 do not make sense with the oversampling clock, they are held inside these oversampling phase control means 8. The operation cycle conversion means 9 converts the signal from a signal synchronized with the oversampling clock into a signal synchronized with the channel bit clock 14. This conversion is equivalent to dividing by four. Based on the converted signal or the output signal of the oversampling phase control means 8, the phase synchronization control means 10 extracts phase error information, and then performs a filtering process to control the clock oscillation means 11. A phase control signal for phase synchronization control is generated. Based on this phase control signal, an oversampling clock 12 synchronized with the reproduced digital signal 6 is supplied from the clock oscillating means 11 to the analog-to-digital converter 5, so that a PLL 100 capable of phase synchronization pull-in is configured. .

  FIG. 5 shows the configuration of the oversampling phase control means 8. Note that the circuit configuration illustrated in FIG. 5 is an example, and when the device is realized, the circuit configuration may be applied.

  In this oversampling phase control means 8, the output signal of the offset correction means 7 is regenerated as a reproduction signal delay means C 33, a reproduction signal delay means 34, a reproduction signal delay means B 35, and a reproduction signal delay at a timing synchronized with the oversampling clock 12. By means of delay means 33 to 37 connected in series with each other in the order of means 36 and reproduction signal delay means A37, the signals are sequentially delayed and held for each clock. The signals of the reproduction signal delay means C33, the reproduction signal delay means B35, and the reproduction signal delay means A37 are represented as various delay signals of the output signal of the offset correction means 7 as shown in FIG.

  Then, at the timing of the phase reference signal 16 that is the output signal of the phase determining means 15, the output signal of the reproduction signal delay means C33 is held in the reproduction signal holding means C38 to generate a reproduction signal holding output C. Similarly, the reproduction signal holding means B39 holds the output signal of the reproduction signal delay means B35 to generate a reproduction signal holding output B, and the output signal of the reproduction signal delay means A37 is held in the reproduction signal holding means A40 to reproduce the reproduction signal. A holding output A is generated. The reproduction signal holding output C, the reproduction signal holding output B, and the reproduction signal holding output A are signals that change in the same cycle as the channel bit clock 14, as shown in FIG. The reproduction signal holding output C holds a sampling signal of “O” which is a signal of “0” phase “0” of “A0”, “B0”, “C0”, “D0”, “E0”, and reproduction signal holding output B Holds the sampling signal of “●”, which is the phase “π” signal of “A2”, “B2”, “C2”, “D2”, “E2”, and the reproduction signal holding output A is holding the reproduction signal A signal delayed by one channel bit clock of the output C is held. “□” is a signal having a phase position of “π / 2” and “3π / 2”.

  From this relationship, when demodulating digital data, the reproduction signal holding outputs A and C are levels for performing binarization determination at an arbitrary level, which is advantageous when there is a defect that causes a burst-like error. The reproduction signal holding output B is suitable for a discrimination method, and is suitable for a PRML signal processing method that is advantageous for high-density recording / reproduction in the linear direction. Moreover, by performing oversampling, the reproduced signal holding output A and the reproduced signal holding output B are obtained as signals sampled by the same oversampling clock, so that the binarized signal by the PRML signal processing method can be obtained without switching the sampling method. And a binarized signal by the level discrimination method can be obtained simultaneously.

  Next, the polarity reversal detection means 41 in FIG. 5 compares the polarity signal output from the reproduction signal delay means A37 with the polarity signal output from the reproduction signal delay means C33, and when these polarities are different, the zero cross position is detected. A flag indicating that is output. This flag detects polarity inversion of “A0” and “B0” and polarity inversion of “D0” and “E0” in FIG. In addition to this method, there is a method of detecting polarity inversion by “A1” and “A3”, “D1” and “D3”, but it is preferable to select the detection method in consideration of noise tolerance and asymmetry characteristics. . This flag is held by the polarity inversion information holding means 42 at the timing of the phase reference signal 16 to generate zero cross position information A. The zero-cross position information A is a signal that changes in the same cycle as the channel bit clock 14, as shown in FIG.

  In the case of a 4-times oversampling system, the period of the reproduction signal holding output A and the reproduction signal holding output C is separated corresponding to 2π (π is the circumference) which is one period of the channel bit clock 14. . The reproduction signal holding output B reflects the reproduction signal positioned in the middle of the reproduction signal holding output A and the reproduction signal holding output C by a phase π. This is a reference signal for detecting phase error information. By applying this configuration, it is possible to extract phase error information in a short time and with maximum accuracy without losing information of the reproduced digital signal 6.

  FIG. 6 shows the configuration of the operation cycle conversion means 9. The frequency oversampled by this operation cycle conversion means 9 is returned to the same frequency as the original channel bit frequency. This is because the PRML signal processing means 17 and the level discrimination binarization means 18 subsequent to the operation cycle conversion means 9 have no meaning to perform filtering and binarization discrimination unless the channel bit frequency is the original. Note that the circuit configuration illustrated in FIG. 6 is an example, and when the device is realized, the circuit configuration may be applied.

  In this operation cycle conversion means 9, the zero cross position which is the output signal of the oversampling phase control means 8 shown in FIG. 5 is obtained by a shift register 43 A that converts the input signal into a signal that operates at a timing synchronized with the channel bit clock 14. The information A is converted into a zero cross position conversion output. That is, the shift register 43A outputs the input (zero cross position information A) to the shift register 43A as an output signal (zero cross position conversion output) every time the rising edge of the channel bit clock 14 is input, and then the channel bit clock 14 By holding the output signal until the rising edge is input, a zero-cross position conversion output synchronized with the channel bit clock 14 can be obtained. Similarly, the reproduction signal holding output A is changed to reproduction signal conversion output A (second digital data) by the shift register 43B, and the reproduction signal holding output B is changed to reproduction signal conversion output B (first digital data) by the shift register 43C. The reproduction signal holding output C is converted into reproduction signal conversion output C (third digital data) by the shift register 43D. The PRML signal processing means 17 demodulates the reproduction signal conversion output B, and the level discrimination binarization means 18 demodulates the reproduction signal conversion output A or reproduction signal conversion output C.

  When the configuration shown in FIGS. 3 to 6 as described above is applied, it is useless when converting a signal that changes in synchronization with the oversampling clock 12 into a signal that changes in synchronization with the channel bit clock 14. Since the time is lost and the oversampling clock is supplied only to the places where the oversampling clock is required, the increase in the circuit area accompanying the increase in the circuit speed can be minimized, and the conversion efficiency is maximized. A good system can be configured. As for the phase synchronization control means 10, since it operates in synchronization with the channel bit clock, the internal smoothing filter and the clock oscillation means at the next stage can be easily configured.

  FIG. 7 shows the configuration of the phase synchronization control means 10. Note that the circuit configuration illustrated in FIG. 7 is an example, and the circuit configuration may be applied when the device is realized.

  The phase synchronization control means 10 operates at a timing synchronized with the channel bit clock 14. In this phase synchronization control means 10, the operation period shown in FIG. 6 is performed by the switching means 45 in the phase error information detection means 44. When the polarity of the reproduction signal conversion output C, which is the output signal of the conversion means 9, is “positive”, the polarity inversion means for inverting the polarity of the reproduction signal conversion output B as shown in FIG. When the signal output from 46 is selected and the polarity of the reproduction signal conversion output C is “negative”, the reproduction signal conversion output B itself is selected. This reproduction signal conversion output B is indicated by a black circle “●” in FIG.

  Next, only when the mask processing unit 47 in the phase error information detecting unit 44 determines that the zero cross position, that is, the polarity is inverted, is output from the zero cross position conversion output, and corresponds to the rising edge or falling edge of the optical reproduction waveform. In addition, the output signal of the switching means 45 is output as phase error information. The obtained phase error information is indicated by “P1”, “P2”, “P3”, “P4”, “P5” in FIG. 7B. Here, the output signal of the polarity inverting means 46 is selected by the switching means 45 at “P2” and “P4” corresponding to the falling edge.

  The phase synchronization control means 10 performs a filtering process by the loop filter 48 using the phase error information thus detected to generate a phase control signal.

  Here, the loop filter 48 may have an active filter configuration as shown in FIG. In the loop filter 48, phase error information is input to the gain adjusting means 49A and the gain adjusting means 49B to adjust the gains on the proportional term side and the integral term side, respectively. Thereafter, the output signal of the gain adjusting means 49B is input to the integrating means 50 to perform integration processing. The mixing means 51 adds the output signals of the integrating means 50 and the gain adjusting means 49A. Finally, the output signal of the mixing means 51 is configured to generate a phase control signal by the gain adjusting means 49C.

  The phase synchronization control means 10 may be configured as shown in FIG. The operation of this circuit will be described below, but this circuit is an example, and the present invention is not limited to this configuration.

  The phase synchronization control means 10 detects zero-cross position information by the zero-cross position detection means 52 based on the output signal of the over-sampling phase control means 8, and the zero-cross position information and the over-sampling phase by the phase error information detection means 44. Phase error information is detected based on the output signal of the control means 8. Next, using the detected phase error information, the loop filter 48 performs filter processing to generate a phase control signal.

  On the other hand, PRML (Partial Response Maximum Likelihood) signal processing means 17 which is means for estimating the most probable data sequence using intentionally added intersymbol interference based on the output signal of the operation cycle conversion means 9; The digital signal recorded on the optical disk medium is demodulated by the digital data demodulating means 19 having the level discrimination binarizing means 18 that performs binarization and demodulation at the center level where the code balance of the output signal is balanced. The PRML signal processing means 17 outputs the demodulated binarized signal A20, and the level discrimination binarizing means 18 outputs the demodulated binarized signal B21 simultaneously. For this reason, for example, the demodulated binary signal B21 which is strong against scratches is used in an area where the optical disk is scratched, such as scratches or black dots, and the demodulated binary signal A20 is used in other areas. Accordingly, it is possible to properly use two types of demodulated binary signals in real time, and to obtain a high-quality binarized discrimination output.

  More specifically, in the case of PRML signal processing, when a high-order partial response characteristic is used, the discrete signal is digitally equalized to a plurality of levels as shown in the lower part of FIG. Maximum likelihood demodulation is performed in which a reliable sequence is selected and demodulated. In this way, the signal is discriminated after performing equalization on the partial response characteristics that intentionally cause inter-waveform interference, so that the signal quality deteriorates and a reproduced signal with a low S / N ratio or an inter-waveform interference tilt occurs. High-performance demodulation can be performed against deterioration. However, if a state in which the plurality of level distributions cannot be accurately determined due to amplitude fluctuations caused by scratches or the like continues, there is a property that an erroneous sequence is selected and a demodulation error occurs. On the other hand, since the level discrimination is to demodulate the discrete signal shown in the middle of FIG. 18 by determining the positive / negative polarity, the demodulation performance for inter-waveform interference in the linear direction is inferior to that of the PRML signal processing. It has the property of being less susceptible to amplitude fluctuations. Therefore, it is possible to improve the demodulation performance by providing means for detecting an abnormality of the reproduction signal due to a scratch or the like and switching between PRML signal processing and level discrimination.

  This can be realized, for example, by configuring the digital data demodulating means 19 as shown in FIG. In FIG. 10, the demodulated data switching means 19A determines either the demodulated data output from the PRML signal processing means 17 or the demodulated data output from the level discrimination binarizing means 18 from information such as the state of the reproduced signal or the error correction result in the subsequent stage. Is output to the selection means 19B. As the error correction result at the subsequent stage, for example, an output signal 212 from a decoding circuit 202 shown in FIG.

  Next, switching conditions in the demodulated data switching means 19A will be described. The demodulated data switching means 19A compares the level difference between the peak level and the bottom level of the output signal of the analog / digital converter 5, and if the level difference is larger than a predetermined value, amplitude fluctuation due to scratches, dirt or asymmetry occurs. Therefore, the selection unit 19B instructs to select the demodulated data output from the level discrimination binarization unit 18. Alternatively, the peak level and the bottom level of the analog / digital converter 5 are monitored, and the peak level or the bottom level fluctuates in a section determined to be a long mark by, for example, the subsequent decoding circuit (see FIG. 15). In this case, it is determined that the pit formation on the optical disk medium is insufficient due to high-speed recording or the like, and the selection unit 19B instructs to select the demodulated data output from the level determination binarization unit 18. Alternatively, when the selection unit 19B selects the demodulated data output from the PRML signal processing unit 17, if a decoding error occurs in a burst form in the recording code decoding in the subsequent decoding circuit, the amplitude fluctuation occurs. The selection means 19B instructs the selection of the demodulated data output from the level discrimination binarization means 18. Alternatively, when the decoding error exceeds a predetermined number in the recording code decoding in the subsequent decoding circuit, or when the error correction is performed a predetermined number of times or more, the other demodulated data that is not the currently selected demodulated data To select.

  On the other hand, the level discrimination binarization means 18 may be configured as follows. That is, with respect to the reproduction signal conversion output C of the operation cycle conversion means 9 (a part of the PC 101 constituting the PLL 100), “0” is obtained when it is positive, “1” is obtained when it is negative, and the demodulated binary signal. This is output as B21. At that time, in order to match the demodulation timing of the demodulated binarized signal A20, it is effective to delay the demodulated binarized signal B21 by a shift register. As a result, the continuity of the demodulated data is not impaired at any timing, so that no loss of demodulated data occurs when the demodulated binary signal A20 and the demodulated binary signal B21 are switched and reproduced. . Further, the level discrimination binarization means 18 sets “0” as the demodulated binarized signal B21 when the reproduction signal conversion output A of the operation cycle conversion means 9 is positive and “1” when it is negative. You may comprise so that it may output.

  Conventionally, when the digital data demodulating means 19 selects the PRML signal processing means as the demodulating means, the demodulated data cannot be accurately generated by the level discrimination binarizing means 18 unless the sampling method is switched. On the other hand, in the present invention, since the oversampling is performed, the signals necessary for the respective means are simultaneously sampled, and the output can be obtained at the same time with the maximum accuracy. Therefore, it depends on the type, speed, and reproducing method of the optical disk medium. Without having to build and operate the system. In particular, the demodulated binary signal A20 demodulated by the PRML signal processing method effective for high-density recording / reproduction in the line direction, and the level discrimination binary capable of stable reproduction when a burst-like error occurs due to a defect or the like. By using the demodulated binarized signal B21 demodulated by the converting means 18 in real time according to the reproduction state, it becomes possible to improve the reproduction capability for various disks, so-called playability.

  Further, in this system, it is possible to extract highly accurate jitter information 23 by the jitter detection means 22 shown in FIG. Hereinafter, the principle of highly accurate jitter detection will be described with reference to FIG.

  First, the reproduction signal conversion output A, the reproduction signal conversion output B, the reproduction signal conversion output C, and the zero cross position conversion output, which are output signals of the operation cycle conversion means 9, are used as input signals, and the reproduction signal is generated by the zero cross position conversion output. When the conversion output B is determined to be the zero cross position, the absolute value of the difference between the reproduction signal conversion output C and the reproduction conversion output A is calculated. As a result, the instantaneous inclination component shown in FIG. 10 is calculated. This corresponds to a channel bit period when projected in the time direction when the vicinity of the center level of the optical reproduction signal has linearity. When the absolute value of the distance in the amplitude direction from the zero level of the reproduction signal conversion output B at this time is used as the instantaneous amplitude jitter information, if this signal is projected in the time direction, it corresponds to the instantaneous time jitter information. . This leads to the following relationship: The symbol “||” represents an absolute value.

| Instantaneous time jitter information | / | Channel bit period |
= | Instantaneous amplitude jitter information | / | Instantaneous slope component |

Therefore, the jitter information at the zero-cross position can be calculated from the following relationship.
| Reproduction signal conversion output B | / | (Reproduction signal conversion output C) − (Reproduction signal conversion output A) |

  It is possible to extract highly accurate jitter information by performing a smoothing process on the extracted jitter information for each zero cross.

  Therefore, the jitter detection means 22 of FIG. 1 is arranged in the amplitude direction at the zero cross position from the output signal of the reproduction signal holding means B39 and the output signal of the polarity inversion information holding means 42 of FIG. Jitter element detection means 22A for detecting an absolute value component, jitter reference period detection means 22B for calculating the distance in the amplitude direction from the output signal of the reproduction signal holding means A40 and the output signal of the reproduction signal holding means C38, and the jitter element You may comprise as absolute jitter component detection means 22C which detects a jitter component by dividing the output signal of detection means 22A by the output signal of said jitter reference period detection means 22B.

  Further, the offset correction means 7 described above may be configured as shown in FIG. Hereinafter, the operation of this circuit will be described. However, this circuit is an example and is not limited to this circuit.

  In this offset correction means 7, offset level information in the amplitude direction is detected from the output signal of the operation cycle conversion means 9 by the offset level detection means 56, and the offset level information in the amplitude direction is smoothed by the offset level smoothing means 57. Turn into. Next, the subtracting unit 58 subtracts the smoothed offset level information in the amplitude direction from the reproduced digital signal 6 to reduce the offset component in the amplitude direction included in the reproduced digital signal 6.

  Here, the offset level detecting means 56 may be as shown in FIG. Although the operation of this circuit will be described, this circuit is an example and is not limited to this circuit.

  In the offset level detection means 56, the center level fluctuation information detection means 59 outputs the reproduction signal conversion output B when the zero cross position conversion output shown in FIG. 6 is the zero cross position as the center level fluctuation information, The polarity balance calculation means 60 adds “1” when the polarity of the reproduction signal conversion output A and the reproduction signal conversion output C is positive, and adds “−1” when the polarity is negative, and accumulates these pieces of information. . At this time, since the accumulated signal becomes information indicating the balance of the sign polarity of the output signal of the offset correction means 7, the offset information with the sign center level can also be extracted based on the information. Next, the offset information merging means 61 adds the center level variation information and the code polarity balance information at an arbitrary ratio to generate offset level information. Here, the polarity balance calculation means 60 may accumulate the polarity of the reproduction signal holding means obtained at the timing synchronized with the oversampling clock 12 in the channel bit clock 14 of one cycle in order to improve accuracy.

As described above, since the reproduction signal processing apparatus having the configuration shown in FIGS. 1 to 14 uses the multi-bit discrete signal based on the oversampling clock synchronized with the channel bit frequency, the PLL is configured. It is possible to simplify the configuration of the signal processing means, suppress an increase in the delay time of the control loop, and suppress deterioration in the phase lock-in performance. For this reason, the effectiveness of the PRML signal processing method can be exhibited, and stable reproduction can be performed even when reproducing an optical disk with originally poor signal quality or against tilt deterioration. In addition, since the supply destination of the oversampling clock is limited to only necessary portions, an increase in circuit scale and power consumption can be suppressed.
In addition, since a PRML signal processing system effective for high-density recording / reproduction in the linear direction of the disk and a signal of a level discrimination system capable of stable reproduction against a burst error caused by a defect or the like can be obtained at the same time. It is possible to detect the state and instantly switch to the optimum playback method.
Furthermore, the use of the oversampling clock increases the information in the time direction, and the jitter detection accuracy can be improved.

  FIG. 15 shows the configuration of an oversampling type optical recording / reproducing apparatus having this reproduced signal processing apparatus 200. In the figure, an optical disk reproduced signal 210 (FIG. 15) inputted from an optical pickup 201 (corresponding to the optical reproducing means 2 in FIG. 1). 1 corresponds to 73 of 1) and is input to the reproduction signal processing apparatus 200. The reproduction signal processing apparatus 200 has the configuration shown in FIG. 1 and outputs binarized data 211 (corresponding to 20 and 21 in FIG. 1). The decoding circuit 202 demodulates the binarized data 211, extracts the data 213 recorded on the optical disc 1, and outputs the decoding information and error correction information 212 to the reproduction signal processing device 200. The system controller 203 communicates and transfers data with an external device such as a personal computer and controls each block. The system controller 203 outputs the signal 213 demodulated by the decoding circuit 202 and recorded on the optical disk to the external device. Then, a signal to be written to the optical disc is received from the external device. Further, the reproduction signal processing device 200, the decoding circuit 202 and the servo control circuit 204 are controlled by the control signal 208. The reproduction signal processing apparatus 200 demodulates either the PRML signal processing method or the level determination method based on the control signal 208. The servo control circuit 204 performs servo control of the spindle motor 205 that rotates the optical pickup 201 and the optical disc in accordance with the control signal 208.

  As described above, in the oversampling optical recording / reproducing apparatus of FIG. 15, the reproduction signal processing apparatus 200 having the configuration shown in FIGS. 1 to 14 is used. Since the circuit scale and power consumption are small, a high-quality playback signal can be obtained, and the PRML signal processing method and the level discrimination method can be obtained simultaneously as the playback signal, so the optimum playback signal according to the control of the system controller Can be selected. In addition, since the amount of information in the time direction increases, jitter detection accuracy is high, and learning of the cutoff frequency and boost amount in focus servo and waveform degradation can be prevented from converging to optimal values, and playback performance can be reduced. It is possible to suppress deterioration.

  As described above, according to the first embodiment, when demodulating digital data recorded on an optical disc medium, an oversampling clock having a frequency N times the channel bit clock (N is a multiple of 2) is introduced. Since analog-to-digital conversion is performed, the delay time of the PLL can be shortened, and the quality of the reproduced waveform is deteriorated due to the tilt defined by the angle between the vertical axis with respect to the recording surface of the optical disk medium and the incident axis of the laser beam, and the signal to noise ratio Phase synchronization pull-in control is first applied to playback under poor conditions, asymmetry in which the top and bottom of the playback waveform are asymmetric, and local playback characteristics deterioration that depends on defects such as scratches, dirt, and fingerprints on the disk surface. The failure can be prevented, the effectiveness of the PRML signal processing method can be fully exhibited, and the reproduction limit performance can be improved.

  Also, by applying a PRML signal processing method that is advantageous for high recording density reproduction in the linear direction, not only the demodulated data quality is improved more than before, but also the output of the phase comparator constituting the PLL by oversampling. Since the signal necessary to execute the level discrimination method for level discrimination is also obtained at the same time, if burst errors frequently occur due to defects etc., the output of the phase comparator constituting the PLL is leveled. It is also possible to switch in real time to the output signal of the level discriminating method to discriminate, and it is possible to obtain a reproduction signal processing device excellent in versatility and an optical disc recording / reproducing device equipped with the same.

In addition, the oversampling clock is used only in places where an oversampling clock is required, and the low-speed clock converted by the operation cycle conversion means is used in other places. Can be minimized.
Furthermore, since information in the time direction increases, jitter detection accuracy is improved, and learning of focus servo and waveform equalization learning can be optimized.

In the first embodiment, the present invention is applied to an optical disk recording / reproducing apparatus. However, the present invention may be applied to a reproducing system such as a reproduction-only optical disk apparatus or a magnetic disk apparatus.
In addition, although two types of binarized signals are obtained by the PRML signal processing method and the level discrimination method, the binarized signals may be obtained by a method other than the level discrimination method.
Further, the case where the offset correction means 7 is included in the PLL 100 has been described as an example. However, as shown in FIG. 16, the offset correction means is not included in the PLL, and the output signal of the analog / digital converter 5 is directly oversampled by the oversampling phase control means 8. It is also possible to implement it by inputting to. At this time, the offset correction means may correct the offset with respect to the analog signal before being sampled by the analog / digital converter 5.

Further, as shown in FIG. 7A, the phase synchronization control means 10 does not include the zero cross position detection means, but the polarity determination detection means and the polarity inversion information holding means corresponding to the zero cross position detection means are oversampling phase. Although what was provided in the control means 8 was shown, these may be provided in another circuit block and may be provided in the phase synchronization control means 10.
Further, the zero cross position detection means may be realized by means other than the polarity determination detection means and the polarity inversion information holding means.

  As described above, the reproduction signal processing apparatus and the optical disk apparatus according to the present invention can shorten the delay time of the PLL by using the oversampling clock synchronized with the channel bit signal as the reproduction clock, and can achieve high recording density reproduction in the line direction. The output signal of the advantageous PRML signal processing system is not only improved more than before, but also two types of binarized signals by the PRML signal processing system and the level discrimination system can always be obtained. These can be switched and used as necessary, which is useful for improving the playability of the optical disc apparatus.

It is a block diagram which shows the structure of Embodiment 1 of the reproduction | regeneration signal processing apparatus of Claim 1 thru | or 18 by this invention. It is explanatory drawing of the frequency characteristic of a high-order icicle filter. It is a figure which shows the block diagram of the phase determination means 15 in Embodiment 1, and the timing chart of the signal of each part. FIG. 4 is a diagram showing an operation principle of oversampling phase control means 8 in Embodiment 1 and a timing chart of signals at each part thereof. 3 is a block diagram showing a configuration of oversampling phase control means 8 in Embodiment 1. FIG. 3 is a block diagram illustrating a configuration of an operation cycle conversion unit 9 according to Embodiment 1. FIG. FIG. 3 is a block diagram showing a configuration of phase synchronization control means 10 in the first embodiment. It is a figure which shows the detection principle of the phase error information of the phase-synchronization control means 10 in Embodiment 1. FIG. 3 is a block diagram showing a configuration of a loop filter 48 in the first embodiment. FIG. 3 is a block diagram showing a configuration (application example) of phase synchronization control means 10 in Embodiment 1. FIG. FIG. 3 is a block diagram showing a configuration of digital data demodulation means 19 in the first embodiment. 4 is an explanatory diagram illustrating a principle of detecting jitter information by a jitter detecting unit 22 according to Embodiment 1. FIG. FIG. 3 is a block diagram showing a configuration of jitter detection means 22 in the first embodiment. FIG. 3 is a block diagram showing a configuration of offset correction means 7 in the first embodiment. 3 is a block diagram showing a configuration of offset level detection means 56 in Embodiment 1. FIG. It is a block diagram which shows the structure of Embodiment 1 of the oversampling type | mold optical recording and reproducing apparatus of Claim 19 by this invention. FIG. 10 is a block diagram showing another configuration of the reproduction signal processing apparatus 200 according to Embodiment 1. It is a block diagram which shows the structure of the conventional optical disk reproducing | regenerating apparatus. It is explanatory drawing which shows the recording data of the conventional optical disk reproducing | regenerating apparatus, and the output signal waveform in each functional block.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk medium 2 Optical reproduction | regeneration means 3 Preamplifier 4 Waveform equalization means 5 Analog / digital converter 6 Reproduction digital signal 7 Offset correction means 8 Oversampling phase control means 9 Operation cycle conversion means 10 Phase synchronization control means 11 Clock oscillation means 12 Oversampling Clock 13 Clock dividing means 14 Channel bit clock 15 Phase determining means 16 Phase reference signal 17 PRML signal processing means 18 Level discrimination binarizing means 19 Digital data demodulating means 20 Demodulated binary signal A
21 Demodulated binary signal B
22 Jitter detection means 23 Jitter information 24 Edge detection means 25 Shift register B
26 Inverter 27 Periodic signal 28 Reference flag generating means 29A to 29C Shift register A
30 Exclusive OR (EXOR)
31 reference flag 32 reference flag delay means 33 reproduction signal delay means C
34 reproduction signal delay means 35 reproduction signal delay means B
36 Reproduction signal delay means 37 Reproduction signal delay means A
38 Reproduction signal holding means C
39 Reproduction signal holding means B
40 Reproduction signal holding means A
41 polarity inversion detection means 42 polarity inversion information holding means 43A, 43B, 43C, 43D shift register 44 phase error detection means 45 switching means 46 polarity inversion means 47 mask processing means 48 loop filters 49A, 49B, 49C gain adjustment means 50 integration means 51 Mixing means 52 Zero cross position detecting means 56 Offset level detecting means 57 Offset level smoothing means 58 Subtracting means 59 Center level fluctuation information detecting means 60 Polarity balance calculating means 61 Offset information merging means 62 VCO
100 PLL
101 PC
200 reproduction signal processing device 201 optical pickup 202 decoding circuit 203 system controller 204 servo control circuit 205 spindle motor

Claims (19)

The reproduction waveform obtained by reading out the digital signal recorded on the information recording medium by the information reproducing means is over synchronized with the frequency corresponding to N times the frequency of the channel bit clock of the digital signal (N is a multiple of 2 or more). Oversampling phase synchronization that converts a multi-bit discrete signal with a sampling clock and generates first, second, and third digital data having different phases synchronized with the frequency of the channel bit clock from the multi-bit discrete signal Means,
A first demodulator for demodulating the first digital data; and a digital data demodulator having a second demodulator for demodulating the second digital data or the third digital data.
A reproduction signal processing apparatus. The reproduction waveform obtained by reading out the digital signal recorded on the information recording medium by the information reproducing means is over synchronized with the frequency corresponding to N times the frequency of the channel bit clock of the digital signal (N is a multiple of 2 or more). Oversampling phase synchronization that converts a multi-bit discrete signal with a sampling clock and generates first, second, and third digital data having different phases synchronized with the frequency of the channel bit clock from the multi-bit discrete signal Means,
Jitter detection means for detecting a jitter component of the reproduced waveform using the first, second and third digital data,
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 1 or 2,
The oversampling phase synchronization means includes
Analog-to-digital conversion means for converting the reproduced waveform into the multi-bit discrete signal with the oversampling clock;
Clock dividing means for generating a channel bit clock by dividing the oversampling clock by N;
Phase determining means for uniquely determining the phase relationship between the channel bit clock and the oversampling clock;
Oversampling phase control means for converting the output signal of the analog / digital conversion means into a pre-demodulation processing signal and a control signal based on the output signal of the phase determination means;
An operation period converting means for converting an output signal output from the oversampling phase control means that is output in synchronization with the oversampling clock into a signal that operates in synchronization with the channel bit clock;
The oversampling clock generated by the clock oscillating means is operated so as to operate in synchronization with the channel bit clock, detect phase error information from the output of the operation period conversion means, and approach the phase error information to zero. A phase synchronization control means for modulating,
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 3,
The phase determining means includes
Edge generating means for generating a signal necessary for detecting either a rising edge or a falling edge of the channel bit clock;
Reference flag generating means for generating a reference flag for a signal output by the edge generating means at a timing synchronized with the oversampling clock;
Reference flag delay means for delaying the reference flag by an arbitrary clock of the oversampling clock and generating a phase reference signal for uniquely determining the phase relationship between the channel bit clock and the oversampling clock; Have
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 3,
The oversampling phase control means includes
A plurality of reproduction signal delay means for delaying and holding the output signal of the analog-digital conversion means at a timing synchronized with the oversampling clock;
A plurality of reproduction signal holding means for holding the output signals of the plurality of reproduction signal delay means at the timing of the phase reference signal generated by the phase determination means;
Polarity inversion detection means for determining whether or not the polarity is inverted with respect to two predetermined output signals in the output signals of the plurality of reproduction signal delay means;
Polarity inversion information holding means for holding the output signal of the polarity inversion detection means at the timing of the phase reference signal.
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 5, wherein
The plurality of reproduction signal delay means include
Reproduction signal delay means A for outputting a reproduction signal positioned at a phase separated by a predetermined amount of phase from the reference phase of the channel bit clock whose period is represented by 2π (π is a pi), and the reproduction signal delay means A The reproduction signal delay means C for outputting a reproduction signal positioned at a phase 2π away from the reproduction signal delay means C, the reproduction signal delay means A, and the reproduction signal delay means C are intermediate between the reproduction signal delay means A and a phase separated by π. A reproduction signal delay means B for outputting a reproduction signal positioned;
The plurality of reproduction signal holding means include
Reproduction signal holding means A, B, C for holding the output signals of the reproduction signal delay means A, B, C at the timing of the phase reference signal, respectively,
The polarity inversion detection means includes
Based on the output signals of the reproduction signal delay means A and C among the plurality of reproduction signal delay means, it is determined whether or not the polarity is inverted,
The basic signal for detecting phase error information from the output of the oversampling phase control means is:
Output by the reproduction signal holding means B;
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 6, wherein
The reproduction signal delay means A outputs a reproduction signal corresponding to a phase zero of the channel bit clock whose period is expressed by 2π (π is the circumference) among the plurality of reproduction signal delay means. Yes,
The reproduction signal delay means C outputs a reproduction signal corresponding to the phase 2π of the channel bit clock among the plurality of reproduction signal delay means,
The reproduction signal delay means B outputs a reproduction signal corresponding to the phase π of the channel bit clock among the plurality of reproduction signal delay means.
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 3,
The phase synchronization control means includes
Zero-cross position detecting means for detecting zero-cross position information of the output signal of the oversampling phase control means;
Phase error information detection means for detecting phase error information between the zero-cross position information and the output signal of the oversampling phase control means;
A loop filter for smoothing the phase error information,
It operates in synchronization with the period of the oversampling clock,
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 8, wherein
The phase error information detection means includes
The polarity inversion detection means according to claim 6 determines that the polarities of the output signals of the reproduction signal delay means A and C among the plurality of reproduction signal delay means have been inverted, and the rising edge of the optical reproduction waveform Or if a falling edge is detected,
The polarity of the output signal of the reproduction signal holding means B among the plurality of reproduction signal holding means is controlled and detected as phase error information.
A reproduction signal processing apparatus. The reproduction signal processing device according to claim 2,
First demodulation means for demodulating the first digital data;
An information processing apparatus, further comprising a digital data demodulating means comprising a second demodulating means for demodulating the second digital data or the third digital data. The reproduction signal processing device according to claim 1 or 10,
The digital data demodulating means includes
As the first demodulating means, PRML (Partial Response Maximum Likelihood) signal processing means for estimating the most probable data sequence using the intersymbol interference intentionally added to the output signal of the operation period converting means. ,
As the second demodulating means, each has a level discriminating binarizing means for binarizing the output signal based on a center level where the code balance of the output signal of the operation cycle converting means is taken, and performing digital data demodulation,
Both operate in synchronization with the channel bit clock.
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 11, wherein
The PRML signal processing means includes:
Data is demodulated with respect to a signal obtained by converting the operation cycle of the output signal of the reproduction signal holding unit B according to claim 6 by the operation cycle conversion unit.
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 11, wherein
The level discrimination binarization means includes:
The data is demodulated with respect to the binarized preprocessed signal obtained by converting the operation cycle of one of the output signals of the reproduction signal holding means A or C according to claim 6 by the operation cycle conversion means. ,
A reproduction signal processing apparatus. The reproduction signal processing device according to claim 1 or 10,
The digital data demodulating means includes
Further comprising demodulated data switching means and selection means,
The selection means selects an output signal of the first demodulation means or the second demodulation means according to a selection signal of the demodulation data switching means, and outputs it as demodulation data.
A reproduction signal processing apparatus. The reproduction signal processing apparatus according to claim 3,
The oversampling phase synchronization means includes
An offset correction means for reducing an offset component in an amplitude direction from the multi-bit discrete signal and outputting the reduced component to the oversampling phase control means;
A reproduction signal processing apparatus. The reproduction signal processing device according to claim 15, wherein
The offset correction means includes
Offset level detecting means for detecting offset level information in the amplitude direction from the output signal of the oversampling phase control means;
Offset level smoothing means for smoothing the offset level information in the amplitude direction;
Offset level subtracting means for reducing the offset component by subtracting the output signal of the offset level smoothing means from the multi-bit discrete signal,
A reproduction signal processing apparatus. The reproduction signal processing device according to claim 16, wherein
The offset level detection means includes
A center level fluctuation information detecting means for detecting fluctuation information of the center level of the reproduction signal from output signals of the reproduction signal holding means B and the polarity inversion detection means among the plurality of reproduction signal holding means according to claim 6. ,
Polarity balance calculation means for detecting polarity balance information by accumulating polarity information from an output signal corresponding to one period of the channel bit clock among the output signals of the plurality of reproduction signal holding means;
Offset information fusion means for detecting an offset level by adding the center level variation information and the polarity balance information at a predetermined ratio;
A reproduction signal processing apparatus. The reproduction signal processing device according to claim 2,
The jitter detection means includes
Jitter element detection means for detecting an absolute value component in the amplitude direction at the zero cross position from the output signals of the reproduction signal holding means B and the polarity inversion detection means among the plurality of reproduction signal holding means according to claim 6;
Jitter reference period detection means for calculating a distance in the amplitude direction from the output signals of the reproduction signal holding means A and C among the plurality of reproduction signal holding means;
Absolute jitter component detection means for detecting a jitter component by dividing the output signal of the jitter element detection means by the output signal of the jitter reference period detection means,
A reproduction signal processing apparatus. A spindle motor that rotates the optical disc;
An optical pickup for reading a reproduction signal from the optical disc;
The reproduction signal processing device according to any one of claims 1 to 18, which processes the reproduction signal read by the optical pickup;
A decoding circuit that demodulates the signal processed by the reproduction signal processing device and performs error processing;
A servo control circuit for controlling the spindle motor and the optical pickup;
In addition to performing data communication with the outside, it has a system controller that controls each functional block.
An optical disc device characterized by the above.

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