JP3428525B2 - Recorded information playback device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recorded information reproducing apparatus, and more particularly to a recorded information reproducing apparatus for reproducing a recorded information signal on an optical disc.

[0002]

2. Description of the Related Art Conventionally, crosstalk removal is performed based on signals reproduced by separate beams from three adjacent tracks of an optical disc on which high density recording is performed, and reproduction with a good S / N ratio is performed from a central track. Although various recording information reproducing apparatuses by the three-beam method for obtaining a signal have been proposed, it is possible to remove the crosstalk of the reproduced signal without recording a preamble signal for removing the crosstalk in advance. There is known a recorded information reproducing apparatus using a three-beam method in which the recording capacity is improved (Japanese Patent Laid-Open No. 9-
320200).

In this conventional recording information reproducing apparatus, a first read signal reproduced by one beam from any one track of an optical disk and two beams adjacent to both sides of the one track are separated from each other. By sampling the two second read signals reproduced by
And a second sample value series, a crosstalk component is obtained from the second sample value series by a variable coefficient filter, the crosstalk component is subtracted from the first sample value series by a subtracter, and The zero-cross sample extracting means extracts a zero-cross sample value from the output sample value series of the subtractor, and the filter coefficient calculating means updates the filter coefficient of the variable coefficient filter so that the zero-cross sample value converges to zero. In addition, the determination means determines the reproduction signal from the output sample value series of the subtractor.

[0004]

However, in the above-mentioned conventional recording information reproducing apparatus, the LMS adaptive algorithm is used to update the filter coefficient of the variable coefficient filter so that the error signal becomes zero. The above-mentioned error signal is only the zero-cross sample value extracted from the output sample value series of the subtractor, and there is a problem that convergence is slow and misjudgment is large. In addition, since partial response equalization is not performed, Viterbi decoding cannot be performed, and there is a high possibility that data restoration of a reproduction signal with a low S / N read from an optical disc that tends to be recorded with higher density is erroneous. is there.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a recorded information reproducing apparatus which can reproduce recorded information on a recording medium with a fast convergence and surely.

Another object of the present invention is to provide a recorded information reproducing apparatus capable of reproducing reproduced information of a high density recorded recording medium accurately by using partial response equalization.

Still another object of the present invention is to provide a recorded information reproducing apparatus which can operate with a low frequency clock.

Still another object of the present invention is to provide a recorded information reproducing apparatus which can realize crosstalk cancellation with a simple structure.

[0009]

In order to achieve the above object, the first invention is a first information read from any one record information recording track to be reproduced in a record information recording track group on a recording medium. Reproduction signal and the second and third read separately from two adjacent recording information tracks on both sides of any one recording information recording track to be reproduced.
Reading means for obtaining the reproduced signal of, and A / D conversion means for separately converting the first to third reproduced signals into digital signals and outputting the first to third digital reproduced signals,
The digital data sampled at a desired bit rate with respect to the first digital reproduction signal is generated by performing resampling (decimation interpolation), a bit clock is generated, and the zero level of the first digital reproduction signal is detected. Re-sampling operation phase locked loop circuit for outputting zero point information, first to third transversal filters, delay circuit, provisional discrimination means, and first
To a third coefficient generating means, a resampling means, and a subtraction circuit.

Here, the above-mentioned first transversal filter waveform-equalizes the output digital data of the resampling operation phase locked loop circuit based on the first filter coefficient. The delay circuit described above outputs zero point information at least three consecutive zero points. The above-mentioned provisional discrimination means is a PR indicating the type of partial response equalization.
The mode signal, the RLL mode signal indicating the type of run length limited code of the reproduction signal, the plurality of zero point information from the delay circuit, and the waveform equalized reproduction signal are received as inputs, and the PR mode signal and the RLL mode signal are received. Based on the state transition determined by and the pattern of multiple zero point information,
The temporary discriminant value of the waveform equalized signal is calculated, and the difference value between the temporary discriminant value and the reproduced signal after waveform equalization is output as an error signal.

Further, the first coefficient generating means variably controls the first filter coefficient on the basis of the output error signal of the temporary discriminating means so that the error signal is minimized. The resampling means separately performs resampling operation on the second and third digital reproduced signals from the A / D converting means based on the output bit clock of the resampling operation phase locked loop circuit, and then first and second 2 sampling signals are output. The second and third transversal filters are
The first and second sampling signals are separately filtered based on the second and third filter coefficients, respectively, and two recording information tracks adjacent to both sides of any one recording information recording track to be reproduced. The first and second pseudo crosstalk signals corresponding to the read signal of 1 are separately output. The second and third coefficient generation means variably control the second and third filter coefficients separately based on the output error signal of the temporary discrimination means. The subtraction circuit subtracts the first and second pseudo crosstalk signals from the output signal of the first transversal filter, and outputs a reproduced signal after waveform equalization.

According to the first aspect of the invention, the temporary discrimination means performs the temporary discrimination (convergence target setting) on the premise of partial response equalization, and the temporary discrimination value and the waveform-equalized reproduced signal extracted from the subtraction circuit. 1st difference value as error signal
Through the supply to the third filter coefficient generating means so that the error signal becomes 0, the operation of the device can be converged toward a clear value. Further, a resampling calculation phase locked loop circuit can be used.

[0013]

Further, in order to achieve the above object, the second invention is a zero detector which receives the output signal after waveform equalization of the subtraction circuit and detects the zero point information of the waveform equalized reproduction signal. And a delay circuit delays the zero point information from the zero detector .

In order to achieve the above-mentioned object, the third invention inputs the output signal after waveform equalization of the subtraction circuit, and outputs a natural number multiple of the bit clock based on the waveform equalized reproduction signal. A phase-locked loop circuit for generating a system clock of a frequency is provided, and the resampling calculation phase-locked loop circuit and the resampling means in the first invention are deleted, and the first to third digital reproduction signals from the A / D conversion means are provided. Are separately supplied to the first to third transversal filters, and the delay circuit delays the zero point information output from the phase comparator in the phase locked loop circuit.

Further, in order to achieve the above-mentioned object, a fourth invention is a phase locked loop circuit for generating a system clock having a frequency which is a natural multiple of the bit clock based on the first reproduction signal from the reading means. , A zero detector for detecting zero point information of the first digital reproduction signal taken out from the A / D conversion means, and the resampling operation phase locked loop circuit and the resampling means in the first invention are deleted. First to third from A / D conversion means
The digital reproduction signal of (3) is separately supplied to the first to third transversal filters, and the delay circuit delays the zero point information from the zero detector.

[0017]

Further, in order to achieve the above object, a fifth
According to the invention of claim 1, the provisional discrimination means in the first invention uses a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limited code of the reproduction signal, and a plurality of zero points from the delay circuit. Information and a reproduction signal after waveform equalization are received as an input, and the target value of the reproduction signal after waveform equalization is obtained based on the state transition determined by the PR mode signal and the RLL mode signal and a pattern of a plurality of zero point information. The temporary discriminant circuit for calculating the temporary discriminant value and the subtractor for outputting the difference value between the temporary discriminant value and the reproduction signal after waveform equalization as an error signal are provided. Error signal that is input to the first input terminal and the temporary determination value output from the temporary determination circuit is the second determination value.
An error selection circuit for selecting and outputting only an effective component of the error signal according to the provisional discriminant value is provided to the input terminal of the output terminal, and the second and third coefficient generation means are output from the error selection circuit. The second and third based on the error signal
The filter coefficient is separately variably controlled.

According to the present invention, of the output error signals of the temporary discriminating means, the signal indicating an uncertain error value temporarily discriminated as the target value farthest from the zero point by the error selection circuit is invalidated (replaced with 0). Since only the correct error signal is extracted as an effective component, the second and third filter coefficients of the second and third transversal filters for generating pseudo crosstalk are generated based on only accurate data. A filter coefficient of 3 can be generated.

Further, in order to achieve the above object, a sixth
In the invention, the error signal output from the subtractor is input to the first input terminal of the error selection circuit, and the resampling operation phase locked loop circuit is locked to the second input terminal of the error selection circuit. Equivalent to the power zero-cross point,
Enter zero point information that indicates when the sample points formed by resampling are present,
Select the error signal to be input to the first input terminal only at the sample point indicated by the zero point information, or at the sample point indicated by the zero point information and the sample points immediately before and after it, and invalid the error signal at other sample points. In the seventh invention, the reproduced signal after waveform equalization output from the subtraction circuit is input to the first input terminal of the error selection circuit, and the temporary discrimination value input to the second input terminal is input. Resampling operation of the reproduced signal after waveform equalization according to the above, only the effective component of the sample point corresponding to the zero-cross point to be locked by the phase-locked loop circuit is selected and output, and waveform equalization is performed at other sample points. The configuration is such that the post-reproduction signal is invalidated. Further, in order to achieve the above object, an eighth invention inputs a reproduction signal after waveform equalization to a first input terminal of an error selection circuit and inputs the above zero point information to a second input terminal. However, the configuration is such that the reproduced signal after waveform equalization input to the first input terminal is selected only at the sample points indicated by the zero point information, and the reproduced signal after waveform equalization is invalidated at other sample points. Is.

In each of the sixth, seventh and eighth inventions, as in the fifth invention, a signal indicating an uncertain error value is invalidated by an error selection circuit, and a reliable error signal or this error signal is generated. Since only the reproduced signal after waveform equalization having substantially the same value as is extracted as the effective component, the filter coefficients of the second and third transversal filters for generating pseudo crosstalk are generated based on only accurate data. Certain second and third filter coefficients can be generated.

Further, in order to achieve the above object, the first
According to the invention of No. 0, a first memory for writing digital data taken out from a digital operation phase locked loop circuit, reading the digital data, and outputting the digital data to a first transversal filter; Two sampling signals are written separately and then read out and output separately to the second and third transversal filters, and the first to third memories each have a bit. The writing operation is performed at the timing of the clock, and the reading operation is performed at the timing of the newly generated clock.

According to the present invention, the frequency of the new clock can be made lower than the master clock frequency, and by performing the operation of the subsequent stage with this new clock frequency, the operation time can be increased and the latches and the like can be reduced. be able to.

In order to achieve the above object, the eleventh invention
Ming, the reading means in the first aspect of the present invention outputs only the first reproduction signal, the A / D converting means outputs only the first digital reproduced signal, and is removed from the structure of the resampling means, resampling operation Extracted from phase locked loop circuit
Delay means for generating first to third digital data having a time relationship different from each other by about one track scanning period based on the digital data thus obtained, and the first to third digital data extracted from the delay means The first digital data having the minimum delay time and the third digital data having the maximum delay time are supplied to the second and third transversal filters, and the second digital data is supplied to the first digital data.
It is configured to supply to the transversal filter of. The twelfth invention is the third or fourth invention.
And has the same configuration as that of the above eleventh invention.
It

In the present invention, since the signal equivalent to the crosstalk signal obtained from the adjacent tracks on both sides of the track to be scanned by using three beams can be obtained by using the delay means, the resampling means can be eliminated. You can

[0026] In addition, in order to achieve the above object, the first
3 of invention, the reading means in the first aspect of the present invention outputs only the first reproduction signal, the A / D converting means outputs only the first digital reproduced signal, and is removed from the structure of the resampling means, Li From sampling operation phase locked loop circuit
First memory and the reproduction signal after the waveform equalization from the decoded data obtained by Viterbi decoding, each one track scanning period with respect to daisy barrel data output from the first memory for delaying the digital data extracted A first memory that is delayed by about one degree and a second memory that generates second decoded data that is advanced by about one track scanning period are provided .
The digital data output from the memory is supplied to the first transversal filter, and the first and second decoded data are supplied to the second and third transversal filters. The 14th aspect of the invention is
3 or 4th invention WHEREIN: The structure similar to 13th invention
It is what

According to the present invention, the 1-bit Viterbi decoded data having a smaller number of bits than the normal sampling data is written in and read from the first and second memories for generating the pseudo crosstalk signal. ,
The memory capacity of the first and second memories can be minimized.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a recorded information reproducing apparatus according to the present invention. In this embodiment, a known three-beam method is used in which three beam spots are separately formed on three adjacent recording tracks of an optical disc as an example of a recording medium. That is, as shown in FIG. 2, when a recording information signal is reproduced from an arbitrary track Ti of an optical disc in which one track is formed per rotation, a reproduction-only optical beam spot B0 is formed on the track Ti. , The inner track Ti of the tracks Ti-1 and Ti + 1 adjacent to both sides of the track Ti
A beam spot B1 is formed at -1, and the outer track Ti
A beam spot B2 is formed at +1.

These three beam spots B0, B1,
B2 keeps the state in which the beam spot B1 is located at the rear position (or the front position) and the beam spot B2 is located at the front position (or the rear position) in the rotation direction of the optical disc with the central beam spot B0 as the center. Tracking is well known. The light reflected by these three beam spots B0, B1, and B2 is converted into a read signal through separate well-known optical systems.

Of the above-mentioned read signals, the read signal of the central track Ti to be reproduced is supplied to the A / D converter 11 of FIG. 1, and the read signal of the inner peripheral side adjacent track Ti-1 is shown in FIG. The read signal of the adjacent track Ti + 1 on the outer peripheral side is supplied to the A / D converter 13 of FIG. The A / D converters 11, 12 and 13 sample the input read signals by the master clock and convert them into digital signals, and the AGC / ATC circuits 14 and 1 at the next stage.
5 and 16 to perform automatic amplitude control (AGC) in which the amplitude is controlled to be constant and automatic threshold control (ATC) in which the threshold of the binary comparator is appropriately controlled by direct current (DC).

The output signal of the AGC / ATC circuit 14 is supplied to the resampling DPLL 17. The resampling DPLL 17 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block, and resampling (thinning-out interpolation) of digital data sampled at a desired bit rate with respect to an input signal.
It is calculated and generated, and is supplied to the transversal filter 21 through the delay adjuster 20. Also, resampling D
The PLL 17 detects that the read signal crosses the zero level, and supplies the 0-point information obtained thereby to the tap delay circuit 32 described later through the delay adjuster 22.

Further, the resampling DPLL 17 generates a bit clock BCLK for bit sampling, and also generates a parameter T_ratio indicating a ratio to be internally divided for resampling operation, which is sent to resampling circuits 18 and 19. Each of them is supplied and the digital signals from the AGC / ATC circuits 15 and 16 are resampled by the bit clock BCLK at the ratio indicated by the parameter T_ratio. The bit clock BCLK is a missing clock (Punctured Clock). The 0-point information indicates the point at which the bit sampling data crosses the zero level in bit clock units.

The signals respectively taken out from the resampling circuits 18 and 19 are supplied to the transversal filters 25 and 26 through the delay adjusters 23 and 24.
The transversal filter 21 and the transversal filters 25 and 26 described above receive filter coefficients (tap coefficients) from multipliers / low-pass filters (LPFs) 27, 28 and 29, respectively, and perform filtering processing of characteristics corresponding to them. Perform on the input signal.

The transversal filter 21 performs waveform equalization processing based on the tap coefficient (filter coefficient) from the multiplier / LPF 27, and intersymbol interference with signals before and after the read signal from the desired track to be reproduced. Reduce the effect of. The read signal after the output waveform equalization of the transversal filter 21 is supplied to the tentative discrimination circuit 33 through the subtractors 30 and 31 described later, where the delay signal from the tap delay circuit 32 and the type of partial response (PR) are supplied. And the RLL mode signal indicating the run length limited code length (minimum inversion interval or maximum inversion interval) of the signal recorded on the optical disc are input, and the temporary determination result is output based on these.

The tentative discrimination result and the input signal of the tentative discrimination circuit 33 (the output signal of the subtractor 31) are subtracted in the subtractor 34, and the difference value thereof is used as an error signal in the inverter 35.
After the polarity is inverted at, it is supplied to the multiplier / LPF 27, where it is multiplied by the tap output of the transversal filter 21 to detect the correlation, and integrated by the LPF. The output integrated value of the multiplier / LPF 27 is input to the transversal filter 21 as a filter coefficient (tap coefficient) of the transversal filter 21 that makes the value of the error signal 0.

The transversal filter 21, the multiplier / LPF 27, the temporary discrimination circuit 33, and the tap delay circuit 3 described above.
The feedback loop including the subtractor 34 and the inverter 35 is based on the well-known LMS algorithm, but the tentative discrimination circuit 33 is a circuit proposed by the present inventor, and tentatively based on partial response equalization. Determine (set convergence target).

Here, to further explain the partial response (PR) characteristic, for example, PR (a, b, b,
When the characteristic of a) is added to a solitary wave and equalized, the equalized waveform is (0, a, a + b, 2a, 2b, a + 2b, 2a + 2) in the case of (1,7) RLL, as is well known.
Takes 7 values of b. When these 7 values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are constrained by the past signal, and this (1,7)
It is known that the state transition diagram as shown in FIG. 3 can be expressed by utilizing the fact that the input signal "1" does not last twice or more by the RLL.

In FIG. 3, S0 to S5 indicate a state determined by the immediately preceding output value. From this state transition diagram, for example, when the input value is a + 2b, the output value becomes 1 and the state transitions to state S3 when the input value is a + 2b, and when the input value is 2b, the output value becomes 1 and the state transitions to state S4. However, it turns out that the other input values are not input, and if they are input, it is an error.

Here, the value Z of the 0 point information is "
1 "indicates a zero cross point, which is represented by a value" a + b "in the state transition diagram of PR (a, b, b, a) shown in FIG.
This occurs in the process of transitioning to → S2 or state S4 → S5. In this case, the states S2, S3, and S4 in the right half of FIG. 3 have positive values (a + b = 0 when normalized to a + b = 0).
+ 2b, 2a + 2b, or 2b), and the states S5, S0, and S1 in the left half are negative values (a + b = 0).
In the case of normalization to 0, any of 0, a, and 2a) is traced, so that it is possible to determine whether the route is a positive route or a negative route by referring to the value before or after the zero cross point.

Moreover, if the interval from one zero cross point to the next zero cross point is known, that is, from the state S2 to the state S5, or from the state S5 to the state S.
If the number of transitions up to 2 is known, the route is determined, and the possible values become clear for each sample point.

Further, in the above state transition diagram, when the value is other than "a + b", that is, when it is not the zero cross point, the value Z of the 0 point information is "0". From this state transition diagram, two zero cross points (Z = 1) are not consecutively taken out, and in the case of RLL (1, X), at least one "1" is provided between adjacent Z = 1. 0 ”exists (when the value Z of the 0 point information changes from 1 → 0 → 1; that is, when the state S1 → S2 → S4 → S5 or the state S4 → S5 → S1 → S2 transits). In addition,
In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1.

In the actual signal, due to the influence of noise and the like,
It is quite possible that the detection of the zero-cross point itself will be erroneous, but in the case of feedback control, if the probability of being able to make a correct decision exceeds the probability of erroneous, it should converge in the correct direction, and it is also sufficient. Because of the integration process,
Single-shot noise is considered to be practically no problem.

Focusing on the above points, the provisional discrimination circuit 33 discriminates the value Z of the 0-point information input from the tap delay circuit 32 at each cycle of the bit clock, and the five values of the continuous 5 clock cycles are identified. Whether it is all "0", only the first value among the above five values is "1", only the last value among the above five values is "1",
It is determined whether the first and last values of the above five values are "1" and the remaining three values are "0".

In these patterns, when the value Z of the 0-point information of interest is "0", the value Z of the 0-point information on both sides is "0". At this time, the signal waveform is Since it is the case of sticking to the positive side or the negative side, a large value P1 is calculated when either of these patterns is satisfied.

If none of the above patterns,
Value 0 of 5 0 point information in 5 consecutive clock cycles
Is "01010", and in the case of this pattern, it is determined based on the RLL mode signal whether the partial response equalization of RLL (1, X) is performed. Since this pattern may occur only at RLL (1, X), a small value P2 is calculated at RLL (1, X).

When the value Z of the five 0-point information in five consecutive clock cycles is not "01010", those five
The value Z of one 0 point information is "01001", "100"
It is determined whether the pattern is any one of 10 "," 00010 ", and" 01000 ". For these four patterns, the value Z of the 0 point information of interest is" 0 ".
Then, one of the values Z of the 0-point information adjacent on both sides is “1”. When it is one of the four patterns, or "01010", and R
When it is determined that the LL mode is not (1, X), P
An intermediate level value P3 of 1 and P2 is calculated.

When the values P1, P2 or P3 are calculated, if the waveform equalized signal at the current time input to the temporary discrimination circuit 33 is 0 or more, the final temporary determination level Q is P1 at that time.
When the value is P2 or P3, and the value is negative, the final provisional determination level Q is inverted in polarity from the value of P1, P2, or P3 at that time. If none of the above, the final provisional determination level Q is set to 0.

As described above, the provisional discrimination circuit 33 outputs the PR mode signal indicating the type of partial response equalization, the RLL mode signal indicating the type of run length limited code of the reproduction signal, and the plurality of tap delay circuits 32. The zero point information and the output signal after the waveform equalization of the subtractor 31 are received as inputs, and the waveform equalization signal is obtained based on the state transition determined by the PR mode signal and the RLL mode signal and a plurality of zero point information patterns. The tentative discrimination level Q of is calculated. This tentative decision level Q is supplied to the subtractor 34 of FIG. 1 as a target value, and the difference from the waveform equalized reproduction signal which is an actual signal is taken to be an error signal.

On the other hand, the signals extracted from the resampling circuits 18 and 19 of FIG.
A fixed delay is given by 3 and 24, and the time is roughly adjusted with pseudo crosstalk, which will be described later, and is input to the transversal filters 25 and 26. The transversal filters 25 and 26 have tap coefficients (filter coefficients).
The multipliers / LPFs 28 and 29 for supplying the
The error signal output from the signal No. 4 is input, where it is multiplied by the tap outputs of the transversal filters 25 and 26 to extract the correlation between adjacent track signals, and the correlation value is L
It is integrated by PF and input to the transversal filters 25 and 26.

In this way, the tap coefficients (filter coefficients) of the transversal filters 25 and 26 are updated according to the correlation value of the adjacent track signals, and the inner and outer circumference sides of the transversal filters 25 and 26 are changed. A pseudo crosstalk signal corresponding to the read signal from each track is extracted. These transversal filters 25,
The output pseudo crosstalk signal of 26 is subtracted by the subtractors 30 and 31 from the reproduction signal from the track to be reproduced after waveform equalization from the transversal filter 21, respectively. As a result, the subtracter 31 cancels and eliminates the crosstalk in the reproduction signal of the track to be reproduced after the waveform equalization from the transversal filter 21, and outputs as a reproduction signal with a good S / N. In this embodiment,
Since it is a feedback process, stable operation can be realized.

In this embodiment, a transversal filter 21 is included in an inter-symbol interference removal block of a reproduction signal of a track to be reproduced, and a transversal filter 25.
In each of the pseudo crosstalk generation blocks based on the reproduction signals from the adjacent tracks including the control signals 26 and 26, each tap coefficient (filter coefficient) is controlled so that the same error signal is set to 0, so that a control collision occurs. do not do.

As a secondary effect corresponding to partial response equalization, it is possible to extract an error signal from the information of all sampling points. The crosstalk component can be clearly identified when the reproduction signal of the desired track is flat (a state where the reversal interval is large). Since this level cannot be fixed in the past, the crosstalk component is correlated only at the zero cross point. It was

On the other hand, in this embodiment, the value is 0.
Alternatively, since convergence is made toward a clear value such as 2a + 2b, an error from this value is used as an error signal to be correlated with the crosstalk component, so that accurate and quick convergence is possible. Other values (a, 2a, a +
2b, 2b, etc.) is the same. Therefore, if the average inversion interval of the signal is 5T (T is a bit period), it can be easily imagined that the convergence will be 5 times or more faster, and the convergence in the wrong direction will not occur.

When the resampling DPLL 17 is used, the sampling clock used for the A / D converter 11 is not synchronized with the bit clock, and the same applies to the sampling clock of the reproduction signal of the adjacent track. The constant phase shift can be absorbed by the pseudo crosstalk generator (transversal filters 25, 26).
It can be regarded as a resampling arithmetic unit itself. )
However, when the frequencies are deviated, the sampling time interval is not constant, and thus the conventional pseudo crosstalk generator cannot handle it.

On the other hand, in this embodiment, the internal sampling ratio T_ratio and the bit clock BCLK generated by the resampling DPLL 17 at the time of resampling calculation are used, and the resampling devices 18 and 19 resampling the reproduced signals from the adjacent tracks. Since the sampling calculation is performed, the frequency shift can be dealt with. Further, the phase is roughly adjusted by the delay adjusters 23 and 24 in the subsequent stage, and the phase is left to the pseudo crosstalk generator using the transversal filters 25 and 26. Thereby, the resampling DPLL 17 can be used. The delay adjusters 23 and 24 are replaced by the resampling device 1
The reason why they are arranged after 8 and 19 is that this can reduce the number of delay flip-flops, so they may be arranged functionally before the resampling devices 18 and 19.

The resampling DPLL 17 is independently AG
Since it is sandwiched between the C / ATC circuit 14 and the inter-symbol interference elimination block of the reproduction signal of the track to be reproduced including the transversal filter 21, and the loop is completed in its own block, Can be expected to converge. On the other hand, when the resampling DPLL 17 is not used, an external voltage controlled oscillator (VCO) is required,
Further, since the A / D converter performs bit sampling, a PLL loop including the A / D converter is formed,
Since a high-speed D / D converter is required, the cost is high.

If the resampling DPLL 17 is not used, a PLL loop including an AGC / ATC circuit is formed, so that there is a case where they interfere with each other and cannot converge in an appropriate direction. It is conceivable to put all the loops and PLL loop out and configure them with analog circuits, but voltage controlled amplifier (VCA)
Need to be added, and it is adversely affected by changes over time and component variations that are peculiar to analog circuits. From the above, it is clear that the configuration using the resampling DPLL as in this embodiment is desirable, and in particular, in the optical disc, the recording / reproducing system has the high-frequency attenuation characteristic in the frequency characteristic, which is suitable for oversampling.

Next, the simulation waveform of this embodiment will be described. 4 to 7 are simulation waveforms when crosstalk cancellation is not performed, and the horizontal axis is the time axis. In FIG. 4, I, II, and III indicate the output signal waveform of the resampling DPLL 17, the pseudo crosstalk signal waveform from the transversal filter 25 or 26, and the input signal waveform of the temporary discrimination circuit 33. Also, FIG.
Shows the tap coefficient of the transversal filter 25 or 26, and FIG. 6 shows the eye pattern of the input signal of the provisional discrimination circuit 33.

Further, in FIG. 7, IV is a resampling DPL.
An error flag obtained by comparing the output signal of L17 with the recording signal, V is an error flag obtained by comparing the reproduction data obtained by further Viterbi decoding the signal output through the subtractor 31 with the recording signal. The error flag V of the decoded signal is low in the frequency of occurrence of the error flag IV of the output signal of the resampling DPLL 17, and the error is reduced, even though the crosstalk canceller is off and the operation of this embodiment is not performed. However, this is a transversal filter 21
By waveform equalization and Viterbi decoding.

On the other hand, FIGS. 8 to 11 are simulation waveforms when the crosstalk cancellation is performed according to this embodiment, and the horizontal axis is the time axis. VI, VII and V in FIG.
III is the output signal waveform of the resampling DPLL 17,
The pseudo crosstalk signal waveform from the transversal filter 25 or 26 and the input signal waveform of the temporary discrimination circuit 33 are shown. As can be seen from the figure, the pseudo crosstalk signal waveform converges to a steady state in a short time after the operation is started, and the crosstalk signal is removed from the input signal waveform of the provisional discrimination circuit 33 so that the amplitude becomes almost constant. ing.

FIG. 9 shows the transversal filter 2
10 shows the eye pattern of the input signal of the provisional discrimination circuit 33, and FIG. It can be seen that the tap coefficient is variable and the eye pattern is open compared to when the crosstalk canceller is off. Furthermore, FIG.
Where IX is an error flag obtained by comparing the output signal of the resampling DPLL 17 with the recording signal, and X is an error flag obtained by comparing the reproduction data obtained by further Viterbi decoding the signal output through the subtractor 31 with the recording signal. Is.

As can be seen by comparing FIGS. 7 and 11, the error flag obtained by comparing the output signal of the resampling DPLL 17 with the recording signal is the same regardless of whether the crosstalk canceller operation is performed or not. However, it can be seen that when the crosstalk canceller operation is performed, there is almost no error in the Viterbi-decoded reproduction data as compared with the case where the crosstalk canceller operation is not performed. That is, according to the present embodiment, it is understood that the error that cannot be removed by the Viterbi decoding can be completely removed except immediately after the operation is started.

Next, another embodiment of the present invention will be described. FIG. 12 shows a second embodiment of the recorded information reproducing apparatus according to the present invention.
3 is a block diagram of the embodiment of FIG. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the second embodiment shown in FIG. 12, the A / D converters 11 to 13 are used.
And a digital pre-equalizer (PreEQ) 37-39 is used between the AGC / ATC circuits 14-16.

FIG. 13 shows a block diagram of the third embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The third embodiment of FIG. 13 is the A / D converter 11 to 11.
An analog pre-equalizer (PreE
Q) It is characterized in that 41 to 43 are used.

FIG. 14 is a block diagram of the fourth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The fourth embodiment shown in FIG. 14 is characterized in that a provisional determination circuit 45 is provided for performing determination using a fixed threshold value instead of using zero point information for provisional determination. That is, the reproduced signal after waveform equalization extracted from the subtracter 31 is output to the Viterbi decoding circuit in the subsequent stage, and is also supplied to the provisional determination circuit 45, where it is compared with a predetermined threshold value and the zero cross point is detected. Then, the tentative discrimination is performed from the continuous pattern series of the zero cross points by the above-mentioned algorithm.

The temporary discrimination result by the temporary discrimination circuit 45 and the input signal of the temporary discrimination circuit 45 (the output signal of the subtractor 31) are subtracted by the subtractor 34, and the difference value is an error signal and the polarity is inverted by the inverter 35. After being
It is supplied to the LPF 27, and is inputted to the transversal filter 21 as a filter coefficient (tap coefficient) of the transversal filter 21 which makes the value of the error signal 0. In this embodiment, the resampling DPL
Since the zero point information from L17 is not used, the delay adjuster 22 and the tap delay circuit 32 are unnecessary.

FIG. 15 is a block diagram of the fifth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 15, of the three adjacent tracks in the track group formed on the optical disc, the read signal of the track Ti to be reproduced at the center is a voltage control amplifier (VC).
A) The read signal of the adjacent track Ti-1 on the inner peripheral side is input to the VCA 48, and the read signal of the adjacent track Ti + 1 on the outer peripheral side is input to the VCA 49 to control the level and DC. .

The output read signals of the VCAs 47, 48 and 49 are supplied to the A / D converters 50, 51 and 52 of the next stage, sampled by the master clock and converted into digital signals, and the fixed equalizer of the next stage ( EQ) 53, 5
After the equalizer characteristic is given at 4, 55, AGC A
It is supplied to the TC detection circuits 56, 57 and 58, where automatic amplitude control (AGC) in which the amplitude is controlled to be constant and automatic threshold control (ATC) in which the threshold value of the binary comparator is appropriately controlled (DC). A gain control signal and a DC control signal are generated. This gain control signal is VCA47, 4
8 and 49 to variably control the gain. As a result, in this embodiment, AGC and ATC can be performed together with the analog circuit.

FIG. 16 is a block diagram of the sixth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIGS. 1 and 15 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 16, of the three adjacent tracks in the track group formed on the optical disc, the read signal of the central track Ti to be reproduced is an analog AG.
The read signal of the adjacent track Ti-1 on the inner peripheral side is input to the C / ATC circuit 61 and the analog AGC / ATC circuit 62 is read.
The read signal of the adjacent track Ti + 1 on the outer peripheral side is input to the analog AGC / ATC circuit 63,
The amplitude is controlled to be constant and the threshold value of the binary comparator is controlled appropriately.

The output read signals of the AGC / ATC circuits 61, 62 and 63 are output to the A / D converters 50, 51 and 52 of the next stage.
To the digital signal and sampled by the master clock to be converted into a digital signal. Only the output of the A / D converter 50 is provided with the equalizer characteristic by the fixed equalizer (EQ) 53 at the next stage. In this embodiment, AGC and ATC are performed only by AGC / ATC circuits 61, 62 and 63 which are analog circuits.

FIG. 17 is a block diagram of the seventh embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. The seventh embodiment of FIG. 17 is characterized in that the zero point information is extracted from the waveform equalized reproduction signal output from the subtractor 31 to the Viterbi decoder.

That is, the reproduced signal after waveform equalization extracted from the subtractor 31 is supplied to the zero detector 65, and when the polarity is inverted here, one of two neighboring sample points which is closer to 0 is selected. Are sampled as zero point information. The zero point information extracted from the zero detector 65 is input to the tap delay circuit 32. Thereby, according to the temporary discrimination algorithm similar to FIG.
A tentative discrimination result is obtained.

FIG. 18 shows a block diagram of an eighth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the eighth embodiment shown in FIG. 18, the recorded information is reproduced without using the resampling DPLL 17 and the resampling circuits 18 and 19. That is, the output digital read signals of the AGC / ATC circuits 14, 15 and 16 are directly fed to the delay adjusters 20 and 23, respectively.
Transversal filters 21, 25, 2 through 24
6 is supplied.

The crosstalk removed from the subtractor 31 and the waveform-equalized reproduction signal are supplied to the provisional discrimination circuit 33 while being supplied to the zero-cross detection / phase comparator 67, where Zero cross is detected, and the phase of the detected zero cross point and the voltage controlled oscillator (VCO) 69
It is generated as a phase error signal by comparing the phase with the phase of the bit clock. This phase error signal is applied as a control voltage to an analog or digital voltage controlled oscillator (VCO) 69 through a loop filter 68 to variably control the output system clock frequency. VCO6
The output system clock of 9 has a frequency that is a natural multiple of the bit clock, and the clock of the device is applied to each block that requires it.

FIG. 19 is a block diagram of the ninth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as in FIG. In FIG. 19, of the three adjacent tracks in the track group formed on the optical disc, the read signal of the central track Ti to be reproduced is an analog AGC / AT.
It is input to the C circuit 71 and the adjacent track Ti-1 on the inner peripheral side
Read signal is input to the analog AGC / ATC circuit 72, and the read signal of the adjacent track Ti + 1 on the outer peripheral side is input to the analog AGC / ATC circuit 73, and the amplitude of each is controlled to be constant and the binary comparison is performed. The rate threshold is properly controlled.

The output read signal of the AGC / ATC circuit 71 is provided with an equalizer characteristic by a fixed equalizer (EQ) 41 at the next stage, and then supplied to the A / D converter 11 and sampled by a bit clock to obtain a digital signal. Is converted to. The output read signals of the AGC / ATC circuits 72 and 73 are supplied to the A / D converters 12 and 13, sampled by a bit clock, and converted into digital signals. The output digital signals of the A / D converters 11, 12 and 13 are supplied to the transversal filters 21, 25 and 26 through the delay adjusters 20, 23 and 24.

The output analog signal of the fixed equalizer 41 is the phase comparator 74 and the loop filters 75 and 76.
And a system clock having a frequency that is a natural number multiple of the bit clock. On the other hand, when the polarity of the signal from the delay adjuster 20 is inverted, the zero detector 77 supplies, to the tap delay circuit 32, one of two nearby sampling points that is closer to 0 as zero point information. This embodiment also has the same features as the above embodiments.

FIG. 20 shows a block diagram of a tenth embodiment of a recorded information reproducing apparatus according to the present invention. In the figure, FIG.
4, FIG. 18 and FIG. 19 are given the same reference numerals and their description will be omitted. The tenth embodiment shown in FIG. 20 has a configuration in which ATC / AGC is performed only by an analog circuit and fixed threshold value determination is performed without using a digital VCO. In FIG. 20, the reproduced signal after the waveform equalization extracted from the subtractor 31 is output to the Viterbi decoding circuit in the subsequent stage, and is also supplied to the tentative determination circuit 45, where it is compared with a predetermined threshold value and the zero cross point is compared. Is detected, and the tentative discrimination is performed from the continuous pattern series of the zero cross points by the above-mentioned algorithm.

FIG. 21 is a block diagram of the eleventh embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In the eleventh embodiment shown in FIG. 21, the error signal output from the subtractor 34 is input to the first input terminal,
A feature is that an error selection circuit 81 to which the output temporary determination value of the temporary determination circuit 33 is input is provided at the second input terminal.

In the error selection circuit 81, as shown in FIG. 22, the error signal output from the third subtractor 34 is input to the first input terminal 811, and the temporary determination circuit 33 is input to the second input terminal 812. The selection circuit 813, the switch circuit 814, and the 0 generator 815 to which the temporary discrimination value output from
It consists of The provisional discrimination value output from the provisional discrimination circuit 33 should be set to the target value for PR equalization, and the deviation from the target value is output as an error signal. When the circuit 33 outputs 0 ^* corresponding to the zero cross point as the target value, it outputs "1".

Further, in the case of RLL (2, X), the selection circuit 813 also determines "when the above tentative discrimination values are + b ^* and -b ^*.
1 "is output. This b is the value of b in PR (a, b, b, a), and * is RLL (1, X) or RLL.
It is shown that the median value (a + b) of (2, X) is a value after being offset so that it becomes 0. When the provisional discrimination value is + b ^* or -b ^* , the selection circuit 813 determines that it is a value immediately before or after the zero cross point and is "1".
Is output. When the provisional discrimination value is other than the above values, the selection circuit 813 outputs "0". When it is RLL (1, X), it is + (b−a) ^* , and when it is − (b−a) ^* , it is judged to be the value immediately before or after the zero cross point, and “1”.
Otherwise, "0" is output otherwise.

The switch circuit 814 receives as input the error signal input to the terminal a and the fixed value 0 from the 0 generator 815 input to the terminal b, and the selection circuit 8
13 is supplied as a switching signal, and when the output signal of the selection circuit 813 is "1", the effective component of the error signal input to the terminal a is selected, and the selection circuit 813 is selected.
When the output signal of is 0, the value 0 input to the terminal b is selected. The signal selected by the selection circuit 813 is supplied to the multipliers / LPFs 28 and 29 of FIG. 21 through the output terminal 816, respectively, and is multiplied by the tap output from the pseudo crosstalk component extracting transversal filters 25 and 26. After the post high frequency components are removed, tap coefficients (filter coefficients) that make the above error signal zero are input to the transversal filters 25 and 26, respectively.

Next, regarding the operation of this embodiment, R
LL (2, X) will be described as an example. Error selection circuit 8
In the first to tenth embodiments not having No. 1, when the waveform distortion of the reproduced signal is small, when there is no crosstalk from the adjacent track, I is shown in FIG.
When the crosstalk component as shown in FIG. 23B is included, the output signal of the transversal filter 21 is correctly PR-equalized, as shown by II in FIG. An error signal as shown in FIG. 23D is extracted. This error signal represents the crosstalk component of FIG. 23B, that is, it has a high correlation with the adjacent track signal, and the pseudo crosstalk component can be correctly generated.

In FIG. 23, circles are sample points when the target value is 0 (zero cross point), x marks are sample points when the target value is + b ^* or -b ^* , and white triangle marks are the target values. Shows sample points when is (a + b) ^* or − (a + b) ^* (the same applies to FIGS. 24 to 25 described later).

However, as shown in the reproduced signal from the optical disk, when the reproduced signal has a large distortion, when there is no crosstalk from the adjacent tracks, FIG.
When the crosstalk component is included in III and also includes the crosstalk component as illustrated in FIG. 24B, the output signal of the transversal filter 21 is correctly PR equalized as illustrated in IV in FIG. From the subtractor 34, as shown in FIG.
As shown in (D), an error signal in which the sample points indicated by white triangles are largely deviated from the target value is extracted.

That is, the output error signal of the subtractor 34 is
Inaccurate data appear at sample points that are not near zero crossing, deviate from the crosstalk component shown in FIG. 24B, and the correlation with adjacent track signals is low. Therefore, the pseudo crosstalk component cannot be correctly generated, and the effect of crosstalk cancellation is halved.

Therefore, in this embodiment, the error selection circuit 81 having the configuration shown in FIG. 22 is provided on the input / output side of the subtractor 34 as shown in FIG. 21, and the target value 0, + b ^* or -b ^{* is set.}
At this time, the error signals of the sampling points other than the sampling points near the zero cross are not output, and the error signal is invalidated by outputting the fixed value 0. Therefore, when the distortion is large and there is no crosstalk, In FIG. 25A, III (same as III in FIG. 24A) is included in FIG. 25C when IV (FIG. 24C) is included.
25), the error signal output from the error selection circuit 81 is equal to the error signal output from the error selection circuit 81, even when a signal not properly PR-equalized is output from the transversal filter 21. As schematically shown in (D), sample points that are not near zero crossing are replaced with a fixed value 0 as indicated by black triangles.

Therefore, even at a sample position where a large deviation from the target value occurs when the error selection circuit 81 does not exist, in this embodiment, as shown in FIG.
There is no deviation from the target value. As described above, in this embodiment, by invalidating an uncertain error signal among the error signals and using only probable sample points near the zero cross as an effective component of the error signal, it is possible to converge to a correct target value and correct The error can be extracted, the error rate can be improved as a result, and a reproducing device for a high-density recording medium such as a next-generation VDR (15 to 20 Gbytes or more) can be realized. In this embodiment, a part of the error signal is invalidated as compared with the above-mentioned respective embodiments, so that the efficiency is lowered, but by increasing the loop gain, it is possible to prevent the efficiency from being lowered.

FIG. 26 is a block diagram of another embodiment of the error selection circuit 81. 22, those parts which are the same as those corresponding parts in FIG. 22 are designated by the same reference numerals, and a description thereof will be omitted. The embodiment shown in FIG. 26 is characterized in that a selection circuit 818 having a configuration different from that of the selection circuit 813 of FIG. 22 is used. The selection circuit 818 only operates when the temporary discrimination circuit 33 outputs 0 ^* corresponding to the zero cross point as the target value.
"1" is output, and when other provisional discrimination values are output, "
Therefore, in this embodiment, the error selection circuit 81 outputs only the error signal of the most probable sample point and invalidates the error signals of the other sample points.

FIG. 27 is a block diagram of the twelfth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In the twelfth embodiment shown in FIG. 27, the error signal output from the subtractor 34 is input to the first input terminal,
A feature is that an error selection circuit 83 to which 0-point information is input from the resampling DPLL 17 through the delay adjustment circuit 22 and the tap delay circuit 32 is provided at the second input terminal.

FIG. 28 shows the error selecting circuit 83 and a part of the circuit 32a of the tap delay circuit 32. Resampling D
0 point information from PLL17 is the resampling D
Information indicating the timing at which a sampling point formed by resampling, which corresponds to the zero-cross point to which the PLL 17 should be locked, exists (for example, only that point is "1", and other points are "0"). The OR circuits 32 are delayed by one sample clock each by two cascaded latch circuits 321 and 322.
3 as well as directly to the OR circuit 323. Therefore, three consecutive 0's are output from the OR circuit 323.
Only when at least one of the point information is "1", "1" is output and applied to the switch circuit 831 as a switching signal.

The switch circuit 831 is the OR circuit 32.
When the output signal of 3 is “1”, the error signal output from the subtractor 34 is selected and output to the output terminal 833.
When the output signal of the R circuit 323 is “0”, the 0 generator 8
The fixed value “0” output from 32 is selected and output to the output terminal 833.

Here, when at least one of the three 0-point information of three consecutive clock cycles input to the OR circuit 323 is "1", the digital reproduction signal input to the resampling DPLL 17 is zero-cross sampled. It indicates that the value is one of the three sample values including the value and the sample value immediately before and the sample value immediately after, and therefore the switch circuit 831 selects only the error signal output from the subtractor 34 at this time. However, at the timing of the other sample values, the fixed value 0 from the 0 generator 832 is selected. As a result, like the error selection circuit 81 having the configuration of FIG. 22, the error selection circuit 83 invalidates an uncertain error signal not near zero crossing and selectively outputs only a probable error signal. The same effect as can be obtained.

The error selection circuit 83 can also be constructed as shown in the block diagram of FIG. The error selection circuit 83 shown in FIG.
0 point information indicating the timing at which a sample point formed by resampling, which corresponds to the zero-cross point to be locked, is latched by the latch circuit 835 and supplied to the switch circuit 831 as a switching signal. As a result, the error signals supplied to the pseudo-crosstalk component extracting transversal filters 25, 26 are selected and output only at the timing indicated by the 0-point information, and the error signals at other sample points are invalid. Turn into. As a result, only the most probable error signal can be selectively output.

FIG. 30 is a block diagram of the thirteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In the thirteenth embodiment shown in FIG. 30, the main signal (the reproduced signal after waveform equalization) output from the second subtractor 31 is input to the first input terminal, and the tentative determination is made to the second input terminal. Error selection circuit 8 to which the provisional discrimination value from the circuit 33 is input
The feature is that 5 is provided.

In the error selection circuit 85, as shown in FIG. 31, the main signal output from the second subtractor 31 is input to the first input terminal 851, and the temporary determination circuit 33 is input to the second input terminal 852. The selection circuit 853, the switch circuit 854, and the 0 generator 855 to which the provisional discrimination value output from
It consists of The provisional discrimination value output from the provisional discrimination circuit 33 should be set to the target value for PR equalization, and the deviation from the target value is output as an error signal. "1" is output only when the circuit 33 outputs 0 ^* corresponding to the zero cross point as the target value, and "0" is output otherwise.

The switch circuit 854 receives as input the main signal input to the terminal a and the fixed value 0 from the 0 generator 855 input to the terminal b, and also the selection circuit 8
When the output signal of 53 is supplied as a switching signal and the output signal of the selection circuit 853 is "1", the effective component of the main signal input to the terminal a is selected, and the selection circuit 853 is selected.
When the output signal of is 0, the value 0 input to the terminal b is selected. The signal selected by the switch circuit 854 is output via the output terminal 856 to the multiplier / LPF 28, 2 of FIG.
9 and the high-frequency components are removed after being multiplied by the tap outputs from the pseudo-crosstalk component extracting transversal filters 25 and 26, and then the tap coefficient ( Filter coefficient)
Are input to the transversal filters 25 and 26, respectively.

In this embodiment, the error signal from the subtractor 34 and the main signal (sample data signal) output from the subtractor 31 are set at the sampling point when the provisional discrimination value is "0" corresponding to the zero cross point. , Ie, the reproduced signal after waveform equalization), the error selection circuit 8
5 selects the main signal from the subtracter 31 instead of the error signal (that is, invalid data is invalid under certain conditions other than zero crossing) and outputs it as an error signal. Is. This embodiment can also obtain the same effects as the eleventh embodiment and the twelfth embodiment.

FIG. 32 is a block diagram of the fourteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In the fourteenth embodiment shown in FIG. 32, the main signal output from the second subtractor 31 is input to the first input terminal, and the resampling DPLL 17 to the delay adjustment circuit 22 and the tap are input to the second input terminal. 0 through the delay circuit 32
A feature is that an error selection circuit 87 for inputting point information is provided.

As shown in FIG. 33, the error selection circuit 87 latches 0-point information indicating the timing at which the sampling point formed by resampling, which corresponds to the zero-cross point to which the resampling DPLL 17 should be locked, exists. Latched by and supplied as a switching signal to the switch circuit 872. The main signal output from the second subtractor 31 is input to the terminal a of the switch circuit 872, and the 0 generator 873 is input to the terminal b.
The fixed value 0 from is input.

Here, the timing indicated by the 0-point information output from the latch circuit 871 is the sample point corresponding to the zero cross point, and at this sample point, the error signal from the subtractor 34 and the subtracter 31 output. Since it is the same as the main signal (sample data signal),
The error selection circuit 87 selects and outputs the main signal from the subtractor 31 instead of the error signal.

In this embodiment, the error selection circuit 87
Of the main signal from the subtractor 31 in response to a signal (output signal z3 of the latch circuit 871) indicating a timing at which a sampling point formed by resampling, which corresponds to a zero cross point to which the resampling DPLL 17 should be locked, exists. Since only the effective component is selected (that is, invalid data is invalid under certain conditions other than zero crossing) and output as an error signal, the eleventh embodiment ~ The same effect as that of the thirteenth embodiment can be obtained.

FIG. 34 is a block diagram of the fifteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In FIG. 34, of the digital data and 0-point information extracted from the resampling DPLL 17, digital data is supplied to the FIFO 91, and 0-point information is supplied to the FIFO 92, and the bit clock of the bit clock generated by the resampling DPLL 17 is supplied. It is written at the timing. Further, the first and second sampling signals respectively taken out from the resampling circuits 18 and 19 are supplied to the FIFOs 93 and 94 and written at the timing of the above bit clock.

The signals written in the FIFOs 91, 92, 93 and 94 are read by a new clock corresponding to the average value of the frequencies generated by the bit clocks, respectively, and the delay adjusters 20, 22, 23, and 24. As a result, the transversal filter 2
The operations 1, 25 and 26 and the tap delay circuit 32 operate with a new clock. This new clock has a lower frequency than the master clock in each of the above embodiments.

By the way, in each of the above-described embodiments, the resampling DPLL 17 and the transversal filter 2 are used.
1. The provisional discrimination circuit 33 and the tap delay circuit 32 have the above-described excellent effects in full digital processing.
Since the operating frequency is the master clock, it is necessary to perform all the calculations under the master clock frequency. Depending on the system, there are cases where it is not suitable in terms of speed limitation and power consumption by the IC device.

On the other hand, in this embodiment, the digital data and zero point information output from the resampling DPLL 17 and the first and second sampling signals output from the resampling circuits 18 and 19 are Since the FIFOs 91, 92, 93, and 94 are read at timings of new clock frequencies lower than the master clock, and the subsequent operation is performed using the new clocks, the operating frequency of the circuit is low. It is possible to solve the problems of speed limitation and power consumption.

FIG. 35 is a block diagram of the sixteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In FIG. 35, the digital data taken out from the resampling DPLL 17 is directly supplied to the transversal filter 26 without being delayed, while being supplied to the transversal filter 25 through the two-stage cascade connected FIFOs 95 and 96. FIF
The output delayed digital data of O95 is supplied to the transversal filter 21.

Since the FIFOs 95 and 96 each have a predetermined delay time τ, the digital data input to the transversal filter 25 is delayed by the time τ with respect to the digital data input to the transversal filter 21. On the other hand, the digital data input to the transversal filter 26 is a signal advanced by time τ.

Since the predetermined delay time τ is about one track scanning period, the digital data input to the transversal filter 25 is the digital data input to the transversal filter 21. Is a signal from an adjacent track position on the inner circumference side (when the beam travels from the inner circumference to the outer circumference) of the beam spot position at that time. On the other hand, the digital data input to the transversal filter 26 is the transversal filter. It is a signal from an adjacent track position on the outer circumference side of the track (when the beam travels from the inner circumference to the outer circumference) with respect to the beam spot position when the digital data input to 21 is obtained.

As a result, in the embodiment of FIG. 1, the first and second crosstalk signals obtained separately from the tracks adjacent to both sides of the main track by the three beams are input to the transversal filters 25 and 26. On the other hand, in this embodiment, the signals replaced with the first and second crosstalk signals described above can be generated by giving the necessary delay by the FIFOs 95 and 96, which is necessary in the embodiment of FIG. The existing second and third reading means and resampling means including resampling circuits 18 and 19 can be dispensed with, and as a result, crosstalk cancellation with a single beam can be realized, and circuits other than the memory can be downsized. .

FIG. 36 shows a block diagram of the seventeenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as those in No. 8 are designated by the same reference numerals and the description thereof will be omitted. In the seventeenth embodiment shown in FIG. 36, as in the sixteenth embodiment, the AGC.
By giving a necessary delay to the output read signal of the ATC circuit 14, a signal replaced with the first and second crosstalk signals can be generated, which is necessary in the embodiment of FIG. 2nd and 3rd reading means and AG
The resampling means including the C / ATC circuits 15 and 16 can be dispensed with, and as a result, crosstalk cancellation with a single beam can be realized, and the circuits other than the memory can be downsized.

FIG. 37 shows a block diagram of the eighteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as those of item 9 are designated by the same reference numerals, and the description thereof will be omitted. In the eighteenth embodiment shown in FIG. 37, as in the sixteenth and seventeenth embodiments, a necessary delay is given to the output read signal of the A / D converter 11 by the FIFOs 99 and 100. It is possible to generate a signal replaced with the first and second crosstalk signals, and the second and third reading means, the AGC / ATC circuits 72 and 73, and the A / D, which are necessary in the embodiment of FIG. Converter 12
The resampling means including Nos. 13 and 13 can be eliminated, and as a result, crosstalk cancellation with a single beam can be realized, and the circuits other than the memory can be downsized.

FIG. 38 shows a block diagram of the nineteenth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. 16th and 17th shown in FIGS. 35, 36 and 37
In the eighteenth and eighteenth embodiments, the read means is used by using the FIFOs for the required tracks, respectively.
Since the sampling signal input to is a signal having a value of 8 bits, for example, the memory capacity of the FIFOs 95 to 100 becomes large.

Therefore, in this embodiment, the 1-bit data output from the Viterbi decoder is used as the signal input to the transversal filters 25 and 26 for pseudo crosstalk generation, and the transversal filter 2 is used.
The 1-bit data is directly input to 6, and the transversal filter 25 is input by the FIFO 101 with a delay of about two track scanning periods.

On the other hand, the digital data output from the resampling DPLL 17 is supplied to the transversal filter 21 after being delayed for about one track scanning period by the FIFO 102, and also resampling DPL.
The digital data output from L17 is the FIFO1
After being delayed by about one track scanning period by 03, it is supplied to the tap delay circuit 32.

Thus, the transversal filter 2
The digital data input to 5 is an adjacent track position on the inner track side (when the beam travels from the inner circumference to the outer circumference) one track from the beam spot position when the digital data input to the transversal filter 21 is obtained. On the other hand, the digital data input to the transversal filter 26 is the Viterbi decoded data from the 1st track outer peripheral side (the beam is on the outer side of the track) from the beam spot position when the digital data input to the transversal filter 21 is obtained. It is the Viterbi decoded data from the adjacent track position (when proceeding from the inner circumference to the outer circumference).

As a result, the Viterbi decoded data can be input to the transversal filters 25 and 26 as a signal replaced with the first and second crosstalk signals, as shown in FIG.
The second and third reading means and resampling means, which were necessary in the embodiment of the above, can be eliminated, and as a result,
Crosstalk cancellation with a single beam is realized, circuits other than the memory can be reduced, and since the Viterbi decoded data is 1 bit, the memory capacity of the FIFO 101 can be made smaller than that of the FIFO 95 to 100 (for example, 1 / if the original sampling data is 8 bits
8).

FIG. 39 is a block diagram of the twentieth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as those in No. 8 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the AGC is performed by the FIFO 104.
The output signal of the ATC circuit 14 is supplied to the transversal filter 21 after being delayed for about one track scanning period, while the 1-bit Viterbi decoded data is supplied to the transversal filter 26 without delay and the FIF
After being delayed by about two track scanning periods in O105, the signal is supplied to the transversal filter 25.

As a result, similarly to the eighteenth embodiment shown in FIG. 38, the memory capacity of the FIFO 105 is set to the FI shown in FIG.
It can be made smaller than that of FO97, 98 (for example,
1/8 if the original sampling data is 8 bits).

FIG. 40 is a block diagram of the twenty-first embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, FIG.
The same components as those of item 9 are designated by the same reference numerals, and the description thereof will be omitted. This embodiment uses A / D by the FIFO 106.
The output signal of the converter 11 is delayed for about one track scanning period and then supplied to the transversal filter 21, while
The bit Viterbi decoded data is supplied to the transversal filter 26 without delay, and the FIFO 10
After being delayed by about 2 track scanning periods at 7, the data is supplied to the transversal filter 25.

As a result, similarly to the nineteenth and twentieth embodiments of FIGS. 38 and 39, the memory capacity of the FIFO 107 can be made smaller than that of the FIFOs 99 and 100 of FIG. 36 (for example, the original sampling data is With 8 bits, it is 1/8).

The present invention is not limited to the above embodiment, and for example, the delay adjuster 20 shown in FIG.
23 and 24 are AGC / ATC circuits 14, 15 and 16
Of the transversal filters 21, 25 and 26 may be omitted if there is a margin.

Further, in the above-described embodiment, two system circuits are provided for exclusively generating the pseudo crosstalk signals for the two-beam read signals for the two tracks adjacent to both sides of the track to be reproduced. If the device has a known tilt sensor that detects the irradiation angle of the beam with respect to the optical disc, based on the output signal of the tilt sensor, reading of two beams for two tracks adjacent to both sides of the track to be reproduced is performed. By providing a switch circuit that selects only one of the signals having a large crosstalk component, the pseudo crosstalk signal generation circuit system can be made only one system.

In the case of multi-valued equalization, some of them may be selected to generate tap coefficients of a transversal filter for generating a pseudo crosstalk component. Further, the selected error signal may be shared with the error signal on the automatic equalization circuit side.

Although not shown in the figure, the signals input to the transversal filters 21, 25 and 26 are written in a separately provided FIFO with a bit clock, and a new clock having a lower frequency than the master clock is written from this FIFO. Read at the timing of frequency,
The means for outputting to the transversal filters 21, 25 and 26 and performing the subsequent operation using a new clock is
It is also applicable to each of the embodiments shown in FIGS. 13 to 17, 21, 21, 27, 30 and 32. Also,
It is also possible to use a RAM or other memory element other than the FIFO as the memory element.

[0126]

As described above, according to the present invention,
The temporary discrimination means performs the temporary discrimination (convergence target setting) on the premise of partial response equalization, and the difference value between the temporary discrimination value and the waveform-equalized reproduced signal extracted from the subtraction circuit is used as an error signal for the first to the first. By supplying it to the filter coefficient generating means of No. 3, and controlling so that the error signal becomes 0,
The operation of the device can be converged toward a clear tentative discriminant value (0, 2a + 2b, etc.), and all points (sample values) are crosstalk using errors from the tentative discriminant value subject to correlation detection as error signals. Since the correlation with the components is taken, rapid convergence can be achieved, and moreover, reliable waveform equalization can be achieved without convergence in the wrong direction. Further, according to the present invention, since partial response equalization is performed, a Viterbi decoder can be used in the subsequent stage,
Accurate decryption is possible.

Further, according to the present invention, the resampling calculation of the reproduction signal from the adjacent track is performed by the resampling means by utilizing the internal division ratio and the bit clock at the resampling calculation generated by the resampling calculation phase locked loop circuit. Therefore, the frequency shift can be dealt with. Further, according to the present invention, since the resampling operation phase-locked loop circuit can be used, the integrated circuit can be easily integrated, the number of components can be reduced, and since it is suitable for oversampling, the reproduced signal has a high-frequency attenuation characteristic. It is suitable to be applied to a reproducing apparatus for a recording medium such as an optical disk. Furthermore, it is not affected by changes with time and parameter variations peculiar to analog.

Further, according to the present invention, since the error selection circuit invalidates the signal indicating the uncertain error value and takes out only the probable error signal as the effective component, the distortion of the reproduced signal is large. Even when partial response equalization cannot be completed, the deviation from the target value is small, the error signal can be correctly extracted, and as a result, the error rate can be improved.

Further, according to the present invention, the frequency of the new clock is set lower than the master clock frequency and the subsequent operation is performed at this new clock frequency, so that the operation time can be increased and the latches and the like can be reduced. Therefore, the circuit delay, the circuit scale, and the operating frequency can be reduced, and as a result, the problems of speed limitation, power consumption, and cost due to the IC device in the system can be solved.

Further, according to the present invention, the resampling means is eliminated by using the delay means to obtain a signal equivalent to the crosstalk signal obtained from the adjacent tracks on both sides of the track to be scanned using the three beams. By doing so, crosstalk cancellation by a single beam can be realized, the circuit configuration can be simplified, and the cost can be reduced.

Further, according to the present invention, since the pseudo crosstalk signal is generated by using the 1-bit Viterbi decoded data having a smaller number of bits than the normal sampling data, the first pseudo crosstalk signal is generated. The memory capacity of the second memory can be minimized, and the circuit scale and cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a schematic explanatory view of an example of a positional relationship between a beam spot and a track by the 3-beam method.

FIG. 3 is a state transition diagram of an example of partial response equalization.

FIG. 4 is a diagram when crosstalk cancellation is not performed.
It is a figure which shows an example of the simulation waveform of each part of.

FIG. 5 is a diagram when crosstalk cancellation is not performed.
It is a figure which shows the change of the tap coefficient of the transversal filter in the pseudo crosstalk signal generation block in the inside.

FIG. 6 is a diagram when crosstalk cancellation is not performed.
The eye pattern of the input signal of the temporary discrimination circuit in the inside is shown.

FIG. 7 is a diagram when crosstalk cancellation is not performed.
It is an error flag of each part inside.

FIG. 8 is a diagram showing an example of a simulation waveform of each part of FIG. 1 when crosstalk cancellation is performed.

9 is a diagram showing changes in tap coefficients of a transversal filter in the pseudo crosstalk signal generation block in FIG. 1 when crosstalk cancellation is performed.

FIG. 10 is a diagram when crosstalk cancellation is performed.
The eye pattern of the input signal of the temporary discrimination circuit in the inside is shown.

FIG. 11 is a diagram when crosstalk cancellation is performed.
It is an error flag of each part inside.

FIG. 12 is a block diagram of a second embodiment of the present invention.

FIG. 13 is a block diagram of a third embodiment of the present invention.

FIG. 14 is a block diagram of a fourth embodiment of the present invention.

FIG. 15 is a block diagram of a fifth embodiment of the present invention.

FIG. 16 is a block diagram of a sixth embodiment of the present invention.

FIG. 17 is a block diagram of a seventh embodiment of the present invention.

FIG. 18 is a block diagram of an eighth embodiment of the present invention.

FIG. 19 is a block diagram of a ninth embodiment of the present invention.

FIG. 20 is a block diagram of a tenth embodiment of the present invention.

FIG. 21 is a block diagram of an eleventh embodiment of the present invention.

22 is a block diagram of an embodiment of the error selection circuit in FIG. 21. FIG.

FIG. 23 is an explanatory diagram of sample points and extraction error components when the PR equalization is correctly performed without the error selection circuit.

FIG. 24 is an explanatory diagram of sampling points and extraction error components when PR equalization is not performed correctly when there is no error selection circuit.

FIG. 25 is an explanatory diagram of a sampling point and an extraction error component when the PR equalization is not performed correctly when an error selection circuit is provided.

FIG. 26 is a block diagram of another embodiment of the error selection circuit in FIG.

FIG. 27 is a block diagram of a twelfth embodiment of the present invention.

28 is a block diagram of an embodiment of the error selection circuit in FIG. 27. FIG.

FIG. 29 is a block diagram of another embodiment of the error selection circuit in FIG. 27.

FIG. 30 is a block diagram of a thirteenth embodiment of the present invention.

31 is a block diagram of an embodiment of the error selection circuit in FIG. 30. FIG.

FIG. 32 is a block diagram of a fourteenth embodiment of the present invention.

33 is a block diagram of an embodiment of the error selection circuit in FIG. 32. FIG.

FIG. 34 is a block diagram of a fifteenth embodiment of the present invention.

FIG. 35 is a block diagram of a sixteenth embodiment of the present invention.

FIG. 36 is a block diagram of a seventeenth embodiment of the present invention.

FIG. 37 is a block diagram of an eighteenth embodiment of the present invention.

FIG. 38 is a block diagram of a nineteenth embodiment of the present invention.

FIG. 39 is a block diagram of a twentieth embodiment of the present invention.

FIG. 40 is a block diagram of a twenty-first embodiment of the present invention.

[Explanation of symbols]

11 to 13 A / D converter 14 to 16 AGC / ATC circuit 17 resampling DPLL circuit 18, 19 resampling circuit 20, 22, 23, 24 delay adjuster 21 waveform equalization transformer of a reproduction signal of a track to be reproduced Versal filter 25, 26 Transversal filter 27-29 for generating pseudo crosstalk signal Multiplier / LPF 30, 31, 34 Subtractor 32 Tap delay circuit 32a Part of tap delay circuit 33 Temporary discrimination circuit 45 Temporary discrimination of fixed threshold value Circuit 65, 77 Zero detector 81, 83, 85, 87 Error selection circuit 91-107 FIFO 321, 322, 835, 871 Latch circuit 323 OR circuit 811, 851 First input terminal 812, 852 Second input terminal 813 , 815, 853 selection circuits 814, 831, 854, 872 Latch circuit 815,832,855,873 0 generator 816,833,856,874 output terminal

Continuation of the front page (56) Reference JP-A-9-320220 (JP, A) JP-A-3-203816 (JP, A) JP-A-9-97476 (JP, A) JP-A-7-240068 (JP , A) JP-A-8-7489 (JP, A) JP-A-2-257474 (JP, A) JP-A-7-334931 (JP, A) JP-A-2000-339862 (JP, A) JP-A-2001- 110146 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 G11B 7/005

Claims (14)

(57) [Claims] 1. A first reproduction signal read from an arbitrary recording information recording track to be reproduced of a recording information recording track group on a recording medium, and the arbitrary recording information recording track to be reproduced. Reading means for obtaining the second and third reproduction signals separately read from each of the two recording information tracks adjacent to each other on both sides, and converting the first to third reproduction signals into digital signals separately. A / D conversion means for outputting first to third digital reproduction signals; and digital clock data sampled at a desired bit rate with respect to the first digital reproduction signal by resampling operation and generating a bit clock. For detecting the zero level of the first digital reproduction signal and outputting zero point information. Circuit, a first transversal filter for waveform equalizing the output digital data of the resampling operation phase locked loop circuit based on a first filter coefficient, and the zero point information at least at each bit sampling timing. A delay circuit that outputs three consecutive signals, a PR mode signal that indicates the type of partial response equalization, an RLL mode signal that indicates the type of run-length limited code of the reproduction signal, and a plurality of the delay circuits from the delay circuit. The zero point information and the reproduced signal after waveform equalization are received as inputs, and based on the state transition determined by the PR mode signal and the RLL mode signal and the pattern of the plurality of zero point information, the temporary discrimination of the waveform equalized signal is performed. Value is calculated, and the difference value between the tentative discrimination value and the reproduction signal after waveform equalization is calculated as an error signal And a first coefficient generation means for variably controlling the first filter coefficient based on an output error signal of the temporary judgment means so that the error signal is minimized. The second and third digital reproduction signals from the D conversion means are separately subjected to resampling operation based on the output bit clock of the phase-locked loop circuit to obtain the first and second sampling signals. Resampling means for outputting, and the first and second sampling signals are separately filtered based on the second and third filter coefficients, so that one of the recording information recording tracks to be reproduced is reproduced. The second and third transistors which separately output the first and second pseudo crosstalk signals corresponding to the read signals of the two recording information tracks adjacent to each other on both sides. A sversal filter, second and third coefficient generation means for variably controlling the second and third filter coefficients separately based on the output error signal of the temporary discrimination means, and a first transversal filter And a subtraction circuit for subtracting the first and second pseudo crosstalk signals from the output signal and outputting the waveform-equalized reproduction signal. 2. A first reproduction signal read from an arbitrary recording information recording track to be reproduced of a recording information recording track group on a recording medium and the arbitrary recording information recording track to be reproduced. Reading means for obtaining the second and third reproduction signals separately read from each of the two recording information tracks adjacent to each other on both sides, and converting the first to third reproduction signals into digital signals separately. A / D conversion means for outputting first to third digital reproduction signals; and digital clock data sampled at a desired bit rate with respect to the first digital reproduction signal by resampling operation and generating a bit clock. And a resampling operation phase locked loop circuit for generating And waveform equalization <br/> reduction based on the first filter coefficients, and detects a first transversal filter for outputting a reproduction signal after waveform equalization, the zero point information of the waveform equalization after regeneration signal
The output zero detector and the zero point information output from the zero detector
A delay circuit that outputs at least three consecutive signals at each bit sampling timing, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limited code of the reproduction signal, and the delay a plurality of said zero-point information from the circuit receives as inputs a reproduction signal after the waveform equalization, and a state transition defined by the PR mode signal and the RLL mode signal, path of the plurality of zero point information
Based on the turn and , calculate the temporary discriminant value of the waveform equalized signal,
Based on an output error signal of the temporary discrimination means, which outputs the difference value between the temporary discrimination value and the reproduced signal after the waveform equalization as an error signal, the first filter coefficient is set to the minimum error signal. And the output bit clock of the resampling operation phase locked loop circuit separately for the second and third digital reproduction signals from the A / D conversion means. Resampling means for performing a resampling operation based on the above, and outputting the first and second sampling signals, and the first and second sampling signals separately based on the second and third filter coefficients. To the read signal of the two recording information tracks adjacent to both sides of the arbitrary one recording information recording track to be reproduced. Second and third transversal filters that separately output the pseudo crosstalk signal of, and second and third that separately and variably control the second and third filter coefficients based on the output error signal of the temporary discrimination means. And a subtraction circuit for subtracting the first and second pseudo crosstalk signals from the output signal of the first transversal filter and outputting the waveform-equalized reproduction signal. A recorded information reproducing apparatus characterized by the above. 3. A phase-locked loop circuit for inputting a reproduced signal after waveform equalization of the subtraction circuit and generating a system clock having a frequency which is a natural multiple of the bit clock based on the reproduced signal after waveform equalization. By providing the resampling operation phase locked loop circuit and the resampling means, the first to third digital reproduction signals from the A / D conversion means are separately provided to the first to third transversal filters. 2. The recording information reproducing apparatus according to claim 1, wherein the delay circuit delays the zero point information output from the phase comparator in the phase locked loop circuit while supplying the zero point information. 4. A phase locked loop circuit for generating a system clock having a frequency that is a natural number multiple of the bit clock based on the first reproduction signal from the reading means, and extracted from the A / D conversion means. A zero detector for detecting zero point information of the first digital reproduction signal is provided, and the resampling operation phase locked loop circuit and the resampling means are deleted to remove the first to the first from the A / D conversion means. 3. The recording according to claim 1, wherein three digital reproduction signals are separately supplied to the first to third transversal filters, and the delay circuit delays the zero point information from the zero detector. Information reproduction device. 5. A first reproduction signal read from an arbitrary recording information recording track to be reproduced of a recording information recording track group on a recording medium and the arbitrary recording information recording track to be reproduced. Reading means for obtaining the second and third reproduction signals separately read from each of the two recording information tracks adjacent to each other on both sides, and converting the first to third reproduction signals into digital signals separately. A / D conversion means for outputting first to third digital reproduction signals, and receiving the first digital reproduction signal as an input signal,
A resampling operation phase locked loop circuit for generating digital data resampled at a desired bit rate, generating a bit clock, and further detecting a zero cross point of the digital data to output zero point information; A first transversal filter for waveform equalizing the output digital data of the operational phase locked loop circuit based on a first filter coefficient, and the second and third digital reproduction signals from the A / D conversion means. Resampling operation for separately resampling operation based on the output bit clock of the phase-locked loop circuit and outputting first and second sampling signals; and the first and second sampling signals. Based on the second and third filter coefficients separately A first filtering section which separately filters and outputs first and second pseudo crosstalk signals corresponding to read signals of two recording information tracks adjacent to both sides of one arbitrary recording information recording track to be reproduced. A second and a third transversal filter; a delay circuit that outputs at least three consecutive zero-point information extracted from the resampling operation phase locked loop circuit in synchronization with a bit clock; A PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limited code of the reproduction signal, the plurality of zero point information from the delay circuit, and a waveform equalized reproduction signal. Input as input and the state transition determined by the PR mode signal and the RLL mode signal And a pattern of the plurality of zero point information, a temporary discrimination circuit for calculating a temporary discrimination value which is a target value of the waveform equalized reproduction signal, the temporary discrimination value and the waveform equalized reproduction signal And a subtractor that outputs a difference value between and as an error signal, the error signal output from the subtractor is input to a first input terminal, and the temporary determination value output from the temporary determination circuit is a second Based on the error signal output from the subtracter, an error selection circuit that is input to an input terminal and selects and outputs only an effective component of the error signal according to the tentative discriminant value; Of the second and third filter coefficients are separately controlled based on the error signal output from the error selection circuit, and a first coefficient generation unit that variably controls the filter coefficient of Yes Second and third coefficient generating means for performing variable control, and subtracting the first and second pseudo crosstalk signals from the output signal of the first transversal filter, respectively, and outputting the waveform-equalized reproduction signal. And a subtraction circuit for performing the recording information reproducing apparatus. 6. The error selection circuit receives the error signal output from the subtractor at the first input terminal, and outputs the error signal output from the temporary determination circuit at the second input terminal. Instead of the tentative discriminant value, the zero point information indicating the timing at which a sample point formed by resampling, which corresponds to the zero cross point to which the resampling operation phase locked loop circuit should be locked, is input, Only the sample point indicated by the information, or the sample point indicated by the zero point information and the sample points immediately before and after the sample point
6. The recorded information reproducing apparatus according to claim 5, wherein the error signal input to the input terminal of the above is selected, and the error signal is invalidated at other sample points. 7. The error selection circuit receives the waveform equalized reproduction signal output from the subtraction circuit in place of the error signal output from the subtractor in the first input terminal. , An effective component of a sample point corresponding to a zero-cross point to be locked by the resampling operation phase locked loop circuit in the reproduced signal after waveform equalization in accordance with the temporary discriminant value input to the second input terminal 6. The recorded information reproducing apparatus according to claim 5, wherein only the selected signal is selected and outputted, and the reproduced signal after the waveform equalization is invalidated at the other sample points. 8. The error selection circuit receives the waveform equalized reproduction signal output from the subtraction circuit, instead of the error signal output from the subtractor, at the first input terminal. , A sample formed by resampling, which corresponds to a zero-cross point to which the resampling operation phase locked loop circuit should be locked, instead of the provisional determination value output from the provisional determination circuit at the second input terminal The zero point information indicating the timing at which a point exists is input, and the waveform equalized reproduction signal input to the first input terminal is selected only at the sample point indicated by the zero point information, and the other samples are selected. The recorded information reproducing apparatus according to claim 5, wherein the reproduction signal after the waveform equalization is invalidated at a point. 9. The recording medium is an optical disk, and the reading means forms a first light beam spot on any one recording information recording track to be reproduced and reads the first reproduction signal. , Two recording information tracks adjacent to both sides of any one of the recording information recording tracks to be reproduced are respectively located on the front side and the rear side in the rotation direction of the optical disc with respect to the first light beam spot. recorded information reproducing apparatus as claimed in any one of claims 1 to 8, characterized in that to form the second and third light beam spot read independently said second and third reproduction signal. 10. A first memory for writing the digital data taken out from the digital operation phase locked loop circuit and then reading the digital data and outputting the digital data to the first transversal filter, and the first memory from the resampling means. First and second sampling signals are written separately and then read out and output separately to the second and third transversal filters, respectively. memory, respectively performs a write operation at the timing of the bit clock, recording information according to claim 1,2,5,6,7 or 8 further characterized in that the read operation at the timing of the clock newly generated in Playback device. 11. The reading means is provided for reading the first reproduction signal.
Output from the A / D conversion means and the A / D conversion means outputs the first digit
Output only the playback signal and eliminate the resampling means.
The resampling calculation phase synchronization loop
Based on the digital data extracted from the circuit
The first one having a time relationship different from each other by about one track scanning period
A delay means for generating the third to third digital data,
The first to third disks extracted from the delay means
The first digital with the minimum delay time among digital data
Before the data and the third digital data with the maximum delay time
Supply to the second and third transversal filters,
Converting the second digital data into the first transbar
3. The monkey filter is supplied to a monkey filter.
Recorded information reproduction device. 12. The method of claim 11, wherein reading means outputs only the first reproduction signal, the A / D converting means Outputs only the first digital reproduced signal, based on said first digital reproduced signal , For the first digital reproduction signal,
In the second and the second time relationships which differ by about one track scanning period
A delay means for generating a third digital reproduction signal ,
The first to third delay time of the digital reproduction signal is the minimum of the first digital reproduced signal wherein a maximum of the third digital reproduction signal of the delay time between the second and third
5. The recorded information reproducing apparatus according to claim 3 , wherein the second digital reproduction signal is supplied to the first transversal filter, and the second digital reproduction signal is supplied to the first transversal filter. 13. The reading means is provided for reading the first reproduction signal.
Output from the A / D conversion means and the A / D conversion means outputs the first digit
Output only the playback signal and eliminate the resampling means.
The resampling calculation phase synchronization loop
The delay digital data the issued to Ri taken from flop circuit
1 memory and Viterbi decoding the reproduced signal after waveform equalization
The decoded data obtained is output from the first memory.
1-track scanning period for each digital data
A second memory for generating a first decoded data and second decoded data has progressed about one track scanning period is delayed approximately between provided, the digital data output from said first memory 2. The recorded information reproducing apparatus according to claim 1, wherein the first and second transversal filters are supplied to the first transversal filter, and the first and second decoded data are supplied to the second and third transversal filters. 14. The reading means outputs only the first reproduction signal, the A / D converting means Outputs only the first digital reproduced signal, the first digital reproduced signal
A first memory for delaying the signal and decoded data obtained by Viterbi decoding the reproduced signal after waveform equalization, and one track scanning is performed for each first digital reproduced signal output from the first memory. The first memory, which is delayed by about a period, and the second memory, which generates the second decoded data, which is advanced by one track scanning period are provided, and the first memory is provided.
And supplying the first digital reproduction signal output from the memory to the first transversal filter and supplying the first and second decoded data to the second and third transversal filters. Claim 3 or
4. The recorded information reproducing device described in 4 .