JP2002197666A - Recording information reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for stably removing the crosstalk between layers on the signal processing side to solve such a problem that pits or grooves cannot be properly read out, or the like, when air bubbles, gaps, etc., exist on a spacer layer in a multi-layer disk whereon a plurality of recording layers are laminated. SOLUTION: Preliminary discrimination (convergence target setting) premised on the equalization of partial response is performed by a temporary discrimination circuit 33. The differential value between this preliminarily discriminated value and a reproduction signal after the waveform equalization is taken out from a subtractor 34 as an error signal and supplied to multiplier/LPFs 27 to 29, and the filer coefficients of transversal filters 21, 25, 26 are variably controlled so that the error signal becomes 0. The reproduction signal from a center layer to be reproduced is inputted to the transversal filter 21 and subjected to waveform equalization, and the reproduction signals from adjacent layers are inputted to the transversal filters 25, 26 and taken out as pseudo crosstalk signals, and substracted from the waveform equalized reproduction signals by substractors 30, 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a recorded information reproducing apparatus, and more particularly to a recorded information reproducing apparatus for reproducing a recorded information signal of an optical disk.

[0002]

2. Description of the Related Art In recent years, pits or grooves carried on an optical disk have been required to have a high density in accordance with high-density recording of information, and pits or grooves are formed in multiple layers and optically read from one side. Multilayer optical discs have been studied (for example, Japanese Patent Application Laid-Open No. Hei 9-138970).

[0003] The above-mentioned multilayer optical disk includes, for example, FIG.
There is a dual-layer optical disk (DualLayer Disk) as shown in FIG. In the figure, a two-layer optical disc is formed by injection-molding a transparent synthetic resin and forming a light-transmitting substrate 11 having a predetermined thickness.
No. 01, a pit or groove carrying first information is formed, and a reflective layer 11 made of a translucent film having a predetermined reflectance and transmittance on the pit or groove.
02 is formed by coating.

A pit or groove carrying second information is formed on one side of a substrate 1103 having a predetermined thickness, and a reflective layer 1 having a high reflectance is formed on the pit or groove.
104 is formed in close contact with the coating. Further, the reflective layer 1102 and the reflective layer 1104 are attached to each other using a light-transmitting ultraviolet-curable resin so as to face each other, and the ultraviolet-curable resin is cured to a predetermined thickness to have a light-transmitting property. The spacer layer 1105 is formed to form a two-layer optical disc.

Using the optical pickup (not shown) of the recording information reproducing apparatus, the first layer (referred to as layer 0) from the light transmitting substrate 1101 side is formed from the two-layer optical disk thus configured. When reading recorded information,
As shown in FIG. 39, the read beam of the optical pickup is focused on the reflective layer 1102, and the reflected light modulated by the pits or grooves formed on the reflective layer 1102 is read.

When reading recorded information of the second layer (hereinafter referred to as Layer 1), the recorded information reproducing apparatus transmits a read beam of the optical pickup through the reflective layer 1102 and the spacer layer 1105 of the two-layer optical disc. Then, the light is focused on the reflective layer 1104, and the light obtained by transmitting the reflected light modulated by the pits or grooves formed on the reflective layer 1104 again through the spacer layer 1105 and the reflective layer 1102 is read.

The recording information reproducing apparatus can appropriately select and read the information recorded on the two layers without turning over the both sides of the two-layer optical disc as described above. The recorded information can be reproduced instantaneously.

FIG. 40 shows a state in which a light beam emitted from the optical pickup of the recording information reproducing apparatus reflects each layer of the two-layer optical disk and reaches the optical pickup again. As shown in the figure, when reading information of Layer 0 of a two-layer optical disc, the incident light 1107 from the optical pickup is
Approximately 30% of the light is reflected by Layer 0, and becomes reflected light 1108 to reach the optical pickup.

When reading information on Layer 1 of a two-layer optical disc, the incident light 1107 from the optical pickup is read.
Is about 70%, although there is some absorption in the translucent substrate 1101 and the translucent reflective film 1102 of Layer 0.
It goes to Layer1, and in Layer1, about 80% of the light is reflected by the reflection film 1104, and the reflected light reaches Layer0 again in the spacer layer, is reflected again by about 30% in Layer0, and is reflected through Layer0. Light 1109 returns to the optical pickup. In this case, the reflected light 1108 at Layer 0 and the reflected light 1 at Layer 1 are viewed from the optical pickup.
The reflectivities of Layer 0 and Layer 1 are selected so that 109 is substantially equal.

Further, the spacer layer 1105 is formed of the reflective layer 110.
It is formed for the purpose of keeping the distance between the reflective layer 1 and the reflective layer 1104 constant. The refractive index of light is uniform and the transmittance is large. Also, when reading a two-layer optical disc, the reflected light from Layer 0 and the reflected light from Layer 1 are mixed and reflected by the optical pickup. When reading the recorded information of Layer 0, the focal point of the read beam is adjusted. Layer0
As shown by 1201 in FIG. 41A, the light beam applied to Layer 1 is defocused and greatly spreads.

FIG. 41 shows how a light beam emitted from an optical pickup is focused on one reflective layer of a two-layer optical disc and defocused on the other reflective layer. On the other hand, if the spot diameter of the light beam is very large compared to the size of the recorded pit or groove, it will not be modulated by the pit or groove, but will only be a DC offset. If the low-pass component is removed from the RF signal obtained by the high-pass filter, only the signal by Layer 0 can be extracted.

Similarly, as shown by reference numeral 1202 in FIG.
Only the signal by er1 can be extracted. Thus, 2
In an apparatus for reproducing information recorded on a layered optical disc, information recorded on two layers can be selectively read by appropriately selecting each layer from one side using an optical pickup and focusing a light beam.

[0013]

However, when the thickness of the spacer layer is formed with a width d 'smaller than the predetermined width d shown in FIG. 41A, reference numeral 1203 shown in FIG. As described above, when the reading beam is focused on Layer 0, L
The light beam irradiated on ayer1 does not spread so much,
Therefore, when reading a signal by Layer 0, interlayer crosstalk increases rapidly, and a modulated signal by Layer 1 cannot be ignored.

FIG. 42 is a graph showing the relationship between the spacer layer thickness and interlayer crosstalk. As shown in the drawing, as the thickness of the spacer layer becomes thinner than the predetermined thickness d, the interlayer crosstalk rapidly increases. Therefore, in a two-layer optical disk, the thickness d of the spacer layer is set practically to a lower limit of 30 μm, and the effect of interlayer crosstalk of each layer read from one side is suppressed.

Here, the optical pickup used for the two-layer optical disk is designed to be able to read a single-layer optical disk. For example, when the thickness of the light-transmitting substrate reaching the reflective layer of the single-layer optical disk is 0.6 mm. Is set so that the objective lens of the optical pickup is optimally focused by a reflective layer on a light-transmitting substrate having a thickness of 0.6 mm so that the aberration becomes zero. Therefore, when reading the information of Layer 0 and Layer 1 of the two-layer optical disc, respectively, when focusing the light beam on Layer 0, the thickness of the light-transmitting substrate 1101 affects the aberration, and focuses the light beam on Layer 1. In this case, the sum of the thickness of the light-transmitting substrate 1101 and the thickness of the spacer layer 105 affects the aberration.

As shown in FIG. 43, the sum of the thickness of the light transmitting substrate 1101 and the thickness of the spacer layer 1105 up to the reflection layer from which the light beam is read is the thickness when the aberration is 0 (FIG. 43).
(0.6 mm), the optical aberration (spherical aberration) gradually increases, so that the light beam cannot be appropriately stopped down, and finally the information of Layer 0 and Layer 1 cannot be read correctly. Therefore, by forming the thickness of the spacer layer and / or the translucent substrate reaching each reflective layer of the two-layer optical disc within a predetermined range, the aberration of the light beam focused on each reflective layer can be read. It is set almost equally within the range.

In FIG. 43, Layer 0 and Layer 1 are arranged evenly displaced from the position corresponding to the reflection layer of the single-layer optical disc via the light-transmitting substrate having a thickness of 0.6 mm, and each information is read. The aberration is set to slightly deviate from the optimum point (ie, 0 aberration). Note that the allowable value of the aberration is such that the position of each reflective layer of the two-layer optical disc is within a range of -50 μm to +60 μm at the maximum from the position of the reflective layer of the single-layer optical disc having a light-transmitting substrate thickness of 0.6 mm. Otherwise, signals cannot be read properly from each layer.

That is, the thickness and aberration of each layer must be strictly controlled, and the productivity is low. Translucent substrate 110
By strictly controlling the thickness variation of the spacer layer 1, the spacer layer 1
Although it is conceivable to loosen the tolerance of the thickness of the layer 105, the mass productivity is also significantly reduced due to a low yield.

Also, if there are bubbles or gaps in the spacer layer, the refractive index of the light in that portion fluctuates greatly, and due to irregular reflection, the transmittance of the light beam is greatly reduced or the aberration is significantly deteriorated. Therefore, the optical pickup cannot read pits or grooves correctly. Therefore, it is general that the ultraviolet curable resin used for the spin coating is subjected to a vacuum defoaming treatment or the like in advance. However, when the spacer layer is formed by the spin coating method, the substrate is not spind at high speed (during shaking). Bubbles may be entrained from the inner peripheral side of the container. Most of the entrained air bubbles come off the outer peripheral edge during high-speed spinning, but there is a problem that it takes a long time to bond the substrates and that some air bubbles remain, so that mass productivity is deteriorated.

For the above reasons, a method for stably removing interlayer crosstalk on the signal processing side has been desired.

The present invention has been made in view of the above points,
By adaptively and stably removing interlayer crosstalk,
It is an object of the present invention to provide a recording information reproducing apparatus capable of increasing the productivity of a multilayer recording medium in which information is recorded on each of a plurality of recording layers.

It is another object of the present invention to provide a recording information reproducing apparatus capable of rapidly and reliably reproducing recorded information on a multilayer recording medium.

Another object of the present invention is to provide a recording information reproducing apparatus capable of accurately reproducing recording information of a multilayer recording medium on which high-density recording has been performed by using two-dimensional partial response equalization including crosstalk removal. To provide.

Still another object of the present invention is to provide a recorded information reproducing apparatus capable of reproducing not only a plurality of laser beams but also signal processing using a single laser beam.

Still another object of the present invention is to convert a signal having an integral system characteristic into a partial response characteristic PR.
An object of the present invention is to provide a recording information reproducing apparatus which is an effective means for equalizing (a, b, b, a).

[0026]

In order to achieve the above object, a first aspect of the present invention is an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked. Reading means for reading a piece of recording information to obtain a first read signal, and a recording layer existing on at least one of the upper and lower sides of any one recording layer of the multilayer recording medium to be read by the first reading means Read the recorded information of the second
A second reading means for obtaining a first reading signal, a first filtering means for waveform-equalizing the first reading signal based on a first filter coefficient, and a second filtering coefficient for the second reading signal. A second filtering means for filtering and outputting a pseudo-crosstalk signal based on a target value of the reproduced signal after waveform equalization, which receives at least a reproduced signal after waveform equalization as an input, and presumes partial response equalization. Provisional determination means for calculating a temporary determination value, a first subtraction means for outputting a difference value between the provisional determination value and the reproduced signal after waveform equalization as an error signal, and an error signal output from the first subtraction means. A first coefficient generating means for variably controlling a first filter coefficient so that an error signal is minimized, and a second filter function based on an error signal output from the first subtraction means. And a pseudo-crosstalk signal output from the second filtering means and the output signal of the first filtering means and the pseudo-crosstalk signal output from the second filtering means. And a second subtracting means for outputting a reproduction signal after the waveform equalization of the recording information.

According to the present invention, the output signal of the first filtering means for equalizing the waveform of the first read signal obtained by reading the record information of any one recording layer to be reproduced, and the above one arbitrary one An arbitrary pseudo-talk signal to be reproduced by subtracting the pseudo-crosstalk signal output from the second filtering means for filtering the second read signal obtained by reading the recording information of the recording layer existing at least above or below the recording layer. Since the reproduction signal after the waveform equalization of the recording information of one recording layer is output, the pseudo crosstalk signal, that is, the interlayer crosstalk can be adaptively canceled.

In order to achieve the above object, a second aspect of the present invention determines whether or not the first read signal, the output signal of the first filtering means, or the zero-cross point of the waveform-equalized reproduced signal is present. A zero-crossing discriminating means for outputting the zero-point information, and receiving the zero-point information and the reproduced signal after the waveform equalization as inputs, and providing the type of the partial response equalization and the first read signal. The provisional determination value of the reproduced signal after waveform equalization is determined based on a state transition determined by the type of the run-length limiting code.

According to a third aspect of the present invention, there is provided a multi-layered recording medium having a structure in which a plurality of recording layers are stacked, the recording information of any one recording layer to be reproduced. Reading means for obtaining a first read signal by reading the information, and recording information of a recording layer existing on at least one of the upper and lower sides of any one of the recording layers of the multilayer recording medium to be read by the first reading means A second reading unit for reading the first and second read signals to convert the first and second read signals into digital signals, respectively, and converting the first and second read signals into digital signals.
A / D conversion means for outputting a digital reproduction signal of the first digital reproduction signal, digital data sampled from the first digital reproduction signal at a desired bit rate by resampling operation, and generating a bit clock. A first resampling operation phase locked loop circuit for detecting a zero cross resampling point of the digital reproduction signal of 1 and outputting 0 point information; and a first filter coefficient for outputting digital data of the resampling operation phase locked loop circuit. A first transversal filter that performs waveform equalization based on the above, a delay circuit that delays zero-point information by a predetermined time at each bit sampling timing, a PR mode signal that indicates the type of partial response equalization, and a first reading operation. RLL mode indicating the type of signal run-length limiting code A signal, a plurality of 0-point information from a delay circuit, and a reproduced signal after waveform equalization are input, and a waveform is formed based on a state transition determined by a PR mode signal and an RLL mode signal and a pattern of a plurality of point information. A first determining means for calculating a temporary determining value of the reproduced signal after the equalization, a first subtracting means for outputting a difference value between the temporary determining value and the reproduced signal after the waveform equalization as an error signal, and a first subtracting means. A first coefficient generation means for variably controlling a first filter coefficient based on the output error signal so that the error signal is minimized, and a second digital reproduction signal from the A / D conversion means. Resampling means for performing a resampling operation based on an output bit clock of the sampling operation phase locked loop circuit and outputting a sampling signal; A second transversal filter for filtering based on the number and outputting a pseudo-crosstalk signal corresponding to a read signal of at least one recording layer above and below any one recording layer to be reproduced; A second coefficient generation means for variably controlling a second filter coefficient based on the error signal output from the subtraction means such that the error signal is minimized;
Second subtraction means for subtracting the pseudo crosstalk signal from the output signal of the first transversal filter and outputting a reproduced signal after waveform equalization is provided.

In the third aspect of the invention, the provisional discrimination means performs provisional discrimination (setting of a convergence target) on the premise of partial response equalization, and reproduces the provisional discrimination value and the waveform after being extracted from the second subtraction means after equalization. By supplying the difference value from the signal to the first and second coefficient generation means as an error signal and controlling the error signal to be 0, the operation of the apparatus can be made to converge toward a clear value. it can. Also, a resampling operation phase locked loop circuit can be used.

In order to achieve the above object, a fourth aspect of the present invention is directed to a fourth aspect of the present invention, wherein the provisional determination means according to the third aspect of the present invention uses the at least one of the PR mode signal and the RLL mode signal as a fixed value to output a waveform-equalized reproduced signal. A temporary discriminant value is calculated, and the first subtraction means outputs a difference value between the provisional discrimination value from the provisional discrimination means and the reproduced signal after waveform equalization output from the second subtraction means as an error signal. And

According to a fifth aspect of the present invention, a reproduced signal after waveform equalization output from a second subtracting means is inputted, and a zero cross point of the reproduced signal after waveform equalization is detected. A zero detector for outputting as zero point information is provided, and the delay circuit outputs the zero signal output from the zero detector.
It is characterized in that point information is delayed.

In order to achieve the above object, according to an eighth aspect of the present invention, the first and second filtering means provide a partial response characteristic PR (a, b, It is characterized by waveform equalization to b, a).

According to a ninth aspect of the present invention, a first read signal or a second read signal, an output signal of a digital operation phase locked loop circuit and an output signal of a resampling operation phase locked loop circuit are provided. One or all of the signals are recorded on a memory medium and read out later to synchronize the signals and perform a desired crosstalk canceling operation.

According to the present invention, reproduction can be performed using a single beam. Furthermore, according to the present invention, a signal equivalent to a crosstalk signal obtained from an arbitrary layer above and below a target layer can be obtained in a time-division manner, so that the resampling means can be omitted.

Further, in order to achieve the above object, the tenth
The first invention provides a first reading means for reading recording information of an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked, to obtain a first reading signal. And second reading means for reading recording information in at least one of the upper and lower recording layers of any one of the recording layers of the multilayer recording medium to be read by the first reading means to obtain a second reading signal. And the first read signal
A first filtering means for filtering based on the filter coefficient of the second, a second filtering means for filtering the second read signal based on the second filter coefficient and outputting a pseudo crosstalk signal, Detecting means for receiving an output reproduction signal of the filtering means as an input, comparing the input reproduction signal with a predetermined fixed threshold value, and detecting a zero-cross sample value of the input signal; , A coefficient generating means for variably controlling the first and second filter coefficients, and an output signal of the first filtering means and a pseudo-crosstalk signal outputted from the second filtering means are subtracted and reproduced. And a subtracting means for outputting a reproduction signal after waveform equalization of the recording information of any one recording layer. In the present invention, only the crosstalk removing function is used without using the partial response equalization.

Further, in order to achieve the above-mentioned object, the present invention reads the recording information of any one recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are laminated. A first reading means for obtaining a first reading signal; and reading of recording information on at least one of the upper and lower recording layers of any one of the recording layers of the multilayer recording medium to be read by the first reading means. Second reading means for obtaining a second reading signal, A / D converting means for separately converting the first and second reading signals into digital signals and outputting the first and second digital reproduction signals, and Receiving the first digital reproduction signal as an input signal, generating digital data resampled at a desired bit rate, generating a bit clock, and further generating a zero cross point of the digital data. Resampling phase locked loop circuit for detecting zero point information and outputting zero point information, and a first transversal for waveform equalizing output digital data of the resampling phase locked loop circuit based on a first filter coefficient Resampling means for performing a resampling operation on the second digital reproduction signal from the A / D conversion means based on an output bit clock of the phase locked loop circuit and outputting a sampling signal; A second transversal filter for filtering a signal based on a second filter coefficient and separately outputting a pseudo crosstalk signal corresponding to a first read signal of an arbitrary recording layer to be reproduced; Sampling operation Synchronized with the bit clock from the phase locked loop circuit A delay circuit that outputs at least three consecutive zero point information at each bit sampling timing, a PR mode signal indicating the type of partial response equalization, and an RLL mode signal indicating the type of the run-length limiting code of the reproduction signal. , A plurality of zero point information from a delay circuit and a reproduced signal after waveform equalization as inputs, and a PR mode signal and R
A tentative judgment circuit for calculating a tentative judgment value serving as a target value of the reproduced signal after waveform equalization based on a state transition determined by the LL mode signal and a plurality of zero point information patterns; A subtractor that outputs a difference value from the reproduction signal as an error signal; an error signal output from the subtractor is input to a first input terminal; and a tentative judgment value output from a tentative judgment circuit is input to a second input terminal. And an error selection circuit that selects and outputs only valid components of the error signal in accordance with the provisional determination value, and an error signal that determines the first filter coefficient based on the error signal output from the subtractor. First coefficient generating means for variably controlling the filter coefficient to be minimized, second coefficient generating means for variably controlling a second filter coefficient based on an error signal output from the error selection circuit, and first transversal H From filter output signal is obtained by a structure and a subtracting circuit for outputting a pseudo crosstalk signal respectively subtracted to waveform equalization after the reproduction signal of the.

According to the present invention, a signal indicating an uncertain error value is invalidated by the error selection circuit, and only a likely error signal is taken out as an effective component. Therefore, the distortion of the reproduced signal is large, and the partial response cannot be equalized. Even in this case, the deviation from the target value is small, the error signal can be correctly extracted, and as a result, the error rate can be improved.

In order to achieve the above object, according to the present invention, there is provided the above-described error selection circuit, wherein an error signal output from a subtractor is input to a first input terminal, and a temporary signal is input to a second input terminal. Instead of the provisional determination value output from the determination circuit, zero point information indicating the timing at which a sample point formed by resampling exists, which corresponds to a zero cross point to be locked by the resampling operation phase locked loop circuit, is input. The error signal input to the first input terminal is selected only at the sample point indicated by the zero point information or at the sample point indicated by the zero point information and the sample point immediately before and after the sample point, and the error signal is selected at the other sample points. It is characterized by invalidation.

According to the present invention, among the output error signals of the provisional determination means, a signal indicating an uncertain error value which is provisionally determined by the error selection circuit as the target value farthest from the zero point is invalidated (replaced with 0). Output), and only a likely error signal is taken out as an effective component. Therefore, based on only accurate data, a second filter coefficient which is a filter coefficient of a second transversal filter for generating a pseudo crosstalk is generated. can do.

To achieve the above object, according to the present invention, the above-mentioned error selection circuit is provided with a first input terminal, in place of an error signal output from a subtractor, a waveform output from a subtraction circuit. A sample corresponding to a zero-crossing point to be locked by the resampling operation phase locked loop circuit of the waveform-equalized reproduced signal according to the provisional determination value input to the second input terminal after the equalized reproduced signal is input. Only the effective components of the points are selected and output, and at other sample points, the reproduced signal after waveform equalization is invalidated.

Further, in order to achieve the above object, according to the present invention, the above-mentioned error selection circuit is provided with a first input terminal, instead of an error signal output from a subtractor, a waveform output from the subtraction circuit. The regenerated signal is input to the second input terminal, and the second input terminal is formed by resampling corresponding to the zero-cross point to be locked by the resampling operation phase locked loop circuit, instead of the temporary determination value output from the temporary determination circuit. Zero point information indicating the timing at which the selected sample point exists is selected, and the waveform-equalized reproduction signal input to the first input terminal is selected only at the sample point indicated by the zero point information, and the other sample points are selected. Is characterized in that the reproduced signal after waveform equalization is invalidated.

[0043]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a recorded information reproducing apparatus according to the present invention. In this embodiment, as an example of a recording medium on which recording information to be reproduced is recorded, a multi-layer optical disc in which three recording layers of a lower layer, a middle layer (center layer) and an upper layer are stacked with a spacer layer interposed therebetween is taken as an example. explain. As shown in the plan view of FIG. 2, three laser beams emitted from the optical head (not shown) of this embodiment are divided into three beam spots B0 and B0.
B1 and B2 are the same tracks Ti of the above three recording layers.
Separately and in focus.

As shown in FIG. 2, when a recorded information signal is reproduced from an arbitrary track Ti on the center layer of the optical disk, a reproduction-only light beam spot B0 is set on the track Ti.
Is formed so as to converge on the center layer of the laser beam.
1 is formed so as to converge, and a beam spot B2 is formed so as to converge on an upper layer track Ti existing above the center layer. Here, since the track Ti of the center layer and the track Ti of the upper layer are recorded at the same rotational position in the vertical direction (vertical direction) with respect to the medium surface of the optical disk, the recording layers are They are adjacent.

The three beam spots B0, B1,
B2 keeps the beam spot B1 at the rear position (or front position) and the beam spot B2 at the front position (or rear position) in the rotation direction of the optical disc around the center beam spot B0. Tracked. These three beam spots B0, B1, B
The reflected light from 2 is separately converted into a read signal through a known optical system.

Of the above read signals, the read signal of the center layer to be reproduced (center layer) is the A / D converter 1 of FIG.
1, the read signal of the lower adjacent layer (lower layer) is supplied to the A / D converter 12 of FIG. 1, and the read signal of the upper adjacent layer (upper layer) is converted to the A / D converter of FIG. Is supplied to the vessel 13. The A / D converters 11, 12, and 13 sample the input read signal with a master clock and convert it into a digital signal.
5 and 16, where the amplitude is controlled to be constant, and automatic threshold control (ATC) for appropriately controlling the threshold of the binary comparator by direct current (DC).

The output signal of the AGC / ATC circuit 14 is supplied to a resampling DPLL 17. The resampling DPLL 17 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block. The resampling DPLL 17 resamples (samples out) digital data obtained by sampling an input signal at a desired bit rate.
It is generated by calculation and supplied to the transversal filter 21 through the delay adjuster 20. Also, resampling D
The PLL 17 detects that the read signal crosses the zero level, and supplies the obtained zero-point information to the tap delay circuit 32 to be described later through the delay adjuster 22.

Further, the resampling DPLL 17 generates a bit clock BCLK for bit sampling, and also generates a parameter T_ratio indicating an internally dividing ratio for performing resampling operation, and sends them to the resampling circuits 18 and 19. The digital signals from the AGC / ATC circuits 15 and 16 are re-sampled by the bit clock BCLK at a rate indicated by the parameter T_ratio. The bit clock BCLK is a missing clock (Punctured Clock). The zero point information indicates the point where bit sampling data crosses the zero level in bit clock units.

The signals extracted from the resampling circuits 18 and 19 are supplied to transversal filters 25 and 26 through delay adjusters 23 and 24, respectively.
The transversal filter 21 and the transversal filters 25 and 26 receive filter coefficients (tap coefficients) from multipliers / low-pass filters (LPFs) 27, 28 and 29, respectively, and perform filtering processing of characteristics according to the input coefficients. Perform on the input signal.

The transversal filter 21 performs a waveform equalization process based on the tap coefficient (filter coefficient) from the multiplier / LPF 27, and performs intersymbol interference with a signal before and after a read signal from a desired layer to be reproduced. Reduce the effects of
The read signal after the output waveform equalization of the transversal filter 21 is supplied to a temporary discriminating circuit 33 through subtracters 30 and 31, which will be described later, where the delayed signal from the tap delay circuit 32 and the type of partial response (PR) And an RLL mode signal indicating a run-length limited code length (minimum inversion interval or maximum inversion interval) of the signal recorded on the optical disk, and outputs a provisional determination result based on these.

The result of the tentative judgment and the input signal of the tentative judgment circuit 33 (the output signal of the subtractor 31) are subtracted in a subtractor 34, and the difference is used as an error signal as an error signal in an inverter 35.
Is supplied to the multiplier / LPF 27, where it is multiplied by the tap output of the transversal filter 21 to detect the correlation, and is integrated by the LPF. The output integrated value of the multiplier / LPF 27 is input to the transversal filter 21 as a filter coefficient (tap coefficient) of the transversal filter 21 for setting the value of the error signal to 0.

The above-mentioned transversal filter 21, multiplier / LPF 27, provisional judgment circuit 33, tap delay circuit 3
2. The feedback loop including the subtractor 34 and the inverter 35 is based on a well-known LMS algorithm. However, the provisional determination circuit 33 is a circuit proposed by the present inventor, and is a provisional circuit based on partial response equalization. The determination (convergence target setting) is performed.

Here, to further explain the partial response (PR) characteristics, for example, PR (a, b, b,
When the characteristic of a) is added to the solitary wave and equalized, the equalized waveform is 0, a, a + b, 2a, 2b, a + 2b, 2a + 2 in the case of (1, 7) RLL, as is well known.
Take 7 values of b. When these seven values are input to the Viterbi decoder, the original data (input value) and the reproduced signal (output value) after PR equalization are restricted by the past signal, and this and (1, 7)
It is known that the use of the fact that the input signal "1" does not continue more than twice by the RLL can be represented by a state transition diagram as shown in FIG.

In FIG. 3, S0 to S5 indicate states determined by the immediately preceding output value. From this state transition diagram, for example, when in the state S2, when the input value is a + 2b, the output value becomes 1, and the state transits to the state S3. However, it can be seen that no other input value is input, and that if it is, it is an error.

Here, the value Z of the 0 point information is "
1 "indicates a zero cross point, which is represented by a value" a + b "in the state transition diagram of PR (a, b, b, a) shown in FIG.
It occurs in the process of transition from → S2 or state S4 → S5. In this case, in FIG. 3, the right half states S2, S3, and S4 are paths having positive values (when normalized to a + b = 0, a
+ 2b, 2a + 2b, or 2b), and the left half states S5, S0, and S1 have negative value paths (a + b = 0).
(0, a, or 2a), it is possible to determine whether the path is a positive path or a negative path by referring to a value before or after the zero cross point.

Furthermore, if the interval from one zero cross point to the next zero cross point is known, that is, from state S2 to state S5, or from state S5 to state S5
If the number of transitions up to 2 is known, the path is determined, and possible values become clear for each sample point.

In the above state transition diagram, when a value other than “a + b” is not a zero cross point, the value Z of the zero point information is “0”. From this state transition diagram, two zero cross points (Z = 1) are not taken out consecutively, and in the case of RLL (1, X), at least one zero cross point is present between adjacent Z = 1. 0 "exists (when the value Z of the 0 point information changes from 1 → 0 → 1, that is, when the state S1 → S2 → S4 → S5 or the state S4 → S5 → S1 → S2). In addition,
In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1.

In an actual signal, due to the influence of noise and the like,
It is fully expected that the zero cross point itself will be erroneously detected, but in the case of feedback control, if the probability of making a correct decision exceeds the probability of making a mistake, it should converge in the correct direction. For the integration process,
It is considered that a single noise is not a problem in practical use.

Focusing on the above points, the provisional determination circuit 33 identifies the value Z of the 0 point information input from the tap delay circuit 32 for each bit clock cycle, and the five values of the five successive clock cycles are identified. Whether all are "0", whether only the first of the five values is "1", whether only the last of the five values is "1",
It is determined whether the first and last values of the above five values are "1" and the remaining three values are "0".

In these patterns, when the value Z of the 0-point information of interest is "0", the values Z of the 0-point information on both sides are both "0". In this case, the signal waveform is Since the pattern is stuck on the positive side or the negative side, a large value P1 is calculated when any of these patterns is satisfied.

When none of the above patterns is used,
Five zero point information values Z for five consecutive clock cycles
Is "01010", and in the case of this pattern, based on the RLL mode signal, it is determined whether or not RLL (1, X) partial response equalization. Since this pattern may occur only in the case of RLL (1, X), a small value P2 is calculated in the case of RLL (1, X).

When the value Z of the five 0-point information in five consecutive clock cycles is not “01010”,
The value Z of the 0 point information is “01001”, “100”
It is determined whether the pattern is any one of “10”, “00010” and “01000.” In these four patterns, the value Z of the 0-point information of interest is set to “0”.
, One of the values of the zero point information Z adjacent on both sides is “1”. If it is any of the four patterns, or if it is "01010" and R
When it is determined that the LL mode is not (1, X), P
An intermediate level value P3 between 1 and P2 is calculated.

When the value P1, P2 or P3 is calculated, if the reproduced signal after the waveform equalization at the current time inputted to the provisional decision circuit 33 is 0 or more, the final provisional decision level Q is changed to P1, P2 or P2 at that time. The value of P3 is used. When the value is negative, the final provisional determination level Q is inverted from the polarity of the value of P1, P2 or P3 at that time. If none of the above, the final provisional judgment level Q is set to 0.

As described above, the provisional determination circuit 33 includes a PR mode signal indicating the type of the partial response equalization, an RLL mode signal indicating the type of the run-length limiting code of the reproduction signal, and a plurality of signals from the tap delay circuit 32. The zero point information and the reproduced signal after the waveform equalization output from the subtractor 31 are received as inputs, and the waveform equalization is performed based on the state transition determined by the PR mode signal and the RLL mode signal and a plurality of zero point information patterns. The provisional determination level Q of the reproduction signal is calculated. This provisional judgment level Q is used as a target value in the subtractor 3 of FIG.
4 and the difference from the reproduced signal after waveform equalization, which is an actual signal, is taken as an error signal.

On the other hand, the signals extracted from the resampling circuits 18 and 19 in FIG.
A fixed delay is given by 3 and 24, and the time is adjusted roughly with a pseudo crosstalk to be described later and input to the transversal filters 25 and 26. Tap coefficients (filter coefficients) are applied to the transversal filters 25 and 26.
The multipliers and LPFs 28 and 29 that supply the subtractor 3
The error signal output from the input signal 4 is input, where the error signal is multiplied by the tap output of the transversal filters 25 and 26 to extract the correlation of the adjacent layer signal, and the correlation value is integrated by the LPF to obtain the transversal filter 25. Input to 26.

In this way, the tap coefficients (filter coefficients) of the transversal filters 25 and 26 are updated in accordance with the correlation values of the adjacent layer signals, and the lower and upper layers from the transversal filters 25 and 26 The pseudo crosstalk signal corresponding to the read signal is extracted. The output pseudo crosstalk signals from the transversal filters 25 and 26 are subtracted by the subtracters 30 and 31 from the reproduction signal from the layer to be reproduced after the waveform equalization from the transversal filter 21. As a result, the subtractor 31 cancels and removes the crosstalk in the reproduction signal of the layer to be reproduced after the waveform equalization from the transversal filter 21 and outputs the signal as a reproduction signal having a good S / N. In this embodiment, since the feedback processing is performed, a stable operation can be realized.

In this embodiment, the intersymbol interference removal block of the reproduction signal of the track to be reproduced including the transversal filter 21 and the transversal filter 25
In each of the pseudo-crosstalk generation blocks based on the reproduction signals from the adjacent layers including the control signals 26 and 26, each tap coefficient (filter coefficient) is controlled so that the same error signal becomes 0. do not do.

As a secondary effect corresponding to partial response equalization, an error signal can be extracted from information on all sampling points. The crosstalk component can be clearly identified when the reproduction signal of the desired layer is flat (a state where the inversion interval is large).
This level cannot be determined if partial response equalization is not supported.

On the other hand, in this embodiment, the value is 0
Alternatively, since convergence toward a definite value such as 2a + 2b is performed, and an error from this value is correlated with a crosstalk component as an error signal, accurate and rapid convergence is possible. Other values (a, 2a, a +
2b, 2b, etc.). Therefore, assuming that the average inversion interval of the signal is 5T (T is a bit period), it is easy to imagine that the convergence is five times or more, and the convergence in the wrong direction does not occur.

When the resampling DPLL 17 is used, the sampling clock used for the A / D converter 11 is not synchronized with the bit clock, and the same applies to the sampling clock of the reproduction signal of the adjacent track. The constant phase shift can be absorbed by the pseudo crosstalk generator (transversal filters 25 and 26).
It can be regarded as a resampling arithmetic unit itself. )
However, when the frequency is shifted, the sampling time interval is not constant, so that the conventional pseudo-crosstalk generator cannot cope with it.

On the other hand, in this embodiment, the resampling devices 18 and 19 use the resampling devices 18 and 19 to regenerate the reproduced signal from the adjacent layer using the internal ratio T_ratio and the bit clock BCLK generated by the resampling DPLL 17 at the time of the resampling operation. Because sampling operation is performed,
Can cope with frequency deviation. The phases are roughly adjusted by delay adjusters 23 and 24 at the subsequent stage, and the rest is left to a pseudo crosstalk generator using transversal filters 25 and 26. Thereby, the resampling DPLL 17 can be used. In addition,
The reason why the delay adjusters 23 and 24 are arranged after the resampling units 18 and 19 is that the number of stages of the delay flip-flops can be reduced, so that the delay adjusting units 23 and 24 are functionally arranged before the resampling units 18 and 19. You may.

The resampling DPLL 17 is independent of AG
Since it is sandwiched between the C / ATC circuit 14 and the intersymbol interference removal block of the reproduced signal of the layer to be reproduced including the transversal filter 21, and the loop is completed in its own block, Exact convergence can be expected. On the other hand, when the resampling DPLL 17 is not used, an external voltage controlled oscillator (VCO) is required.
Since bit sampling is performed by the / D converter, A /
Since a PLL loop including a D converter is formed and a high-speed A / D converter is required, the cost increases.

When the resampling DPLL 17 is not used, since a PLL loop including an AGC / ATC circuit is formed, the PLL loops may interfere with each other and may not converge in an appropriate direction. It is conceivable that all the loops and PLL loops are put out and constituted by analog circuits, but a voltage controlled amplifier (VCA)
And the adverse effects of aging and component variations unique to analog circuits. From the above, it is clear that a configuration using a resampling DPLL is desirable as in this embodiment. In particular, an optical disc is suitable for oversampling because the recording / reproducing system has a high-frequency attenuation characteristic in frequency characteristics.

Next, the simulation waveform of this embodiment will be described. 4 to 7 show simulation waveforms when crosstalk cancellation is not performed, and the horizontal axis is a time axis. In FIG. 4, I, II, and III indicate the output signal waveform of the resampling DPLL 17, the pseudo crosstalk signal waveform from the transversal filter 25 or 26, and the input signal waveform of the temporary discriminating circuit 33. FIG.
6 shows a tap coefficient of the transversal filter 25 or 26, and FIG.

Further, in FIG. 7, IV is a resampling DPL.
An error flag obtained by comparing the output signal of L17 with the recording signal, and V is an error flag obtained by comparing reproduction data obtained by further Viterbi decoding the signal output through the subtractor 31 with the recording signal. Even though the operation of this embodiment is not performed and the crosstalk canceller is off, the error flag V of the decoded signal has a low frequency of occurrence of the error flag IV of the output signal of the resampling DPLL 17 and the error is reduced. However, this is a transversal filter 21
And Viterbi decoding.

On the other hand, FIGS. 8 to 11 show simulation waveforms when crosstalk is canceled according to this embodiment, and the horizontal axis is the time axis. Another signal is added to the main signal in advance as crosstalk. In FIG.
VI, VII and VIII show the output signal waveform of the resampling DPLL 17, the pseudo crosstalk signal waveform from the transversal filter 25 or 26, and the input signal waveform of the temporary discriminating circuit 33. As can be seen from the figure, the pseudo crosstalk signal waveform has converged to a steady state in a short time after the start of the operation, and the amplitude of the input signal waveform of the temporary discrimination circuit 33 becomes substantially constant after the crosstalk signal is removed. ing.

FIG. 9 shows a transversal filter 2.
FIG. 10 shows an eye pattern of an input signal of the provisional determination circuit 33. It can be seen that the tap coefficient is variable and the eye pattern is open compared to the case where the crosstalk canceller is off. Further, FIG.
IX is an error flag obtained by comparing the output signal of the resampling DPLL 17 with the recording signal, and X is an error flag obtained by comparing reproduced data obtained by further Viterbi decoding the signal output through the subtractor 31 with the recording signal. It is.

As can be seen by comparing FIGS. 7 and 11, the error flag obtained by comparing the output signal of the resampling DPLL 17 with the recording signal is the same regardless of whether or not the crosstalk canceller operation is performed. However, it can be seen that there is almost no error in Viterbi-decoded reproduced data when the crosstalk canceller operation is performed, compared to when the crosstalk canceller operation is not performed. That is, according to the present embodiment, it can be seen that errors that could not be removed by Viterbi decoding can be completely removed except immediately after the start of operation.

Next, another embodiment of the present invention will be described. FIG. 12 shows a second embodiment of the recorded information reproducing apparatus according to the present invention.
FIG. 2 is a block diagram of the embodiment. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the second embodiment shown in FIG. 12, A / D converters 11 to 13 are used.
And the use of digital pre-equalizers (PreEQ) 37-39 between the AGC / ATC circuits 14-16.

FIG. 13 is a block diagram showing a third embodiment of the recording information reproducing apparatus according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the third embodiment shown in FIG. 13, A / D converters 11 to 11 are used.
13, an analog pre-equalizer (PreE
Q) There is a feature in that 41 to 43 are used.

FIG. 14 is a block diagram showing a fourth embodiment of the recording information reproducing apparatus according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The fourth embodiment of FIG. 14 is characterized in that a provisional determination circuit 45 for performing determination using a fixed threshold value without using zero point information for provisional determination is provided. That is, the reproduced signal after the waveform equalization taken out from the subtractor 31 is output to the Viterbi decoding circuit at the subsequent stage, while being supplied to the provisional decision circuit 45, where it is compared with a predetermined threshold value to make a provisional decision. .

The result of the tentative judgment by the tentative judgment circuit 45 and the input signal of the tentative judgment circuit 45 (the output signal of the subtractor 31) are subtracted by the subtractor 34, and the difference value is inverted by the inverter 35 as an error signal. After that, the multiplier
The signal is supplied to the LPF 27 and is set as a filter coefficient (tap coefficient) of the transversal filter 21 for setting the value of the error signal to 0, and is input to the transversal filter 21. In this embodiment, the resampling DPL
Since the zero point information from L17 is not used, the delay adjuster 22 and the tap delay circuit 32 become unnecessary.

FIG. 15 is a block diagram showing a fifth embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 15, a read signal of a layer to be reproduced at the center among three layers existing in a layer group formed on the optical disc is input to a voltage control amplifier (VCA) 47 to read a lower adjacent layer. The signal is input to the VCA 48, and the read signal of the upper adjacent layer is input to the VCA 49 to control the level and DC.

The output read signals from the VCAs 47, 48, and 49 are supplied to A / D converters 50, 51, and 52 at the next stage, sampled by the master clock, converted into digital signals, and fixed at the next stage. EQ) 53, 5
After the equalizer characteristics are added at 4, 55, AGC A
It is supplied to the TC detection circuits 56, 57 and 58, where the automatic amplitude control (AGC) in which the amplitude is controlled to be constant and the automatic threshold control (ATC) in which the threshold of the binary comparison is appropriately controlled in a direct current (DC). And a DC control signal are generated. The gain control signals are VCA 47, 4
8 and 49 to variably control the gain. Thus, in this embodiment, AGC and ATC can be performed together with the analog circuit.

FIG. 16 is a block diagram showing a recording information reproducing apparatus according to a sixth embodiment of the present invention. 15, the same components as those in FIGS. 1 and 15 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 16, a read signal of a layer Ti to be reproduced at the center among three layers existing in a layer group formed on the optical disc is an analog AGC / ATC circuit 61.
The read signal of the lower adjacent layer Ti-1 is input to the analog AGC / ATC circuit 62, and the read signal of the upper adjacent layer T
The read signal of i + 1 is converted to an analog AGC / ATC circuit 63
And the amplitude is controlled to be constant, and the threshold value of the binary comparator is appropriately controlled.

The output read signals of the AGC / ATC circuits 61, 62, 63 are supplied to A / D converters 50, 51, 52 at the next stage.
The digital signal is sampled by the master clock and converted into a digital signal, and only the output of the A / D converter 50 is given an equalizer characteristic by a fixed equalizer (EQ) 53 at the next stage. In this embodiment, AGC and ATC are performed only by AGC / ATC circuits 61, 62 and 63 which are analog circuits.

FIG. 17 is a block diagram showing a seventh embodiment of the recorded information reproducing apparatus according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The seventh embodiment of FIG. 17 is characterized in that zero-point information is extracted from a reproduced signal after waveform equalization output from a subtractor 31 to a Viterbi decoder.

That is, the reproduced signal after waveform equalization taken out from the subtractor 31 is supplied to the zero detector 65, and when the polarity is inverted here, the closer to 0 of the two sample points in the vicinity, Are detected as zero point information. The zero point information extracted from the zero detector 65 is input to the tap delay circuit 32. Thereby, according to the same provisional determination algorithm as in FIG.
A provisional determination result is obtained. FIG. 18 is a block diagram showing an eighth embodiment of the recording information reproducing apparatus according to the present invention. In the figure, the same components as those of FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the eighth embodiment shown in FIG. 18, the resampling DPLL 17, the resampling circuits 18 and 1
9 is used to reproduce recorded information. That is, the AGC / ATC circuits 14, 15, 16
Output digital read signals are directly sent to the delay adjuster 2.
Transversal filter 2 through 0, 23, 24
1, 25, and 26.

The reproduction signal from which the crosstalk extracted by the subtractor 31 has been removed and whose waveform has been equalized is supplied to the provisional discrimination circuit 33, while being supplied to the zero-cross detection / phase comparator 67, where it is supplied there. Zero crossing is detected, and the phase of the detected zero crossing point and the voltage controlled oscillator (VCO) 69
The phase of the bit clock is compared with the phase of the bit clock to generate a phase error signal. This phase error signal is applied as a control voltage to an analog or digital voltage controlled oscillator (VCO) 69 through a loop filter 68, and variably controls the output system clock frequency. VCO6
The output system clock of No. 9 has a frequency which is a natural number multiple of the bit clock and is applied to each block requiring the clock of the device.

FIG. 19 is a block diagram showing a ninth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 19, of the three adjacent tracks in the layer group formed on the optical disk, the read signal of the track Ti of the center layer to be reproduced at the center is an analog AGC signal.
The read signal of the adjacent track Ti in the lower adjacent layer which is input to the ATC circuit 71 is converted into an analog AGC / ATC circuit 7
2, the read signal of the adjacent track Ti of the upper adjacent layer is input to the analog AGC / ATC circuit 73, and the amplitude of each signal is controlled to be constant and the threshold value of the binary comparison is appropriately controlled. You.

The output read signal of the AGC / ATC circuit 71 is provided with an equalizer characteristic by a fixed equalizer (EQ) 41 at the next stage, and then supplied to the A / D converter 11 where it is sampled by a bit clock and digitalized. Is converted to Each output read signal of the AGC / ATC circuits 72 and 73 is supplied to A / D converters 12 and 13 and is sampled by a bit clock to be converted into a digital signal. The output digital signals of the A / D converters 11, 12, 13 are supplied to transversal filters 21, 25, 26 through delay adjusters 20, 23, 24.

The output analog signal of the fixed equalizer 41 is supplied to a phase comparator 74, loop filters 75 and 76.
And a system clock having a frequency which is a natural number multiple of the bit clock. On the other hand, when the polarity of the signal from the delay adjuster 20 is inverted, the zero detector 77 supplies, to the tap delay circuit 32, the one closer to 0 among the two nearby sample points as zero point information. This embodiment also has the same features as the above embodiments.

FIG. 20 is a block diagram showing a tenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
4, the same components as those in FIGS. 18 and 19 are denoted by the same reference numerals, and description thereof will be omitted. The tenth embodiment shown in FIG. 20 has a configuration in which ATC / AGC is performed only by an analog circuit and fixed threshold value determination is performed without using a digital VCO. In FIG. 20, the reproduced signal after the waveform equalization extracted from the subtractor 31 is output to a Viterbi decoder at the subsequent stage, while being supplied to a temporary discriminating circuit 45, where it is compared with a predetermined threshold and temporarily discriminated. I do.

FIG. 21 is a block diagram showing an eleventh embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In the eleventh embodiment shown in FIG. 21, an error signal output from the subtractor 34 is input to a first input terminal,
It is characterized in that an error selection circuit 81 is provided to a second input terminal, to which an output temporary determination value of the temporary determination circuit 33 is input.

As shown in FIG. 22, the error selection circuit 81 receives the error signal output from the third subtractor 34 at the first input terminal 811 and the provisional judgment circuit 33 at the second input terminal 812. Circuit 813, switch circuit 814, and 0 generator 815 to which the provisional determination value output from
It is composed of The tentative judgment value output from the tentative judgment circuit 33 should be set to the target value of PR equalization, and the deviation from the target value is output as an error signal. When the circuit 33 outputs 0 ^* corresponding to the zero cross point as a target value, it outputs "1".

In the case of RLL (2, X), the selection circuit 813 also outputs "+ b ^* " and "-b ^* " when the above-mentioned provisional judgment values are "+ b ^* " and "-b ^* "
1 ". This b is the value of b in PR (a, b, b, a), and * is RLL (1, X) or RLL.
It is assumed that the median value (a + b) of (2, X) is a value after offset so that it becomes 0. When the provisional determination value is + b ^* or -b ^* , the selection circuit 813 determines that the value is immediately before or immediately after the zero crossing point and “1”.
Is output. When the provisional determination value is other than the above value, the selection circuit 813 outputs “0”. RLL (1, X) when the ^{+ (b-a) *,} - (b-a) * it is determined that the value of the immediately before or after the zero-cross point when the "1"
Otherwise, "0" is output.

The switch circuit 814 receives as input the error signal input to the terminal a and the fixed value 0 from the 0 generator 815 input to the terminal b.
13 is supplied as a switching signal, and when the output signal of the selection circuit 813 is “1”, the effective component of the error signal input to the terminal a is selected.
Is "0", the value 0 inputted to the terminal b is selected.

The signal selected by the selection circuit 813 is supplied via an output terminal 816 to the multipliers LPFs 28 and 29 shown in FIG.
After being multiplied by the tap outputs from the pseudo-crosstalk component extraction transversal filters 25 and 26, and after removing the high frequency components, the tap coefficients (filter ) Are input to the transversal filters 25 and 26, respectively.

Next, regarding the operation of this embodiment, R
A description will be given using LL (2, X) as an example. Error selection circuit 8
In the first to tenth embodiments having no 1 in FIG. 23 (A) and FIG. 23 (B) when the waveform distortion of the reproduction signal is small, and when there is no crosstalk from the adjacent layer. (C), the output signal of the transversal filter 21 is correctly PR-equalized as shown by II in FIG. An error signal as shown in D) is extracted. This error signal represents the crosstalk component in FIG. 23B, that is, the error signal has a high correlation with the adjacent layer signal, and can generate a pseudo crosstalk component correctly.

In FIG. 23, circles indicate sample points when the target value is 0 (zero cross point), crosses indicate sample points when the target value is + b ^* or -b ^* , and white triangles indicate the target value. There (a + b) ^* or - (a + b) ^* (also FIGS. 24 25, described later) the sample points respectively when the.

However, as shown in the reproduction signal from the optical disk, when the distortion of the reproduction signal is large, and when there is no crosstalk from the adjacent layer, FIG.
When a crosstalk component as shown in FIG. 24B is included, the output signal of the transversal filter 21 is not correctly PR-equalized as indicated by IV in FIG. From the subtractor 34, as shown in FIG. 24D, an error signal in which the sample point indicated by a white triangle mark largely deviates from the target value is taken out.

That is, in the error signal output from the subtractor 34, inaccurate data appears at a sample point which is not near the zero crossing, deviates from the crosstalk component shown in FIG. Correlation has become low. Therefore, a pseudo crosstalk component cannot be correctly generated, and the effect of crosstalk cancellation is reduced by half.

Therefore, in this embodiment, the error selection circuit 81 having the configuration shown in FIG. 22 is provided on the input / output side of the subtractor 34 as shown in FIG. 21, and the target value 0, + b ^* or -b ^*
The error signal at the sample points other than the sample point near the zero cross at the time of is not output, and the error signal is invalidated by outputting the fixed value 0. Therefore, when the distortion is large and there is no crosstalk, FIG. 25A shows III (same as III in FIG. 24A), and FIG. 25C shows IV (FIG. 24C) when the crosstalk shown in FIG. 25B is included.
25), the error signal output from the error selection circuit 81 is the same as that shown in FIG. 25, even if a signal that is not correctly PR-equalized is output from the transversal filter 21. As schematically shown in (D), sample points that are not near the zero cross are replaced with a fixed value 0 as indicated by black triangles.

Therefore, in this embodiment, as shown in FIG. 25D, even at a sample position where the deviation from the target value greatly occurs when the error selection circuit 81 does not exist,
There is no deviation from the target value. As described above, in this embodiment, an uncertain error signal among error signals is invalidated, and only a sample point near a likely zero cross is used as an effective component of the error signal. Errors can be extracted, and as a result, the error rate can be improved, and a reproduction apparatus for a high-density recording medium such as a next-generation VDR (15 to 20 Gbytes or more) can be realized.

In this embodiment, the efficiency is reduced because a part of the error signal is invalidated as compared with the above-described embodiments, but the reduction in efficiency can be suppressed by increasing the loop gain.

FIG. 26 is a block diagram showing another embodiment of the error selection circuit 81. 22, the same components as those of FIG. 22 are denoted by the same reference numerals, and the description thereof will be omitted. The embodiment shown in FIG. 26 is characterized in that a selection circuit 818 having a different configuration from the selection circuit 813 in FIG. 22 is used. This selection circuit 818 is used only when the temporary determination circuit 33 outputs 0 ^* corresponding to the zero cross point as the target value.
To output 1 "and output other provisional judgment values, use"
Therefore, in this embodiment, the error selection circuit 81 outputs only the most probable sample point error signal, and invalidates the other sample point error signals.

FIG. 27 is a block diagram showing a twelfth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In the twelfth embodiment shown in FIG. 27, the error signal output from the subtractor 34 is input to the first input terminal,
The second input terminal is characterized in that an error selection circuit 83 to which zero point information is input from the resampling DPLL 17 through the delay adjustment circuit 22 and the tap delay circuit 32 is provided.

FIG. 28 shows the error selection circuit 83 and part of the circuit 32a of the tap delay circuit 32. Resampling D
The zero point information from the PLL 17 is
Information indicating the timing at which a sample point formed by resampling, which corresponds to a zero crossing point to be locked by the PLL 17 (for example, the point is “1”, and the rest is “0”), is shown in FIG. The OR circuit 32 is delayed by one sample clock by each of the two cascade-connected latch circuits 321 and 322.
3 and directly to the OR circuit 323. Therefore, three consecutive 0s are output from the OR circuit 323.
Only when at least one of the point information is “1”, “1” is output and applied to the switch circuit 831 as a switching signal.

The switch circuit 831 is connected to the OR circuit 32
3 is "1", the error signal output from the subtractor 34 is selected and output to the output terminal 833.
When the output signal of the R circuit 323 is “0”, the 0 generator 8
The fixed value “0” output from the P. 32 is selected and output to the output terminal 833.

Here, when at least one of the three 0-point information of three consecutive clock cycles input to the OR circuit 323 is "1", the digital reproduction signal input to the resampling DPLL 17 is a zero-cross sample. This indicates that the value is one of the three sample values, that is, the sample value immediately before and the sample value immediately after the sample value. Therefore, the switch circuit 831 selects only the error signal output from the subtractor 34 at this time. At other sample value timings, the fixed value 0 from the 0 generator 832 is selected.

As a result, similarly to the error selection circuit 81 having the configuration shown in FIG. 22, the error selection circuit 83 invalidates an uncertain error signal that is not near zero crossing and selectively outputs only a likely error signal. The same effect as when using 81 can be obtained.

Note that the error selection circuit 83 may be configured as shown in the block diagram of FIG. The error selection circuit 83 shown in FIG.
Is latched by a latch circuit 835 and indicates a timing at which a sample point formed by resampling, which corresponds to a zero crossing point to be locked, is supplied by a latch circuit 835 as a switching signal. As a result, the error signals supplied to the pseudo-crosstalk component extraction transversal filters 25 and 26 are selected and output only at the timing indicated by the 0-point information, and the error signals at other sample points are invalidated. Become As a result, only the most probable error signal can be selectively output.

FIG. 30 is a block diagram of a recording information reproducing apparatus according to a thirteenth embodiment of the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In the thirteenth embodiment shown in FIG. 30, a main signal (reproduced signal after waveform equalization) output from a second subtractor 31 is input to a first input terminal, and provisional determination is performed to a second input terminal. An error selection circuit 8 to which the provisional judgment value from the circuit 33 is input.
5 is provided.

As shown in FIG. 31, in the error selection circuit 85, the main signal output from the second subtractor 31 is input to a first input terminal 851, and the provisional judgment circuit 33 is input to a second input terminal 852. Circuit 853, switch circuit 854, and 0 generator 855 to which the provisional determination value output from
It is composed of The tentative judgment value output from the tentative judgment circuit 33 should be set to the target value of PR equalization, and a deviation from the target value is output as an error signal. "1" is output only when the circuit 33 outputs 0 ^* corresponding to the zero cross point as the target value, and "0" is output otherwise.

The switch circuit 854 receives as input the main signal inputted to the terminal a and the fixed value 0 inputted from the 0 generator 855 inputted to the terminal b.
The output signal of 53 is supplied as a switching signal, and when the output signal of the selection circuit 853 is “1”, an effective component of the main signal input to the terminal a is selected.
Is "0", the value 0 inputted to the terminal b is selected. The signal selected by the switch circuit 854 is output to the multiplier / LPF 28, 2 in FIG.
9 and multiplied by tap outputs from the pseudo crosstalk component extraction transversal filters 25 and 26, and after removing high frequency components, tap coefficients ( Filter coefficient)
And input to the transversal filters 25 and 26, respectively.

In this embodiment, at the sample point when the provisional discrimination value is “0” corresponding to the zero cross point, the error signal from the subtractor 34 and the main signal (sample data signal) output from the subtractor 31 , Ie, the reproduced signal after the waveform equalization), the error selection circuit 8
5 selects the main signal from the subtractor 31 in place of the error signal (that is, invalidates inaccurate data under certain conditions other than zero crossing) and outputs it as an error signal. It is. In this embodiment, the same effects as those of the eleventh and twelfth embodiments can be obtained.

FIG. 32 is a block diagram showing a fourteenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In the fourteenth embodiment shown in FIG. 32, the main signal output from the second subtractor 31 is input to the first input terminal, and the resampling DPLL 17 to the delay adjustment circuit 22 and the tap are input to the second input terminal. 0 through the delay circuit 32
It is characterized in that an error selection circuit 87 to which point information is input is provided.

As shown in FIG. 33, the error selection circuit 87 latches zero point information indicating the timing at which a sample point formed by resampling, which corresponds to a zero crossing point to be locked by the resampling DPLL 17, exists. And supplies it to the switch circuit 872 as a switching signal. The main signal output from the second subtractor 31 is input to a terminal a of the switch circuit 872, and a 0 generator 873 is input to a terminal b.
Is input as a fixed value 0.

Here, the timing indicated by the 0-point information output from the latch circuit 871 is a sample point corresponding to the zero cross point. At this sample point, the error signal from the subtractor 34 and the output from the subtractor 31 are output. Since it is the same as the main signal (sample data signal),
The error selection circuit 87 selects and outputs the main signal from the subtractor 31 instead of the error signal.

In this embodiment, the error selection circuit 87
Is the main signal from the subtractor 31 in accordance with a signal (output signal z3 of the latch circuit 871) indicating the timing at which the sample point formed by resampling exists, which corresponds to the zero cross point to be locked by the resampling DPLL 17. Since only the effective components are selected (that is, under certain conditions other than zero crossing, invalid data is invalidated) and output as an error signal, the eleventh embodiment is described. The same effects as those of the thirteenth embodiment can be obtained.

In the above embodiment, the error selection circuit 8
The output error signals of 1, 83, 85, 87 are multiplied by a multiplier LP
Although they are supplied to F28 and F29, they can of course be input to the INV 35 as error signals.

FIG. 34 is a block diagram showing a fifteenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof is omitted. In the embodiment shown in FIG. 34, a single laser beam is used to reproduce recorded information in a plurality of recording layers. For example, when reproducing the recorded information of each recording layer of a multi-layer disc having a structure in which the above-mentioned three recording layers are stacked with a spacer layer interposed therebetween, first, the laser spot is focused on the first recording layer and the laser beam is focused. Irradiation is performed for a predetermined number of rotations of the number of tracks, the reflected light of the recording layer is received, and photoelectric conversion is performed to obtain a first read signal.

Subsequently, a laser spot is focused on the second recording layer and irradiated for the predetermined number of tracks at the same position as the above for a rotation period, and the reflected light from the recording layer is received.
After obtaining the second read signal by photoelectric conversion, similarly, the laser spot is focused on the third recording layer and irradiated for the predetermined number of tracks at the same position as the above for a rotation period. The reflected light of the recording layer is received, photoelectrically converted and
To obtain a read signal. Hereinafter, the same operation as described above is repeated, and recording information signals for a predetermined number of tracks are sequentially read from each recording layer.

The first to third read signals for the predetermined number of tracks are sequentially supplied to the A / D converter 11 during the read period and A / D-converted, and then resampled DPLL 17 Digital data out of digital data and zero point information extracted from
91, and the zero point information is stored in the FIFO 92
And written at the timing of the bit clock generated by the resampling DPLL 17, respectively.
The signal input to the FIFO 91 is the FIFO 9
3 and 94, and information of another layer is written to the memory element (FIFO) at the above-described bit clock timing in a time sharing manner.

The signals written in the FIFOs 91, 92, 93 and 94 are read by a new clock corresponding to, for example, the average value of the frequency generated by the bit clock, and the delay adjusters 20, 22, 23, 24. Thereby, the transversal filter 2
The operations 1, 25 and 26 and the tap delay circuit 32 operate with the new clock.

Thereafter, the decoded signals for the predetermined number of tracks, which have been Viterbi decoded by the decoding circuit, are stored in the memory. The same operation as above is performed for each of the predetermined number of tracks for the read signal of each layer,
3 memories (or 3 memory areas)
The decoded signals of the recording information of one recording layer are separately stored. According to this embodiment, since signals of each layer can be read out in a time-division manner, it is possible to realize reproduction with a single laser beam, thereby reducing costs.

FIG. 35 is a block diagram showing a sixteenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. The embodiment shown in FIG. 35 is also an embodiment using a single laser beam similarly to the fifteenth embodiment, and the read signal read from a certain recording layer taken out from the resampling DPLL 17 is used. The digital data is directly transmitted to the transversal filter 26 without delay.
Is supplied to the transversal filter 25 through FIFOs 95 and 96 cascaded in two stages, and the output delay digital data of the FIFO 95 is supplied to the transversal filter 21.

Since the FIFOs 95 and 96 each have a predetermined delay time τ, the digital data input to the transversal filter 25 is delayed from the digital data input to the transversal filter 21 by the time τ. On the other hand, the digital data input to the transversal filter 26 is a signal advanced by time τ. The predetermined delay time τ is an arbitrary time.

According to this embodiment, since signals of each layer can be read out in a time-division manner, reproduction can be realized with a single laser beam, and the cost is reduced.
Thus, in the embodiment of FIG. 1, the first and second reproduced signals obtained separately from the layers above and below the main track by the three beams are converted by the transversal filters 25, 2
6, whereas in this embodiment, the FIF
By providing the necessary delay by O95 and 96,
A signal replaced with the first and second reproduced signals can be generated, and the second and third signals required in the embodiment of FIG.
And the resampling means including the resampling circuits 18 and 19 can be dispensed with, and as a result, crosstalk cancellation with a single beam is realized, and circuits other than the memory can be reduced.

FIG. 36 is a block diagram showing a seventeenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those in 8 are denoted by the same reference numerals, and description thereof will be omitted. As in the sixteenth embodiment, the seventeenth embodiment shown in FIG.
By giving a necessary delay to the output read signal of the ATC circuit 14, a signal replaced with the first and second crosstalk signals can be generated, and a signal which is required in the embodiment of FIG. 2nd and 3rd reading means and AG
The resampling means including the C / ATC circuits 15 and 16 can be eliminated, and as a result, crosstalk cancellation with a single beam is realized, and circuits other than the memory can be reduced.

FIG. 37 is a block diagram showing an eighteenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those in 9 are denoted by the same reference numerals, and description thereof will be omitted. In the eighteenth embodiment shown in FIG. 37, similarly to the sixteenth and seventeenth embodiments, the FIFOs 99 and 100 give necessary delays to the output read signal of the A / D converter 11 so that A signal replaced with the first and second crosstalk signals can be generated, and the second and third reading means and AGC / ATC circuits 72 and 73, A / D which are required in the embodiment of FIG. Converter 12
And 13 are unnecessary, as a result, crosstalk cancellation with a single beam is realized, and circuits other than the memory can be reduced.

FIG. 38 is a block diagram showing a nineteenth embodiment of the recorded information reproducing apparatus according to the present invention. In FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 38, a read signal A / D converted by the A / D converter 11 is stored in a FIFO 10 which is a memory element.
1, 102 and 103, and after being delayed for an arbitrary time, the read signal output from the FIFO 101 is supplied to the resampling DPLL 17,
The read signals output from the FIFOs 102 and 103 are supplied to resampling circuits 18 and 19, respectively.
According to this embodiment, since signals of each layer can be read out in a time-division manner, it is possible to realize reproduction with a single laser beam, thereby reducing costs.

The INV 35 is inserted for the purpose of providing negative feedback (negative feedback) when updating the coefficient of the transversal filter 21, and there are many other methods for achieving the purpose. The typical method is as follows. The tap output of the transversal filter 21 is inverted by INV.
The output of the multiplier / LPF 27 is inverted by INV. The polarity of the main signal inside the transversal filter 21 is changed to make the same. The polarity inversion is performed in any of the blocks in the lube.

Note that the present invention is not limited to the above embodiment, and for example, the delay adjuster 20 shown in FIG.
23 and 24 are AGC / ATC circuits 14, 15 and 16
May be provided on the input side, or may be omitted if the transversal filters 21, 25 and 26 have room.

In the case of multi-value equalization, tap coefficients of a transversal filter for generating a pseudo crosstalk component may be generated by selecting some of them. Further, the selected error signal may be shared with the error signal on the automatic equalizing circuit side. Further, in the above embodiment, the order of the light beam spots B0 to B2 may be changed to an order different from that in FIG.

Further, the above embodiment is not limited to a method of generating a plurality of beams. The simplest method is to prepare a plurality of laser beams and use them exclusively for each layer. But,
As shown in FIGS. 19 and 20 of JP-A-2000-149319, by using two divided bi-lenses for an optical pickup, it is possible to optically divide a laser beam and read information of each layer. Can be.

Further, if the error rate has a margin,
It is also possible to split the beam using the well-known two-beam method or three-beam method, and to use a tangential tilt to focus signals on each layer in order to read out signals from different adjacent layers. It is. It is clear that this can reduce the amount of laser light and reduce the cost.

In the above embodiment, the crosstalk cancellation from two layers vertically adjacent to each other using three beams has been described. The good is clear. In the case of two beams, it is clear that the corresponding pseudo crosstalk cancellation generation block is reduced, and the circuit size is significantly reduced. Also,
In the above embodiment, a method of canceling crosstalk from an adjacent layer has been described, but it is clear that crosstalk from a distant layer is also possible.

[0139]

As described above, according to the present invention,
When reproducing recorded information of an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked, pseudo crosstalk (interlayer crosstalk)
Can be adaptively canceled, a high-quality reproduction signal can be obtained, and the reproduction signal quality of the recording medium can be improved, so that the productivity of the recording medium can be improved.

Further, according to the present invention, the tentative discrimination means performs tentative discrimination (convergence target setting) on the premise of partial response equalization, and determines the difference between the tentative discrimination value and the reproduced signal after waveform equalization as an error. By supplying the signal to the first and second coefficient generation means and controlling the error signal to be 0, the operation of the apparatus is made to converge toward a clear temporary discrimination value (0, 2a + 2b, etc.). Since all points (sample values) are correlated with the crosstalk component as an error signal using the error from the provisional discrimination value for which the correlation is to be detected, quick convergence can be achieved and an error Reliable waveform equalization can be performed without converging in the direction.

Further, according to the present invention, since the partial response equalization is performed, a Viterbi decoder can be used in the subsequent stage, and accurate decoding can be performed. Further, according to the present invention, the resampling unit performs the resampling operation of the reproduced signal from the adjacent layer by using the internal division ratio and the bit clock at the time of the resampling operation generated by the resampling operation phase locked loop circuit. Therefore, it is possible to cope with a frequency shift.

Further, according to the present invention, since a resampling operation phase locked loop circuit can be used, integration into an integrated circuit is easy, the number of parts can be reduced, and the reproduced signal is suitable for oversampling. It is suitable to be applied to a reproducing apparatus for a recording medium such as an optical disk having an attenuation characteristic. Further, there is no influence of a change with time or parameter variation peculiar to analog.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a schematic explanatory diagram of an example of a positional relationship between a beam spot and a layer when three beams are used.

FIG. 3 is a state transition diagram of an example of partial response equalization.

FIG. 4 is a diagram when crosstalk cancellation is not performed.
FIG. 5 is a diagram showing an example of a simulation waveform of each section of FIG.

FIG. 5 is a diagram when crosstalk cancellation is not performed.
FIG. 9 is a diagram illustrating a change in a tap coefficient of a transversal filter in a pseudo-crosstalk signal generation block in FIG.

FIG. 6 is a diagram when crosstalk cancellation is not performed.
7 shows an eye pattern of an input signal of a middle provisional determination circuit.

FIG. 7 is a diagram when crosstalk cancellation is not performed.
Error flags of each part in the middle.

8 is a diagram illustrating an example of a simulation waveform of each unit in FIG. 1 when crosstalk cancellation is performed.

9 is a diagram illustrating a change in tap coefficients of a transversal filter in a pseudo crosstalk signal generation block in FIG. 1 when crosstalk cancellation is performed.

FIG. 10 when crosstalk cancellation is performed.
7 shows an eye pattern of an input signal of a middle provisional determination circuit.

FIG. 11 is a diagram when crosstalk cancellation is performed.
Error flags of each part in the middle.

FIG. 12 is a block diagram of a second embodiment of the present invention.

FIG. 13 is a block diagram of a third embodiment of the present invention.

FIG. 14 is a block diagram of a fourth embodiment of the present invention.

FIG. 15 is a block diagram of a fifth embodiment of the present invention.

FIG. 16 is a block diagram of a sixth embodiment of the present invention.

FIG. 17 is a block diagram of a seventh embodiment of the present invention.

FIG. 18 is a block diagram of an eighth embodiment of the present invention.

FIG. 19 is a block diagram of a ninth embodiment of the present invention.

FIG. 20 is a block diagram of a tenth embodiment of the present invention.

FIG. 21 is a block diagram of an eleventh embodiment of the present invention.

FIG. 22 is a block diagram of one embodiment of an error selection circuit in FIG. 21;

FIG. 23 is an explanatory diagram of sample points and extracted error components when PR equalization is correctly performed without an error selection circuit.

FIG. 24 is an explanatory diagram of sample points and extracted error components when PR equalization is not performed correctly when there is no error selection circuit.

FIG. 25 is an explanatory diagram of sample points and extracted error components when PR equalization is not performed correctly when there is an error selection circuit.

FIG. 26 is a block diagram of another embodiment of the error selection circuit in FIG. 21;

FIG. 27 is a block diagram of a twelfth embodiment of the present invention.

FIG. 28 is a block diagram of an embodiment of an error selection circuit in FIG. 27;

FIG. 29 is a block diagram of another embodiment of the error selection circuit in FIG. 27;

FIG. 30 is a block diagram of a thirteenth embodiment of the present invention.

FIG. 31 is a block diagram of an embodiment of an error selection circuit in FIG. 30;

FIG. 32 is a block diagram according to a fourteenth embodiment of the present invention.

FIG. 33 is a block diagram of one embodiment of an error selection circuit in FIG. 32;

FIG. 34 is a block diagram according to a fifteenth embodiment of the present invention.

FIG. 35 is a block diagram according to a sixteenth embodiment of the present invention.

FIG. 36 is a block diagram of a seventeenth embodiment of the present invention.

FIG. 37 is a block diagram of an eighteenth embodiment of the present invention.

FIG. 38 is a block diagram according to a nineteenth embodiment of the present invention.

FIG. 39 is a cross-sectional view of a conventional two-layer optical disc.

FIG. 40 is a diagram showing how a light beam emitted from an optical pickup in a conventional two-layer optical disc reflects each layer of the two-layer optical disc and reaches the optical pickup again.

FIG. 41 shows how a light beam emitted from an optical pickup is focused on one reflection layer of a two-layer optical disc and defocused on the other reflection layer in a conventional two-layer optical disc. FIG.

FIG. 42 is a diagram showing the relationship between the thickness of a spacer layer and interlayer crosstalk in a conventional two-layer optical disc.

FIG. 43 is a diagram showing the relationship between the total thickness of the light-transmitting substrate and the spacer layer and the optical aberration (spherical aberration) in the conventional two-layer optical disc.

[Explanation of symbols]

11-13 A / D converter 14-16 AGC / ATC circuit 17 Resampling DPLL circuit 18, 19 Resampling circuit 20, 22, 23, 24 Delay adjuster 21 Transformer for waveform equalization of reproduced signal of layer to be reproduced Versal filter 25, 26 Transversal filter for pseudo-crosstalk signal generation 27-29 Multiplier / LPF 30, 31, 34 Subtractor 32 Tap delay circuit 32a Partial circuit of tap delay circuit 33 Temporary decision circuit 45 Temporary decision with fixed threshold Circuits 65, 77 Zero detectors 81, 83, 85, 87 Error selection circuits 91-107 FIFOs 321, 322, 835, 871 Latch circuits 323 OR circuits 811, 851 First input terminals 812, 852 Second input terminals 813 , 815, 853 selection circuit 814, 831, 854, 87 Switching circuit 815,832,855,873 0 generator 816,833,856,874 output terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11B 20/18 572 G11B 20/18 572F 576 576Z

Claims (10)

[Claims] 1. A first read for obtaining a first read signal by reading recorded information of an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked. Means for reading recording information of a recording layer existing at least above and below one of the arbitrary recording layers of the multilayer recording medium to be read by the first reading means, and
A second reading means for obtaining a read signal of the following; a first filtering means for equalizing the waveform of the first read signal based on a first filter coefficient; A second filtering unit that performs filtering based on a filter coefficient and outputs a pseudo crosstalk signal; and receives at least a reproduced signal after waveform equalization as an input, and presupposes partial response equalization. Tentative judgment means for calculating a tentative judgment value to be a target value; first subtraction means for outputting a difference value between the tentative judgment value and the reproduced signal after waveform equalization as an error signal; and the first subtraction means A first coefficient generation unit that variably controls the first filter coefficient based on the error signal output from the first filter unit so that the error signal is minimized; Based on the error signal, the second coefficient generating means for variably controlling the second filter coefficients, the second from the output signal of said first filtering means
Second subtraction means for subtracting the pseudo crosstalk signal output from the filtering means, and outputting a reproduction signal after waveform equalization of the recording information of any one recording layer to be reproduced. A recorded information reproducing apparatus characterized by the following. 2. A zero-crossing discriminating means for discriminating whether or not the first read signal, the output signal of the first filtering means or the zero-crossing point of the reproduced signal after waveform equalization, outputs zero-point information. The provisional determination means receives the 0 point information and the first read signal or the output signal of the first filtering means or the reproduced signal after waveform equalization as inputs, and performs partial response equalization. 2. The recording information according to claim 1, wherein a provisional determination value of the reproduced signal after waveform equalization is determined based on a state transition determined by a type and a type of a run-length limiting code of the first read signal. Playback device. 3. A first read for obtaining a first read signal by reading recorded information of an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked. Means for reading recording information of a recording layer existing at least above and below one of the arbitrary recording layers of the multilayer recording medium to be read by the first reading means, and
A / D conversion means for separately converting the first and second read signals into digital signals and outputting first and second digital reproduction signals, Digital data sampled at a desired bit rate from the first digital reproduced signal is generated by resampling operation, a bit clock is generated, and a zero-cross resampling point of the first digital reproduced signal is detected. A first resampling operation phase locked loop circuit for outputting zero point information, and a first transformer for waveform equalizing output digital data of the resampling operation phase locked loop circuit based on a first filter coefficient. A versal filter, delaying the 0 point information by a predetermined time at each bit sampling timing A delay mode, a PR mode signal indicating a type of the partial response equalization, an RLL mode signal indicating a type of a run-length limiting code of the first read signal, and a plurality of the zero point information from the delay circuit. And a reproduced signal after waveform equalization as inputs, and based on the state transition determined by the PR mode signal and the RLL mode signal and the pattern of the plurality of point information, a provisional determination value of the reproduced signal after waveform equalization is obtained. Tentative judgment means for calculating, first subtraction means for outputting a difference value between the tentative judgment value and the reproduced signal after waveform equalization as an error signal, First coefficient generating means for variably controlling the first filter coefficient so that the error signal is minimized, and the second digital signal from the A / D conversion means. Resampling means for performing a resampling operation on the reproduction signal based on an output bit clock of the phase locked loop circuit and outputting a sampling signal; and filtering the sampling signal based on a second filter coefficient. A second transversal filter for outputting a pseudo crosstalk signal corresponding to a read signal of at least one recording layer above and below any one recording layer to be reproduced; and the first subtraction means. A second coefficient generating means for variably controlling the second filter coefficient based on the error signal outputted from the first transversal filter so that the error signal is minimized; and Second subtraction means for subtracting the crosstalk signal and outputting the reproduced signal after the waveform equalization. Recorded information reproducing apparatus characterized by. 4. The tentative determination means calculates a tentative determination value of the waveform-equalized reproduction signal by using at least one of the PR mode signal and the RLL mode signal as a fixed value.
Subtraction means for determining the temporary discrimination value from the temporary discrimination means and the second
4. The reproducing apparatus according to claim 3, wherein a difference value from the reproduced signal after waveform equalization output from the subtraction means is output as an error signal. 5. A zero detector which receives the reproduced signal after waveform equalization output from the second subtracting means, detects a zero crossing point of the reproduced signal after waveform equalization, and outputs the same as zero point information. 4. The recording information reproducing apparatus according to claim 3, wherein the delay circuit delays the zero point information output from the zero detector. 6. A phase synchronization, wherein a reproduced signal after the waveform equalization of the second subtracting means is inputted, and a system clock having a frequency which is a natural number multiple of the bit clock is generated based on the reproduced signal after the waveform equalization. A loop circuit is provided, and the resampling operation phase locked loop circuit and the resampling means are deleted, and the first and second digital reproduction signals from the A / D conversion means are converted into the first and second transversal filters. 4. The recording information reproducing apparatus according to claim 3, wherein the delay circuit delays zero point information indicating a zero cross point output from a phase comparator in the phase locked loop circuit. 7. A phase-locked loop circuit for generating a system clock having a frequency which is a natural number multiple of the bit clock based on the first read signal from the first read unit, and a signal from the A / D conversion unit. A zero detector for detecting a zero cross point of the extracted first digital reproduction signal and outputting zero point information is provided. The resampling operation phase locked loop circuit and the resampling means are deleted to remove the A / D signal. First and second conversion means
5. The digital reproduction signal according to any one of claims 3 to 4, wherein said digital signal is separately supplied to said first and second transversal filters, and said delay circuit delays zero point information from said zero detector. Recorded information reproducing device. 8. The first and second filtering means equalizes the waveforms of the input first and second read signals into partial response characteristics PR (a, b, b, a). 3. The recorded information reproducing apparatus according to claim 1, wherein: 9. A method according to claim 1, wherein one or all of the first read signal or the second read signal, an output signal of the digital operation phase locked loop circuit and an output signal of the resampling operation phase locked loop circuit are stored in a memory medium. Recorded in
The recording information reproducing apparatus according to any one of claims 1 to 8, wherein the signal is synchronized by reading it later to perform a desired crosstalk canceling operation. 10. A first read for obtaining a first read signal by reading recorded information of an arbitrary recording layer to be reproduced, which is recorded on a multilayer recording medium having a structure in which a plurality of recording layers are stacked. Means for reading recording information of a recording layer existing at least above and below one of the arbitrary recording layers of the multilayer recording medium to be read by the first reading means, and
A second reading means for obtaining a read signal of the following; a first filtering means for filtering the first read signal based on a first filter coefficient; and a second filter coefficient for the second read signal. And a second filtering unit that outputs a pseudo-crosstalk signal by filtering based on the input signal, receives the output reproduction signal of the first filtering unit as an input, compares the reproduction signal with a predetermined fixed threshold value, Detecting means for detecting a sample value; coefficient generating means for variably controlling the first and second filter coefficients so that the zero-cross sample value detected by the detecting means becomes 0; The output signal of the filtering means is subtracted from the pseudo crosstalk signal output from the second filtering means, Recorded information reproducing apparatus characterized by having a subtraction means for outputting a waveform equalization after the reproduction signal of the recorded information should do any one of the recording layer.