JP3428499B2 - Digital signal reproduction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing device, and more particularly to a digital signal reproducing device for reproducing a recorded digital signal on a recording medium such as an optical disk.

[0002]

2. Description of the Related Art FIG. 25 shows a block diagram of an example of a conventional digital signal reproducing apparatus. In the figure, a digital signal recorded on a recording medium 81 such as an optical disk, which is obtained by digitally modulating an information signal, is reproduced by reproducing means (not shown) and pre-amplified by a pre-amplifier 82.
A direct current component (DC component) is blocked by the ATC circuit 83, and is sampled by an A / D converter (not shown).
Automatic gain control (AG
C) is done. The PLL circuit 85 generates digital data obtained by resampling the input signal input from the AGC circuit 84 at a desired bit rate, and supplies the digital data to an adaptive equalizer (crosstalk canceller (CTC)) 86.

The adaptive equalizer 86 gives, for example, a partial response (PR) characteristic to an input signal,
Performs waveform equalization. The output signal of the adaptive equalizer 86 is supplied to the decoding circuit 87, where it is subjected to, for example, known Viterbi decoding, and then supplied to the ECC circuit 88, and the error correction code in the decoded data string is used to output the error correction code. The code error of the generated element is corrected, and the decoded data with reduced error is output.

Further, conventionally, crosstalk removal is performed based on signals reproduced by different beams from three adjacent tracks of an optical disc on which high density recording is performed, and reproduction with a good S / N ratio is performed from the center track. Although various digital signal reproducing devices by the three-beam method for obtaining a signal have been proposed, it is possible to remove the crosstalk of the reproduced signal without recording a preamble signal for removing the crosstalk in advance. There is known a digital signal reproducing apparatus using a three-beam method with improved recording capacity (Japanese Patent Laid-Open No. 9-320200).

In this conventional digital signal reproducing apparatus,
A first read signal reproduced by one beam from any one track of the optical disk, and two second read signals reproduced by two separate beams from two tracks adjacent to both sides of the one track. , Sampled and converted into a first and second sample value series, a cross coefficient component is obtained from the second sample value series by a variable coefficient filter, and the cross talk component is obtained from the first sample value series. The subtraction circuit subtracts the value, and the zero-cross sample extraction means extracts the zero-cross sample value from the output sample value series of the subtraction circuit, and the filter coefficient calculation means changes the above-mentioned variable so that the zero-cross sample value converges to zero. While updating the filter coefficient of the coefficient filter, the determination means determines from the output sample value series of the subtraction circuit. It is configured to make a determination of the raw signal.

[0006]

However, the above-mentioned FIG.
In the conventional digital signal reproducing apparatus shown in FIG. 5, when the recording medium 81 is an optical disk, the reproduced signal has a discrepancy between the maximum amplitude center level 92 and the minimum inversion interval center level 93, as indicated by 91 in FIG. Therefore, in the case of such a reproduced signal waveform, the ATC circuit 83 is configured to simply control the central level of the maximum amplitude to 0 level. ,
The 0 level cannot be set at the center of the signal level of the minimum inversion interval which should be the original 0 level.

Further, in the conventional digital signal reproducing apparatus by the three-beam method described in the above publication, the LMS adaptive algorithm is used to update the filter coefficient of the variable coefficient filter so that the error signal becomes zero. The above-mentioned error signal is only the zero-cross sample value extracted from the output sample value series of the subtraction circuit, and there is a problem that convergence is slow and misjudgment is large. Moreover, since partial response equalization is not performed, Viterbi decoding cannot be performed, and S / S read from an optical disc that tends to be recorded at higher density
There is also a problem that there is a high possibility that data restoration of a reproduction signal having a low N will be mistaken.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital signal reproducing device which can reproduce recorded information on a recording medium in a fast and reliable manner.

Another object of the present invention is to provide a digital signal reproducing apparatus capable of accurately reproducing recorded information on a recording medium recorded at high density by using partial response equalization.

Further, another object of the present invention is to surely converge to a correct 0 level position and correct an error rate even for a reproduced digital signal having a vertical asymmetry without erroneously checking the original 0 level. An object is to provide a digital signal reproducing apparatus which can be improved.

[0011]

In order to achieve the above object, a first aspect of the invention is to read from any one record information recording track to be reproduced in a record information recording track group on a recording medium. Reading means for obtaining one reproduction signal and second and third reproduction signals separately read from two recording information tracks adjacent to both sides of one recording information recording track to be reproduced; A to D conversion means for individually converting the first to third reproduced signals into digital signals and outputting the first to third digital reproduced signals, and resampling calculation of the first digital reproduced signals at a desired bit rate. Resampler that generates the resampling data, generates the bit clock, and detects the zero-cross of the resampling data to output the zero point information. And calculating the phase-locked loop circuit, first
To a third transversal filter, a delay circuit,
The temporary discriminating means, the first to third coefficient generating means, the resampling means, the first and second subtraction circuits, and the error calculator are included.

Here, the above-mentioned first transversal filter equalizes the waveform of the resampling data output from the resampling calculation phase locked loop circuit based on the first filter coefficient. The delay circuit described above outputs zero point information at least three consecutive zero points.
Temporary determination means described above, the PR mode signal representing a type of the partial response equalization when performing partial response equalization for the first digital reproduced signal, the kind of run length limited code of the first digital reproduced signal , An RLL mode signal indicating a plurality of zero point information from the delay circuit, and a waveform equalized reproduction signal as inputs, and
A state transition determined by the R mode signal and the RLL mode signal,
A tentative discriminant value of the waveform equalized signal is output based on a plurality of zero point information patterns.

Further, the first coefficient generating means is configured to reduce the first reduction coefficient.
From the reproduction signal after waveform equalization from the arithmetic circuit
Based on the error signal obtained by subtracting the provisional discrimination value , the first filter coefficient is variably controlled to minimize the error signal.
The resampling means separately performs resampling operation on the second and third digital reproduced signals from the A / D converting means based on the output bit clock of the resampling operation phase locked loop circuit, and then first and second 2 sampling signals are output. The second and third transversal filters separately filter the first and second sampling signals based on the second and third filter coefficients, respectively, and record any one record information to be reproduced. The first and second pseudo crosstalk signals corresponding to the read signals of the two recording information tracks adjacent to both sides of the track are separately output. Second and third coefficient generating means, based on the error signal, variably controls the second and third filter coefficients separately. The first subtraction circuit subtracts the first and second pseudo crosstalk signals from the output signal of the first transversal filter, and outputs a reproduced signal after waveform equalization.

The error calculator indicates the above-mentioned error signal and the timing at which there is a sample point formed by resampling, which corresponds to a zero-cross point to which the resampling operation phase locked loop circuit should be locked. The zero point information from the delay circuit is received as an input, and the effective component of the input error signal is integrated and output according to the timing. Further, the second subtraction circuit is A /
The difference signal between the first digital reproduction signal from the D conversion means and the output signal of the error calculator is input to the resampling calculation phase locked loop circuit.

According to the first aspect of the present invention, the provisional discrimination means performs provisional discrimination (convergence target setting) on the premise of partial response equalization, and the provisional discrimination value and the waveform-equalized reproduction signal extracted from the subtraction circuit. 1st difference value as error signal
To the third filter coefficient generating means to control the error signal to be 0 so that the operation of the apparatus converges toward a clear value and the error calculator outputs the output error of the temporary determining means. The signal or the output signal of the first subtraction circuit is extracted at the timing of the sampling point corresponding to the zero-cross point at which the resampling operation phase locked loop circuit should lock, and integrated, and the integrated output is used as the DC offset information for the second subtraction. Since the signal is input to the circuit, the DC component of the input signal of the resampling calculation phase locked loop circuit can be largely removed.

Further, in order to achieve the above-mentioned object, the second and third inventions include the error calculator in the first invention ,
Output signal of first subtraction circuit or output provisional discrimination of provisional discrimination means
The value and the zero point information from the delay circuit, which indicates the timing at which the sample point formed by resampling exists, which corresponds to the zero crossing point to which the resampling operation phase locked loop circuit should lock, are received as input and input. The effective component of the error signal is integrated and output according to the timing, and the difference signal between the reproduced signal after the output waveform equalization of the first subtraction circuit and the output signal of the error calculator is output to the decoding circuit. It has a configuration including a second subtraction circuit.

According to the present invention, the error calculator outputs the output error signal of the temporary discriminating means or the output signal of the first subtraction circuit at the timing of the sample point corresponding to the zero cross point to which the resampling calculation phase locked loop circuit should be locked. Since it is extracted and integrated, and the integrated output is input to the second subtraction circuit as DC offset information, the DC component of the input signal of the resampling calculation phase locked loop circuit can be largely removed.

Here, in any of the first, second and third inventions, instead of the second subtraction circuit, the difference between the output signal of the resampling operation phase locked loop circuit and the output signal of the error operation unit A third subtraction circuit may be provided to input the signal to the first transversal filter, and
The error calculator is the output error signal of the temporary discrimination means or the first error signal.
Timing at which a sample point formed by resampling the effective component of the input error signal from the output signal of the subtraction circuit and the provisional discrimination value of the provisional discrimination means is obtained from the provisional discrimination value is present May be integrated and output according to Furthermore, the zero point information input to the error calculator is not only the sample points formed by resampling, which correspond to the zero cross points to which the resampling operation phase locked loop circuit should lock, but also the samples before and after that sample point. The error calculator may be a signal indicating the timing at which a point exists, and may integrate and output the effective component of the input error signal according to the timing of the sample point and the sample points before and after the sample point.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a digital signal reproducing apparatus according to the present invention.
In this embodiment, a known three-beam method is used in which three beam spots are separately formed on three adjacent recording tracks of an optical disc as an example of a recording medium.
That is, as shown in FIG. 2, an arbitrary track Ti of the optical disc in which one track is formed per rotation.
When the recorded information signal is reproduced from the track Ti, the reproduction-only light beam spot B0 is formed on the track Ti, and the track Ti
A beam spot B1 is formed on the inner track Ti-1 and a beam spot B2 is formed on the outer track Ti + 1 of the tracks Ti-1 and Ti + 1 which are adjacent to each other on both sides.

These three beam spots B0, B1,
B2 keeps the state in which the beam spot B1 is located at the rear position (or the front position) and the beam spot B2 is located at the front position (or the rear position) in the rotation direction of the optical disc with the central beam spot B0 as the center. Tracking is well known. The light reflected by these three beam spots B0, B1, and B2 is converted into a read signal through separate well-known optical systems. These read signals are run length limited codes (digital signals) photoelectrically converted and amplified by the PD head amplifier.

Of the above read signals, the read signal of the central track Ti to be reproduced is supplied to the A / D converter 10 of FIG. 1, and the read signal of the adjacent inner track Ti-1 on the inner peripheral side is shown in FIG. 1 is supplied to the A / D converter 11 of FIG. 1, and the read signal of the adjacent track Ti + 1 on the outer peripheral side is the A / D converter 1 of FIG.
2 is supplied. The A / D converters 10, 11, and 12 sample the input read signal by the master clock, convert it into a digital signal, and supply it to the AGC / ATC circuits 13, 14, 15 at the next stage, where the amplitude is changed. Amplitude control (AGC) in which the constant is controlled, and automatic threshold control (AT) in which the threshold of the binary comparator is appropriately controlled by direct current (DC).
C) Allow.

The output signal of the AGC / ATC circuit 13 is resampled by a subtracting circuit 16 which will be described later.
7 is supplied. The resampling DPLL 17 is a digital PLL (phase-locked loop) circuit in which a loop is completed in its own block, and resampling data generated by performing resampling (thinning interpolation) on an input signal at a desired bit rate. (That is, the resampling data phases 0 ° and 180 °) are supplied to the transversal filter 21 through the delay adjuster 20. Further, the resampling DPLL 17 detects the zero-cross of the resampling data of phase 0 °, and supplies the 0-point information obtained thereby to the tap delay circuit 32 described later through the delay adjuster 22. Furthermore, phase 180
The resampling data of ° is supplied to the transversal filter 21 through the delay adjuster 20.

Further, the resampling DPLL 17 generates a bit clock BCLK for bit sampling, and also generates a parameter T_ratio indicating a ratio to be internally divided for resampling operation, which is sent to resampling circuits 18 and 19. Supply each,
Here, the digital signal from the AGC / ATC circuits 14 and 15 is resampled by the bit clock BCLK at a rate indicated by the parameter T_ratio. The bit clock BCLK is a toothless clock (Punctur).
ed Clock). The 0-point information indicates the point at which the bit sampling data crosses the zero level in bit clock units. Further, the resampling DPLL 17 locks the resampling timing, that is, the frequency so that it becomes 0 based on the value of the resampling data of phase 180 ° corresponding to the zero cross point indicated by the 0 point information.

The signals extracted from the resampling circuits 18 and 19 are supplied to the transversal filters 25 and 26 through the delay adjusters 23 and 24.
The transversal filter 21 and the transversal filters 25 and 26 described above receive filter coefficients (tap coefficients) from multipliers / low-pass filters (LPFs) 27, 28 and 29, respectively, and perform filtering processing of characteristics corresponding to them. Perform on the input signal.

The transversal filter 21 performs waveform equalization processing based on the tap coefficient (filter coefficient) from the multiplier / LPF 27, and intersymbol interference with signals before and after the read signal from the desired track to be reproduced. Reduce the effect of. The read signal after the output waveform equalization of the transversal filter 21 is supplied to the tentative determination circuit 33 through the subtraction circuits 30 and 31 described later, where the tap delay circuit 32 is provided.
Delay signal, a PR mode signal indicating the type of partial response (PR), and an RLL mode signal indicating the run length limited code length (minimum inversion interval or maximum inversion interval) of the signal recorded on the optical disc are input. Then, based on these, the temporary discrimination result is output.

This temporary discrimination result and the input signal of the temporary discrimination circuit 33 (the output signal of the subtraction circuit 31) are subtracted in the subtraction circuit 34, and the difference value is inverted as an error signal in the inverter 35 and then multiplied. It is supplied to the device / LPF 27, where it is multiplied by the tap output of the transversal filter 21 to detect the correlation, and integrated by the LPF.
The output integrated value of the multiplier / LPF 27 is input to the transversal filter 21 as a filter coefficient (tap coefficient) of the transversal filter 21 that makes the value of the error signal 0.

The above-mentioned transversal filter 21, multiplier / LPF 27, temporary discrimination circuit 33, tap delay circuit 3
2, the feedback loop including the subtraction circuit 34 and the inverter 35 is based on the well-known LMS algorithm, but the tentative discrimination circuit 33 is a circuit proposed by the present inventor and tentatively based on partial response equalization. Determine (set convergence target).

Here, to further explain the partial response (PR) characteristic, for example, PR (a, b, b,
When the characteristic of a) is added to a solitary wave and equalized, the equalized waveform is (0, a, a + b, 2a, 2b, a + 2b, 2a + 2) in the case of (1,7) RLL, as is well known.
Takes 7 values of b. When these 7 values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are constrained by the past signal, and this (1,7)
It is known that the state transition diagram as shown in FIG. 3 can be expressed by utilizing the fact that the input signal "1" does not last twice or more by the RLL.

In FIG. 3, S0 to S5 indicate states determined by the immediately preceding output value. From this state transition diagram, for example, when the input value is a + 2b, the output value becomes 1 and the state transitions to state S3 when the input value is a + 2b, and when the input value is 2b, the output value becomes 1 and the state transitions to state S4. However, it turns out that the other input values are not input, and if they are input, it is an error.

Here, the value Z of the 0 point information is "
1 "indicates a zero cross point, which is represented by a value" a + b "in the state transition diagram of PR (a, b, b, a) shown in FIG.
This occurs in the process of transitioning to → S2 or state S4 → S5. In this case, the states S2, S3, and S4 in the right half of FIG. 3 have positive values (a + b = 0 when normalized to a + b = 0).
+ 2b, 2a + 2b, or 2b), and the states S5, S0, and S1 in the left half are negative values (a + b = 0).
In the case of normalization to 0, any of 0, a, and 2a) is traced, so that it is possible to determine whether the route is a positive route or a negative route by referring to the value before or after the zero cross point.

Moreover, if the interval from one zero cross point to the next zero cross point is known, that is, from the state S2 to the state S5, or from the state S5 to the state S.
If the number of transitions up to 2 is known, the route is determined, and the possible values become clear for each sample point.

In the above state transition diagram, when the value is other than "a + b", that is, when it is not the zero cross point, the value Z of the 0 point information is "0". From this state transition diagram, two zero cross points (Z = 1) are not consecutively taken out, and in the case of RLL (1, X), at least one "1" is provided between adjacent Z = 1. 0 ”exists (when the value Z of the 0 point information changes from 1 → 0 → 1; that is, when the state S1 → S2 → S4 → S5 or the state S4 → S5 → S1 → S2 transits). In addition,
In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1.

In the actual signal, due to the influence of noise and the like,
It is quite possible that the detection of the zero-cross point itself will be erroneous, but in the case of feedback control, if the probability of being able to make a correct decision exceeds the probability of erroneous, it should converge in the correct direction, and it is also sufficient. Because of the integration process,
Single-shot noise is considered to be practically no problem.

Focusing on the above points, the provisional discrimination circuit 33 discriminates the value Z of the 0-point information input from the tap delay circuit 32 in each cycle of the bit clock, and the five values in five consecutive clock cycles are identified. Whether it is all "0", only the first value among the above five values is "1", only the last value among the above five values is "1",
It is determined whether the first and last values of the above five values are "1" and the remaining three values are "0".

In these patterns, when the value Z of the 0-point information of interest is "0", the value Z of the 0-point information on both sides is "0". At this time, the signal waveform is Since it is the case of sticking to the positive side or the negative side, a large value P1 is calculated when either of these patterns is satisfied.

If none of the above patterns,
Value 0 of 5 0 point information in 5 consecutive clock cycles
Is "01010", and in the case of this pattern, it is determined based on the RLL mode signal whether the partial response equalization of RLL (1, X) is performed. Since this pattern may occur only at RLL (1, X), a small value P2 is calculated at RLL (1, X).

If the value Z of the five 0-point information in 5 consecutive clock cycles is not "01010", then those 5
The value Z of one 0 point information is "01001", "100"
It is determined whether the pattern is any one of 10 "," 00010 ", and" 01000 ". For these four patterns, the value Z of the 0 point information of interest is" 0 ".
Then, one of the values Z of the 0-point information adjacent on both sides is “1”. When it is one of the four patterns, or "01010", and R
When it is determined that the LL mode is not (1, X), P
An intermediate level value P3 of 1 and P2 is calculated.

When the values P1, P2 or P3 are calculated, when the waveform equalized signal at the current time input to the temporary discrimination circuit 33 is 0 or more, the final temporary determination level Q is set to P1 at that time.
When the value is P2 or P3, and the value is negative, the final provisional determination level Q is inverted in polarity from the value of P1, P2, or P3 at that time. If none of the above, the final provisional determination level Q is set to 0.

As described above, the provisional discrimination circuit 33 outputs the PR mode signal indicating the type of partial response equalization, the RLL mode signal indicating the type of the run length limited code of the reproduction signal, and the plurality of tap delay circuits 32. The zero point information and the output signal after the waveform equalization of the subtraction circuit 31 are received as inputs, and based on the state transition determined by the PR mode signal and the RLL mode signal and a plurality of patterns of the zero point information, the waveform equalization signal is received. The tentative discrimination level Q of is calculated.
This tentative judgment level Q is used as a target value in the subtraction circuit 34 of FIG.
And the difference from the reproduced signal after waveform equalization, which is the actual signal, is taken to be an error signal (error information). The error information extracted from the subtraction circuit 34 is the inverter (I
NV) 35, while being supplied to the error calculator 36. Further, the tap delay circuit 32 outputs the resampling DPLL 17 to the resampling DPL 17.
The zero point information indicating the timing at which the sample point formed by resampling, which corresponds to the zero cross point to which L17 should be locked, is extracted as described above, and this 0 point information is obtained by the error calculator 3
6 is supplied.

The error calculator 36 extracts only the necessary DC offset information from the error information based on the 0-point information, and the integrated result is supplied to the subtraction circuit 16 as a DC shift component. FIG. 4 shows the first part of the error calculator 36.
3 is a block diagram of the embodiment of FIG. In the figure, the switch circuit 40 includes error information input to the terminal 40a,
When the fixed zero point information from the zero generator 41 input to the terminal 40b is received as an input and the zero point information from the tap delay circuit 32 is "1" (at this time, as described above, the zero cross point (Indicating the timing at which the sample points formed by resampling exist), the effective component of the error information input to the terminal 40a is selected, and the digital low frequency band composed of the adder 43 and the latch circuit 44 is selected. Filter (LPF) 4
It is supplied to 2, and integrated here to be output as a DC shift component (DC offset component). The switch circuit 4
When the 0 point information is "0", the fixed 0 point information from the 0 generator 41 input to the terminal 40b is selected and input to the LPF 42. At this time, LPF4
The output of 2 is held at the previous value.

As described above, in this embodiment, as shown in FIG. 5, resampling D of the output error information (crosstalk cancel error signal) of the subtraction circuit 34 is used.
Only the error information corresponding to the zero cross sample indicated by the white circle of the reproduced digital signal I input to the PLL 17 is set to L.
The PF 42 integrates it, and since it can be regarded as a DC shift component, this is input to the subtraction circuit 16 and subtracted from the output signal of the AGC / ATC circuit 13. As a result, the subtraction circuit 1
From 6, the DC component can be removed from the output signal of the AGC / ATC circuit 13.

On the other hand, the signals extracted from the resampling circuits 18 and 19 of FIG.
A fixed delay is given by 3 and 24, and the time is roughly adjusted with pseudo crosstalk, which will be described later, and is input to the transversal filters 25 and 26. The transversal filters 25 and 26 have tap coefficients (filter coefficients).
The error signals output from the subtraction circuit 34 are input to the multipliers / LPFs 28 and 29 for supplying the signal, and the error signals output from the subtractor circuit 34 are multiplied by the tap outputs of the transversal filters 25 and 26 to extract the correlation between adjacent track signals. The correlation value is integrated by the LPF and the transversal filters 25 and 26 are integrated.
To enter.

In this way, the tap coefficients (filter coefficients) of the transversal filters 25 and 26 are updated according to the correlation value of the adjacent track signals, and the inner and outer circumference sides of the transversal filters 25 and 26 are updated. A pseudo crosstalk signal corresponding to the read signal from each track is extracted. These transversal filters 25,
The output pseudo crosstalk signal of 26 is subtracted by the subtraction circuits 30 and 31 from the reproduction signal from the track to be reproduced after waveform equalization from the transversal filter 21, respectively. As a result, the subtraction circuit 31 cancels out crosstalk in the reproduction signal of the track to be reproduced after the waveform equalization from the transversal filter 21, and removes S /
It is output as a good N reproduced signal. Since this embodiment is a feedback process, stable operation can be realized.

In this embodiment, an inter-symbol interference removing block of a reproduction signal of a track to be reproduced, which includes a transversal filter 21, and a transversal filter 25.
In each of the pseudo crosstalk generation blocks based on the reproduction signals from the adjacent tracks including the control signals 26 and 26, each tap coefficient (filter coefficient) is controlled so that the same error signal is set to 0, so that a control collision occurs. do not do. Further, the resampling DPLL 17 is independently sandwiched between the AGC / ATC circuit 13 and the inter-symbol interference elimination block of the reproduction signal of the track to be reproduced including the transversal filter 21, and is looped in its own block. Since it has been completed, reliable convergence can be expected.

The reason why the delay adjusters 23 and 24 are arranged after the resampling devices 18 and 19 is that the number of delay flip-flops can be reduced, which is functionally equivalent to the resampling devices 18 and 19. It may be arranged in the preceding stage. Further, the subtraction circuit 16 uses the resampling DPLL.
You may make it connect and connect between the signal paths from 17 to the transversal filter 21.

FIG. 6 is a block diagram of the second embodiment of the error calculator 36. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. This error calculator is characterized in that the switch circuit 40 is switched based on the result of selecting the output signal of the provisional discrimination circuit 33 by the selection circuit 46 instead of the 0-point information from the tap delay circuit 32. That is, the target value output from the temporary discrimination circuit 33 should be set to the target value for PR equalization,
Since the deviation from the target value is output as an error, when the provisional discrimination circuit 33 outputs "0" corresponding to the zero cross point as the target value, the selection circuit 46 indicates "".
1 "is output, and" 0 "is output when the output signal of the temporary discrimination circuit 33 is other than" 0 ".

As a result, the switch circuit 40 is connected to the terminal 40.
When the error information input to a and the fixed 0 point information from the 0 generator 41 input to the terminal 40b are received as inputs, and the output signal of the selection circuit 46 is "1" (at this time, Terminal 40a only) indicating the timing at which the sample points formed by sampling exist
LPF4 by selecting the effective component of the error information input to
It is supplied to 2, and integrated here to be output as a DC shift component (DC offset component).

FIG. 7 is a block diagram of the third embodiment of the error calculator 36. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. The error calculator 36 is characterized in that the switch circuit 40 is switched based on the logical sum operation result of three adjacent 0-point information from the tap delay circuit 32. That is, when at least any one of the three 0-point information in three consecutive clock cycles is "1", they are zero cross of the reproduced digital signal II inputted to the resampling DPLL 17 and its zero crossing as shown in FIG. When the LPF 42 integrates only the error information corresponding to the zero-cross sample indicated by the white circle and the samples indicated by the white triangles before and after the zero-cross sample indicated by the white circle, it is DC.
Since it can be regarded as a deviation component, this is output.

In FIG. 7, the 0 point information from the tap delay circuit 32 is the two latch circuits 4 connected in cascade.
The signals are delayed by 1 sample clock each by 8 and 49 and are supplied to the OR circuit 50, and are also directly supplied to the OR circuit 50. Therefore, from the OR circuit 50, at least one of the three consecutive 0-point information is "
Only when it is "1", "1" is output, and the switch circuit 40 selects the effective component of the error information input to the terminal 40a and supplies it to the LPF 42, where it is integrated and the DC shift component (DC offset component) is selected. ) Is output.

FIG. 9 is a block diagram of the fourth embodiment of the error calculator 36. In the figure, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. This error calculator operates the switch circuit 40 not by the 0 point information,
Further, it is characterized in that the output signal of the temporary discrimination circuit 33 is switched based on the result selected by the selection circuit 51 by an algorithm different from that of the selection circuit 46 of FIG.

That is, in the selection circuit 51, the input output signal of the provisional discrimination circuit 33 is a in the state transition diagram of FIG.
When normalized to + b = 0, 0 and the level corresponding to the minimum inversion interval, that is, when the PR mode is (1, X) → (ba) or-(ba) (2, X) When → b or -b, the value is judged to be the value at or near the zero cross point and "1" is output, otherwise "1" is output.
As a result, when the output signal of the selection circuit 51 is "1", the switch circuit 40 selects the effective component of the error information input to the terminal 40a and selects the LPF 42.
To a DC offset component (DC offset component).

Next, a second embodiment of the present invention will be described. FIG. 10 shows a block diagram of a second embodiment of a digital signal reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the embodiment shown in FIG.
Although the C offset information is fed back to the input side of the transversal filter 21, the embodiment is shown in FIG. 10. The embodiment of FIG. 10 is feedforward control that takes the difference from the signal on the output side of the transversal filter 21. It is a thing.

That is, the error information output from the subtraction circuit 34 and the 0-point information output from the tap delay circuit 32 are supplied to the error calculator 55. Like the error calculator 36, the error calculator 55 has the configuration shown in FIG. 4, FIG. 6, FIG. 7 or FIG. 9, and extracts only the necessary DC offset information from the error information based on the 0 point information, The result of integration is the DC shift component,
It is supplied to the subtraction circuit 56. The subtraction circuit 56 is the subtraction circuit 3
By subtracting the output DC offset information of the error calculator 55 from the output signal of 1, it is possible to obtain a signal in which a DC error component such as a DC shift or a DC fluctuation is significantly reduced.

Next, the data waveform of the first embodiment will be described. FIGS. 11 to 14 actually resample a signal having a DC offset and fluctuation by a DPLL.
17 is an eye pattern of data when the error calculator 36 does not perform crosstalk cancellation, the vertical axis is the level, the horizontal axis is the time axis, and the arrow attached to the vertical axis is the original Indicates 0 level.

FIG. 11 shows that the output signal of the resampling DPLL 17 is sliced at the absolute 0 level of the circuit.
The eye pattern of the resampling data of the phase 0 ° for discriminating between 1 ”and“ 0 ”, and FIG. 12 is the output signal of the resampling DPLL 17 which is the resampling data of the phase 180 ° for decoding by the Viterbi decoding circuit in the subsequent stage. FIG. 13 is an eye pattern of resampling data having a phase of 0 ° for slicing the output signal of the subtraction circuit 31 at the absolute 0 level of the circuit to determine “1” and “0”. Reference numeral 14 denotes an eye pattern of the resampling data having a phase of 180 ° for decoding the output signal of the subtraction circuit 31 by the Viterbi decoding circuit in the subsequent stage.

As can be seen from FIGS. 11 to 14, the levels of these data are clearly offset, and the DC fluctuation existing in the input signal is also output as it is.
As a result, in the case of the data of FIGS. 11 and 13, if the slice discrimination is simply performed at the 0 level (+ polarity is 1 and −polarity is 0), a large amount of data will cause a discrimination error.
On the contrary, it can be seen from FIGS. 12 and 14 that even if the adaptive equalization processing is performed using the transversal filter 21 or the like, it is not possible to converge to the optimum state (coefficient). In such a state, no matter how much the Viterbi decoder is used in the subsequent stage, the error cannot be eliminated (in particular, Viterbi decoding is weak in DC shift).

On the other hand, when the signal having the DC offset and the fluctuation is actually input to the resampling DPLL 17 and the crosstalk cancellation is performed by the error calculator 36, the eye pattern of the data is as shown in FIG.
It is shown in FIG. FIG. 15 shows the resampling DPLL.
The output signal of 17 is sliced at the absolute 0 level of the circuit and the eye pattern of the resampling data of phase 0 ° for distinguishing "1" from "0" is decoded by the Viterbi decoding circuit in the subsequent stage. 17 shows the eye pattern of the output signal of the resampling DPLL 17, which is the resampling data of phase 180 ° for
Slice at the absolute 0 level of the circuit and "1" and "0"
18 shows the eye pattern of the re-sampling data of the phase 0 ° for discriminating the difference, and FIG. 18 shows the eye pattern of the re-sampling data of the phase 180 ° for decoding the output signal of the subtraction circuit 31 by the Viterbi decoding circuit in the subsequent stage. .

As can be seen from FIGS. 15 to 18, these data have DC fluctuations and DC fluctuations as compared with FIGS. 11 to 14.
Both the shift and the shift are significantly reduced, and therefore, FIGS.
As can be seen from the above, it can be seen that a correct value can be determined even with a simple 0-level slice. Also, FIGS.
It can be seen that the sample corresponding to the zero-cross point from is controlled correctly to 0 level. In this state,
The Viterbi decoding circuit in the latter stage can exhibit a high error rate reduction effect that is closer to the theoretical value.

Next, another embodiment of the present invention will be described. FIG. 19 shows a block diagram of the third embodiment of the digital signal reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In this embodiment, the error calculator 61 receives as input the 0-point information from the tap delay circuit 32 and the output signal of the subtraction circuit 31, and outputs only the necessary DC offset information from the output signal of the subtraction circuit 31 to 0. The signal extracted based on the point information and integrated is supplied to the subtraction circuit 16 as a DC shift component. The subtraction circuit 16 subtracts the output DC offset information of the error calculator 61 from the output signal of the subtraction circuit 31 to obtain D such as DC deviation or DC fluctuation.
It is possible to obtain a signal in which the C error component is significantly reduced.

FIG. 20 shows a block diagram of the fourth embodiment of the digital signal reproducing apparatus according to the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the error calculator 63 receives the tentative discrimination value of the tentative discrimination circuit 33 and the output error information of the subtraction circuit 34 as inputs, and outputs only the necessary DC offset information from the output error information of the subtraction circuit 34. A sampling point formed by resampling obtained by the selection circuit 46 or 51 based on the tentative discriminant value is extracted in accordance with the timing, and the result of integration processing is supplied to the subtraction circuit 16 as a DC shift component. To do. Subtraction circuit 16
Can subtract the output DC offset information of the error calculator 61 from the output signal of the subtraction circuit 31 to obtain a signal in which DC error components such as DC shift and DC fluctuation are significantly reduced.

FIG. 21 is a block diagram of the fifth embodiment of the digital signal reproducing apparatus according to the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the error calculator 65 receives the tentative discrimination value of the tentative discrimination circuit 33 and the output signal of the subtraction circuit 31 as inputs, and outputs the required DC signal from the output signal of the subtraction circuit 31.
Only the offset information is extracted according to the timing at which the sample points formed by the resampling obtained by the selection circuit 46 or 51 based on the tentative discriminant value exist, and the result of the integration processing is taken as the DC shift component, It is supplied to the subtraction circuit 16.

22, FIG. 23, and FIG. 24 are block diagrams of the sixth, seventh, and eighth embodiments of the digital signal reproducing apparatus according to the present invention, respectively. In each drawing, the same components as those in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted. In these embodiments, the error calculators 67, 69, 71 receive the output signal of the subtraction circuit 31 or the output error signal of the subtraction circuit 34 at one input terminal, and the 0 point information from the tap delay circuit 32 or the provisional determination is performed. The tentative discrimination value of the circuit 33 is received by the other input terminal, and only the necessary DC offset information is
Based on the 0-point information or the tentative discrimination value of the tentative discrimination circuit 33, the sampling point formed by resampling is extracted in accordance with the timing when the sampling point exists, and the result of integration processing is used as a DC shift component in the subtraction circuit 56. Supply. The subtraction circuit 56 subtracts the output DC offset information of the error calculators 67, 69, 71 from the output signal of the subtraction circuit 31, and can obtain a signal in which DC error components such as DC shift and DC fluctuation are significantly reduced.

The present invention is not limited to the above embodiment, and for example, the delay adjuster 20 shown in FIG.
23 and 24 are AGC / ATC circuits 13, 14 and 15
Of the transversal filters 21, 25 and 26 may be omitted if there is a margin.

Further, in the above-described embodiment, two system circuits are provided for exclusively generating the pseudo crosstalk signals for the two-beam read signals for the two tracks adjacent to both sides of the track to be reproduced. If the device has a known tilt sensor that detects the irradiation angle of the beam with respect to the optical disc, based on the output signal of the tilt sensor, reading of two beams for two tracks adjacent to both sides of the track to be reproduced is performed. By providing a switch circuit that selects only one of the signals having a large crosstalk component, the pseudo crosstalk signal generation circuit system can be made only one system.

[0065]

As described above, according to the present invention,
The error calculator outputs the output error signal of the provisional discrimination means or the output signal of the first subtraction circuit at the sampling point timing corresponding to the zero-cross point to be locked by the resampling calculation phase locked loop circuit, and integrates it. By inputting the output as the DC offset information to the second subtraction circuit, the resampling calculation phase locked loop circuit and the adaptive equalizer at the subsequent stage do not have the function of controlling the DC component, and the DC component should be controlled automatically. In the threshold control (AFC) device, the response is slow and the accuracy is lacking, so that the D signal of the input signal, the output signal of the resampling operation phase locked loop circuit or the output signal of the adaptive equalizer remains.
The C component can be largely removed, and therefore, in the Viterbi decoding circuit in the subsequent stage, a high error rate reduction effect close to the theoretical value can be exhibited.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a device of the present invention.

FIG. 2 is a schematic explanatory view of an example of a positional relationship between a beam spot and a track by the 3-beam method.

FIG. 3 is a state transition diagram of an example of partial response equalization.

FIG. 4 is a block diagram of a first embodiment of an error calculator.

5 is an operation explanatory diagram of FIG. 4;

FIG. 6 is a block diagram of a second embodiment of an error calculator.

FIG. 7 is a block diagram of a third embodiment of an error calculator.

FIG. 8 is an operation explanatory diagram of FIG. 7;

FIG. 9 is a block diagram of a fourth embodiment of an error calculator.

FIG. 10 is a block diagram of a second embodiment of the device of the present invention.

11 is a diagram showing an example of an eye pattern of an output signal of the resampling DPLL circuit in FIG. 1 when crosstalk cancellation is not performed.

FIG. 12 is a diagram showing another example of the eye pattern of the output signal of the resampling DPLL circuit in FIG. 1 when crosstalk cancellation is not performed.

FIG. 13 is a diagram showing an example of an eye pattern of the output signal of FIG. 1 when crosstalk cancellation is not performed.

FIG. 14 is a diagram showing another example of the eye pattern of the output signal of FIG. 1 when crosstalk cancellation is not performed.

15 is a diagram showing an example of an eye pattern of an output signal of the resampling DPLL circuit in FIG. 1 when an error calculator is used.

16 is a diagram showing another example of the eye pattern of the output signal of the resampling DPLL circuit in FIG. 1 when an error calculator is used.

17 is a diagram showing an example of an eye pattern of the output signal of FIG. 1 when an error calculator is used.

FIG. 18 is a diagram showing another example of the eye pattern of the output signal of FIG. 1 when an error calculator is used.

FIG. 19 is a block diagram of a third embodiment of the device of the present invention.

FIG. 20 is a block diagram of a fourth embodiment of the device of the present invention.

FIG. 21 is a block diagram of a fifth embodiment of the device of the present invention.

FIG. 22 is a block diagram of a sixth embodiment of the device of the present invention.

FIG. 23 is a block diagram of a seventh embodiment of the device of the present invention.

FIG. 24 is a block diagram of an eighth embodiment of the device of the present invention.

FIG. 25 is a block diagram of an example of a general digital signal reproducing device.

FIG. 26 is a diagram showing an example of a vertically and asymmetrically reproduced signal waveform.

[Explanation of symbols]

10-12 A / D converter 13-15 AGC / ATC circuit 17 resampling DPLL circuit 18, 19 resampling circuit 20, 22, 23, 24 delay adjuster 21 waveform equalization transformer for waveform of reproduced signal of track to be reproduced Versal filters 25, 26 Pseudo-crosstalk signal generation transversal filters 27-29 Multiplier / LPF 30, 31, 34, 56 Subtraction circuit 32 Tap delay circuit 33 Temporary discrimination circuit 35 Polarity inversion circuits 36, 55, 61, 63, 65, 67, 69, 71 Error calculator 40 Switch circuit 42 Digital low-pass filter (LPF) 46, 51 Selection circuit 48, 49 Latch circuit 50 OR circuit

Continuation of the front page (56) Reference JP-A-9-97476 (JP, A) JP-A-9-320200 (JP, A) JP-A-9-306105 (JP, A) JP-A-7-262694 (JP , A) JP 5-227042 (JP, A) JP 2000-123487 (JP, A) JP 11-273256 (JP, A) JP 2001-110146 (JP, A) JP 2001-6287 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 G11B 7/005

Claims (8)

(57) [Claims] 1. A recording information recording track group on a recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit,The above The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters,The above From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
ShiWaveA first subtraction circuit for outputting a reproduction signal after shape equalization;Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The error signal And the resampling calculation phase synchronization rule
The loop circuit, which corresponds to the zero-cross point that should be locked,
There are sample points formed by sampling
The zero point from the delay circuit indicating the timing
Input information and the error message
The effective component of the signal is integrated and output according to the timing.
Error calculator, The first digital reproduction signal from the A / D conversion means.
Signal and the difference signal between the output signal of the error calculator and
The second sampling input to the phase locked loop circuit
A digital signal reconstructing circuit having a subtraction circuit.
Raw equipment. 2.Recording information on the recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
First converted into a digital signal To the third digital reproduction signal
A / D conversion means for outputting,The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and Resump
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters, From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
From the temporary discrimination means Error signal obtained by subtracting the provisional discrimination value
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When,The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The waveform equalized reproduced signal from the first subtraction circuit,
The resampling operation phase locked loop circuit locks
By resampling, which corresponds to the power zero-cross point
Indicates when the sample points formed are present
Input the zero point information from the delay circuit
The effective component of the input error signal
An error calculator that integrates and outputs according to the timing, The first digital reproduction signal from the A / D conversion means.
Signal and the difference signal between the output signal of the error calculator and
The second sampling input to the phase locked loop circuit
Subtraction circuit and Is characterized by having Digital signal re
Raw equipment. 3.Recording information on the recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
Separate for playback signal Resampling operation phase
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means,The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters, From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, Input the provisional discrimination value of the provisional discrimination means and the error signal.
Received as a force, and the effective component of the input error signal is received.
Error calculator for integrating and outputting according to the timing
When, The first digital reproduction signal from the A / D conversion means.
Signal and the difference signal between the output signal of the error calculator and
The second sampling input to the phase locked loop circuit
Subtraction circuit and Is characterized by having Digital signal re
Raw equipment. 4.Recording information on the recording medium
Of which should be regenerated From the record information recording track of your choice
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters, From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digit Tal reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means toFrom the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The provisional discrimination value of the provisional discrimination means and the first subtraction circuit
Of the waveform equalized reproduction signal of
The effective component of the error signal is
Error calculator that integrates and outputs The first digital reproduction signal from the A / D conversion means.
Signal and the difference signal between the output signal of the error calculator and
The second sampling input to the phase locked loop circuit
Subtraction circuit andIs characterized by havingDigital signal re
Raw equipment. 5. A recording information recording track group on a recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit,The above The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters,The above From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
ShiWaveA first subtraction circuit for outputting a reproduction signal after shape equalization;Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The error signal And the resampling calculation phase synchronization rule
The loop circuit, which corresponds to the zero-cross point that should be locked,
There are sample points formed by sampling
The zero point from the delay circuit indicating the timing
Input information and the error message
The effective component of the signal is integrated and output according to the timing.
Error calculator, Of the first subtraction circuitThe aboveThe reproduced signal after waveform equalization and the
Error signal to the decoding circuit
And a second subtraction circuit
Signal playback device. 6.Recording information on the recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Second and third transversers for output Filter,From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The waveform equalized reproduction signal from the first subtraction circuit When,
The resampling operation phase locked loop circuit locks
By resampling, which corresponds to the power zero-cross point
Indicates when the sample points formed are present
Input the zero point information from the delay circuit
The effective component of the input error signal
An error calculator that integrates and outputs according to the timing, The waveform equalized reproduction signal of the first subtraction circuit and the error signal
Error signal to the decoding circuit
Second subtraction circuitIs characterized by havingDigital
Signal playback device. 7.Recording information on the recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
First converted into a digital signal To the third digital reproduction signal
A / D conversion means for outputting,The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters, From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
From the temporary discrimination means Error signal obtained by subtracting the provisional discrimination value
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When,The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, Input the provisional discrimination value of the provisional discrimination means and the error signal.
Received as a force, and the effective component of the input error signal is received.
Error calculator for integrating and outputting according to the timing
When, The waveform equalized reproduction signal of the first subtraction circuit and the error signal
Error signal to the decoding circuit
Second subtraction circuit Is characterized by having Digital
Signal playback device. 8. Recording information on the recording medium
From any one of the recorded information recording tracks to be played
The read first reproduction signal and the arbitrary one to be reproduced.
Recording information of two recording information adjacent to both sides of the recording track
Second and second read separately from each of the
Reading means for obtaining a reproduction signal of 3; The first to third reproduction signals are separately digitized.
Converted into a digital signal to convert the first to third digital reproduction signals
A / D conversion means for outputting, The first digital reproduction signal at a desired bit rate
Generate resampling data by performing resampling operation
Generate a bit clock, and
Zero point information is detected by detecting the zero cross of ring data
And a resampling calculation phase locked loop circuit that outputs Output from the resampling operation phase locked loop circuit
Based on the first filter coefficient
A first transversal filter that equalizes the waveform by The zero point information is added to each bit sampling timing.
Delay to output at least 3 consecutive packets
Circuit, The second and third digital signals from the A / D conversion means
The resampling operation phase is separately applied to the playback signal.
Resample based on the output bit clock of the synchronous loop circuit
Pulling operation is performed to obtain the first and second sampling signals.
Output resampling means, The first and second sampling signals are separately separated into a second and a second signal.
And filtering separately based on the third filter coefficient
And any one of the recording information recording tracks to be reproduced.
On the read signals of the two recording information tracks adjacent to both sides of
Separate the corresponding first and second pseudo crosstalk signals
Output second and third transversal filters, From the output signal of the first transversal filter
Subtract the first and second pseudo crosstalk signals respectively
And a first subtraction circuit for outputting a reproduction signal after waveform equalization, Partial response to the first digital reproduction signal
Seed for partial response equalization when performing Ponce equalization
PR mode signal indicating a class and the first digital reproduction
RLL mode indicating the type of run length limited code of the signal
Signal and a plurality of said zero point information from said delay circuit.
And a reproduction signal after the waveform equalization from the first subtraction circuit.
Signal and the PR mode signal and the RL
The state transition determined by the L-mode signal and the plurality of zero points
Outputs the provisional discriminant value calculated based on the information pattern
Tentative discrimination means to From the reproduced signal after the waveform equalization from the first subtraction circuit
An error signal obtained by subtracting the temporary discrimination value from the temporary discrimination means.
Signal of the first filter coefficient to the error signal
Coefficient generating means for variably controlling so that
When, The second and third filters based on the error signal
Second and third coefficient generating means for separately variably controlling coefficients
When, The temporary discriminant value of the temporary discriminator and the first subtraction circuit
Of the waveform equalized reproduction signal of
The effective component of the error signal is
Error calculator that integrates and outputs The waveform equalized reproduction signal of the first subtraction circuit and the error signal
Error signal to the decoding circuit
Second subtraction circuit A digital camera characterized by having
Signal playback device.