JP3395716B2 - Digital signal reproduction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus, and more particularly to a digital signal reproducing apparatus having a waveform equalizing circuit for waveform equalizing a run length limited code reproduced from a recording medium such as an optical disk.

[0002]

2. Description of the Related Art FIG. 24 shows a block diagram of an example of a conventional digital signal reproducing apparatus. In the figure, a digital signal recorded on a recording medium 81 such as an optical disk, which is obtained by digitally modulating an information signal, is reproduced by reproducing means (not shown) and pre-amplified by a pre-amplifier 82.
A direct current component (DC component) is blocked by the ATC circuit 83, and is sampled by an A / D converter (not shown).
Automatic gain control (AG
C) is done. The PLL circuit 85 generates digital data obtained by resampling the input signal input from the AGC circuit 84 at a desired bit rate, and supplies the digital data to an adaptive equalizer (crosstalk canceller (CTC)) 86.

The adaptive equalizer 86 gives, for example, a partial response (PR) characteristic to an input signal,
Performs waveform equalization. The output signal of the adaptive equalizer 86 is supplied to the decoding circuit 87, where it is subjected to, for example, known Viterbi decoding, and then supplied to the ECC circuit 88, and the error correction code in the decoded data string is used to output the error correction code. The code error of the generated element is corrected, and the decoded data with reduced error is output.

Further, conventionally, in a reproducing apparatus which reproduces the run-length limited code from a recording medium such as an optical disc in which the run-length limited code is recorded at high density, in order to remove the waveform distortion of the reproduced signal, a partial response ( Hereinafter, one using a waveform equalizing circuit having an equalizing characteristic (hereinafter also referred to as PR) is known (Japanese Patent Laid-Open No. 10-106).
161). In this digital signal reproducing apparatus, the run-length limited code reproduced by the recording / reproducing system from the optical disc is supplied to the transversal filter, and based on the tap coefficient input from the tap coefficient determiner in the parameter setter. , PR equalize. Bits corresponding to the binary data memory for parameter setting are recorded in advance on the optical disc. The tap coefficient determiner obtains a tap coefficient from the reproduced waveform corresponding to this bit and the equalized target waveform so that the reproduced waveform matches the equalized target waveform, and inputs the tap coefficient to the transversal filter. The ML decoder decodes the equalized reproduced waveform extracted from the transversal filter into binary data and outputs it.

Conventionally, an optical disc for performing maximum likelihood detection having a sign inversion interval as a constraint condition after equalizing a reproduced signal by a run length limited code whose minimum code inversion interval is limited to a constant of 2 or more. In the signal reproduction method, the ternary equalization is performed only on the amplitude except the point corresponding to the data string having the minimum code inversion interval among the points immediately before and after the code inversion position and the amplitude at the code inversion position. There is also known a reproducing device (Japanese Patent Laid-Open No. 7-192270).

[0006]

However, the above-mentioned FIG.
In the conventional digital signal reproducing apparatus shown in FIG. 4, when the recording medium 81 is an optical disk, the reproduced signal has a discrepancy between the maximum amplitude center level 92 and the minimum inversion interval center level 93, as indicated by 91 in FIG. Therefore, in the case of such a reproduced signal waveform, the ATC circuit 83 is configured to simply control the central level of the maximum amplitude to 0 level. ,
The 0 level cannot be set at the center of the signal level of the minimum inversion interval which should be the original 0 level.

Further, in the conventional digital signal reproducing apparatus described in Japanese Patent Laid-Open No. 10-106161, it is premised that bits corresponding to the binary data memory for parameter setting are recorded in advance on the optical disc. Cage,
If it is not known whether the recording signal of the optical disk corresponds to the binary data stored in the parameter setting binary data memory, it is not possible to adaptively equalize the waveform. Therefore, it is necessary to reproduce the data of a known pattern corresponding to the binary data stored in the binary data memory for parameter setting, and determine the tap coefficient of the transversal filter so that the waveform is normally equalized. I won't.
Therefore, it is not possible to deal with the case where the reproduction signal is input with a reproduction characteristic different from that when the tap coefficient is determined.

Further, in the conventional digital signal reproducing apparatus disclosed in Japanese Patent Laid-Open No. 7-192270, since the target value of the PR equalization performed by the reproducing apparatus is multi-valued, fine threshold comparison is performed by the error rate judging device 9. This is necessary, and there is a problem that the determination becomes difficult due to noise and distortion. Therefore,
Equipment to which multiple kinds of signals are input (eg CD, DVD
In such a reproducing device), the run length and the PR characteristic to be equalized differ depending on the property of the signal to be reproduced, so that the control for adjusting the threshold becomes complicated, and the convergence time for stabilizing the waveform equalization takes a long time. there is a possibility.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a digital signal reproducing device which can reproduce recorded information on a recording medium in a fast and reliable manner.

Another object of the present invention is to provide a digital signal reproducing apparatus capable of accurately reproducing recorded information on a recording medium recorded at high density by using partial response equalization.

[0011]

In order to achieve the above object, a first invention uses a transversal filter to reproduce a run length limited code in a reproduced signal and reproduce the run length limited code. In a digital signal reproducing apparatus for performing partial response equalization and then decoding, an A / D converter for converting the run-length limited code into a digital reproduced signal and a digital reproduced signal output from the A / D converter are desired. Resampling operation Phase synchronization that generates resampling data at the bit rate, generates resampling data and outputs it to the transversal filter, and also generates a bit clock, detects the zero cross of resampling data, and outputs 0 point information. The loop clock and bit sampling from the resampling operation phase locked loop circuit. 0 point information retrieved in synchronism with the click, which is constituted from a delay circuit for outputting three at least contiguous, and provisional determination circuit, and the coefficient generating means, and an error calculator, a subtraction circuit.

The tentative discrimination circuit described above includes a PR mode signal indicating the type of partial response equalization and an RLL mode signal indicating the type of run length limited code in the reproduced signal.
A plurality of 0-point information from the delay circuit and the waveform equalized reproduction signal output from the transversal filter are received as inputs, the state transition determined by the PR mode signal and the RLL mode signal, and a pattern of a plurality of 0-point information. Based on the above, the temporary discriminant value of the waveform equalized signal is calculated, and the difference value between the temporary discriminant value and the waveform equalized reproduced signal is output as an error signal. The coefficient generation means variably controls the tap coefficient of the transversal filter based on the output error signal of the provisional discrimination circuit so that the error signal is minimized. Further, the above error calculator is equivalent to the zero cross point to which the resampling calculation phase locked loop circuit should be locked when the error signal output from the provisional discrimination circuit or the output signal of the transversal filter is input to the first input terminal. To do
The 0 point information from the delay circuit indicating the timing at which the sample point formed by resampling exists or the temporary discrimination value of the waveform equalized signal from the temporary discrimination circuit is input to the second input terminal, and the second input Only the effective component of the input signal of the first input terminal corresponding to the timing of the input signal of the terminal is integrated, and the integrated value is output as DC offset information. Further, the subtraction circuit described above generates a difference signal between the digital reproduction signal output from the A / D converter and the DC offset information output from the error calculator, and the resampling calculation phase locked loop circuit and the transversal circuit. Type in one of the filters.

According to the first aspect of the present invention, the error calculator outputs the delay circuit from the delay circuit indicating the timing at which the sampling point formed by resampling, which corresponds to the zero-cross point at which the resampling operation phase locked loop circuit should be locked, exists. 0 point information or only the effective component of the error signal output from the temporary discrimination circuit or the output signal of the transversal filter corresponding to the timing of the temporary discrimination value of the waveform equalization signal from the temporary discrimination circuit is integrated, and the integration is performed. Since the value is subtracted from the digital reproduction signal output from the A / D converter as DC offset information,
By this subtraction, the DC offset component in the digital reproduction signal output from the A / D converter can be removed and input to one of the resampling calculation phase locked loop circuit and the transversal filter.

In addition, in order to achieve the above-mentioned object, the second invention, instead of the subtraction circuit in the first invention, outputs the waveform equalized reproduction signal output from the transversal filter and the error calculator. The subtraction circuit that generates a difference signal from the DC offset information and outputs it to the decoding circuit is used. According to the present invention, the error calculator provides 0-point information from the delay circuit indicating the timing at which the sampling point formed by resampling, which corresponds to the zero-cross point to which the resampling operation phase-locked loop circuit should be locked, or tentative determination. Depending on the timing of the temporary discriminant value of the waveform equalized signal from the circuit,
Only the error signal output from the provisional discrimination circuit or the effective component of the output signal of the transversal filter is integrated, and the integrated value is subtracted from the reproduced signal after waveform equalization output from the transversal filter as DC offset information. Therefore, by this subtraction, the DC offset component in the reproduced signal after waveform equalization output from the transversal filter can be removed and output to the decoding circuit.

According to a third aspect of the present invention, the error calculator of the first or second aspect of the present invention uses the error signal or the effective component of the output signal of the transversal filter according to the timing of the sample point and the sample points before and after the sample point. Is integrated, and the integrated value is output as DC offset information.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a digital signal reproducing apparatus according to the present invention.
In the figure, a signal reproduced from a known optical head from an optical disk is supplied to an A / D converter 11, where it is sampled by a master clock and converted into a digital signal, and the AGC / ATC circuit 12 of the next stage is supplied. To the automatic amplitude control (AG
C) and the threshold of binary comparator are set to direct current (DC) appropriately.
Automatic threshold control (ATC) for controlling is performed.

The output signal of the AGC / ATC circuit 12 is resampled / DPLL through a subtraction circuit 13 described later.
14 are supplied. Resampling / DPLL14
Resampling data (that is, resampling data) generated by resampling (thinning interpolation) the input signal at a desired bit rate with a digital PLL (phase locked loop) circuit in which the loop is completed in its own block. Resampling data of 180 ° out of data phases 0 ° and 180 °) is supplied to the transversal filter 21 in the automatic equalization circuit 15. Further, the resampling / DPLL 14 detects the zero-cross of the resampling data having the phase of 0 °, and the 0 obtained thereby.
The point information is supplied to the later-described tap delay circuit 23 in the automatic equalization circuit 15.

The 0-point information indicates the point at which the bit sampling data crosses the zero level in bit clock units. Further, the resampling / DPLL 14 locks the resampling timing, that is, the frequency so that the resampling data of the phase 180 ° corresponding to the zero cross point indicated by the 0 point information becomes 0. .

The automatic equalization circuit 15 has a resampling / D
PR for resampling data from PLL14
A transversal filter 21 for imparting equalization characteristics,
A multiplier / low-pass filter (LPF) 22 for varying the coefficient of the transversal filter 21 according to the error signal.
, A tap delay circuit 23 for delaying the 0-point information from the resampling / DPLL 14, and a temporary discrimination circuit 24 for generating the error signal based on the output signal of the transversal filter 21 and the delay signal from the tap delay circuit 23. And the polarity of the error signal is inverted to a multiplier / LP
It is composed of an inverter (INV) 25 supplied to F22.

The transversal filter 21 performs waveform equalization processing based on the tap coefficient (filter coefficient) from the multiplier / LPF 22, and intersymbol interference with the signals before and after the read signal from the desired track to be reproduced. Reduce the effect of. The waveform equalized signal output from the transversal filter 21 is output to the Viterbi decoder and is also supplied to the temporary discrimination circuit 24. The temporary discrimination circuit 24 is
The waveform equalized signal output from the transversal filter 21, the delay signal from the tap delay circuit 23, the PR mode signal indicating the type of partial response (PR), and the run length limitation of the signal recorded on the optical disc. RLL indicating the code length (minimum inversion interval or maximum inversion interval)
A mode signal is input, and based on these, a tentative determination (convergence target setting) is performed on the premise of partial response equalization.

Here, to explain the partial response (PR) equalization, for example, PR (a, b, b, a)
When the characteristic of is added to the solitary wave shown in FIG. 2A for equalization, the equalized waveform is well known as shown in FIG.
As shown in. Further, in the continuous wave, this equalized waveform is 0, a, a + b, 2a, 2b, a + 2b, 2a + 2.
Takes 7 values of b. When these 7 values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are constrained by the past signal, and this (1,7)
It is known that the state transition diagram as shown in FIG. 2 (C) can be represented by utilizing the fact that the input signal "1" does not last twice or more by RLL.

In FIG. 2C, S0 to S5 indicate a state determined by the immediately preceding output value. From this state transition diagram, for example, when the input value is a + 2b, the output value becomes 1 and the state transitions to state S3 when the input value is a + 2b, and when the input value is 2b, the output value becomes 1 and the state transitions to state S4. However, it turns out that the other input values are not input, and if they are input, it is an error.

Here, the value Z of the 0 point information is "
When it is 1 ", it indicates a zero cross point, which is represented by the value" a + b "in the state transition diagram of PR (a, b, b, a) shown in FIG. 2 (C). , S1 → S2 or S4 → S5. In this case, the right half state S in FIG.
2, S3 and S4 follow a positive value path (either a + 2b, 2a + 2b or 2b when normalized to a + b = 0), and the left half states S5, S0 and S1 are negative value paths (a + b In the case of normalization to = 0, any one of 0, a, and 2a) is traced. Therefore, by referring to the value before or after the zero cross point, it is possible to determine whether the route is a positive route or a negative route.

Moreover, if the interval from one zero cross point to the next zero cross point is known, that is, from the state S2 to the state S5, or from the state S5 to the state S.
If the number of transitions up to 2 is known, the route is determined, and the possible values become clear for each sample point.

Further, in the above state transition diagram, when the value is other than "a + b", that is, when it is not the zero cross point, the value Z of the 0 point information is "0". From this state transition diagram, two zero cross points (Z = 1) are not consecutively taken out, and in the case of RLL (1, X), at least one "1" is provided between adjacent Z = 1. 0 ”exists (when the value Z of the 0 point information changes from 1 → 0 → 1; that is, when the state S1 → S2 → S4 → S5 or the state S4 → S5 → S1 → S2 transits). In addition,
In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1.

In the actual signal, due to the influence of noise, etc.
It is quite possible that the detection of the zero-cross point itself will be erroneous, but in the case of feedback control, if the probability of being able to make a correct decision exceeds the probability of erroneous, it should converge in the correct direction, and it is also sufficient. Because of the integration process,
Single-shot noise is considered to be practically no problem.

Focusing on the above points, the tentative discrimination circuit 24 discriminates the value Z of the 0-point information input from the tap delay circuit 23 at each cycle of the bit clock, and the five values of consecutive 5 clock cycles are identified. Whether all are "0", only the first value among the above five values is "1", only the last value among the above five values is "1",
It is determined whether the first and last values of the above five values are "1" and the remaining three values are "0".

In these patterns, when the value Z of the 0-point information of interest is "0", the value Z of the 0-point information on both sides is "0". At this time, the signal waveform is Since it is the case of sticking to the positive side or the negative side, a large value P1 is calculated when either of these patterns is satisfied.

If none of the above patterns,
Value 0 of 5 0 point information in 5 consecutive clock cycles
Is "01010", and in the case of this pattern, it is determined based on the RLL mode signal whether the partial response equalization of RLL (1, X) is performed. Since this pattern may occur only at RLL (1, X), a small value P2 is calculated at RLL (1, X).

If the value Z of the five 0-point information in consecutive 5 clock cycles is not "01010", then those 5
The value Z of one 0 point information is "01001", "100"
It is determined whether the pattern is any one of 10 "," 00010 ", and" 01000 ". For these four patterns, the value Z of the 0 point information of interest is" 0 ".
Then, one of the values Z of the 0-point information adjacent on both sides is “1”. When it is one of the four patterns, or "01010", and R
When it is determined that the LL mode is not (1, X), P
An intermediate level value P3 of 1 and P2 is calculated.

When the values P1, P2 or P3 are calculated, when the waveform equalization signal at the current time input to the temporary discrimination circuit 24 is 0 or more, the final temporary determination level Q is P1 at that time.
When the value is P2 or P3, and the value is negative, the final provisional determination level Q is inverted in polarity from the value of P1, P2, or P3 at that time. If none of the above, the final provisional determination level Q is set to 0.

As described above, the provisional discrimination circuit 24 outputs the PR mode signal indicating the type of partial response equalization, the RLL mode signal indicating the type of run length limited code of the reproduction signal, and the plurality of tap delay circuits 23. The zero point information and the reproduction signal after the waveform equalization of the transversal filter 21 are received as inputs, and the PR mode signal and the RL are received.
A tentative discrimination level (temporary discrimination value) Q of the waveform equalized signal is calculated based on the state transition determined by the L mode signal and a plurality of zero point information patterns. This tentative judgment value Q is an error signal (error information) as a target value for waveform equalization, by taking the difference from the output signal after waveform equalization of the transversal filter 21 which is an actual signal.

This error information is sent to the inverter (INV) 2
While being input to 5, the error calculator 16 is supplied.
In addition, the tap delay circuit 23 performs resampling / DP.
Output from LL14 and resampling / DPLL1
The zero point information indicating the timing at which the sample point formed by resampling, corresponding to the zero cross point 4 to be locked, is extracted as described above, and the 0 point information is the tap delay circuit 23.
Is supplied to the error calculator 16. The error calculator 16 extracts only the necessary DC offset information from the error information based on the 0 point information, and supplies it to the subtraction circuit 13 as a DC deviation component after the integration processing.

FIG. 3 is a block diagram of the first embodiment of the error calculator 16. In the figure, the switch circuit 3
0 is the error information input to the terminal 30a, and the terminal 30b
When the 0 point information from the tap delay circuit 23 is "1", the fixed 0 point information from the 0 generator 31 input to the (Indicating the timing at which the sample points formed by resampling exist), the effective component of the error information input to the terminal 30a is selected, and the adder 33 and the latch circuit 34 are selected.
Is supplied to a digital low-pass filter (LPF) 32, which is integrated there and output as a DC shift component (DC offset component). When the 0 point information is "0", the switch circuit 30 selects the fixed value 0 from the 0 generator 31 input to the terminal 30b and inputs it to the LPF 32. At this time, the output of the LPF 32 is held at the previous value.

As described above, in this embodiment, as shown in FIG. 4, of the output error information (crosstalk cancel error signal) of the temporary discrimination circuit 24, the reproduced digital signal I input to the resampling / DPLL 14 is input. Only the error information corresponding to the zero-cross sample indicated by the white circle is integrated by the LPF 32 and can be regarded as a DC shift component. Therefore, this is input to the subtraction circuit 13 and subtracted from the output signal of the AGC / ATC circuit 12. As a result, the subtraction circuit 13 outputs a DC signal from the output signal of the AGC / ATC circuit 12.
The ingredients can be removed.

Returning to FIG. 1 again, the error signal whose polarity is inverted by the inverter 25 is output by the multiplier / LPF2.
After being multiplied by the tap output from the transversal filter 21 in 2, the high frequency component is removed, and then the tap coefficient (filter coefficient) that makes the above error signal 0
Is output to the transversal filter 21 as The equalized reproduction waveform to which the PR characteristic is added by the automatic equalization circuit 15 is supplied from the transversal filter 21 to a Viterbi decoding circuit (not shown) and is Viterbi decoded. The circuit configuration of this Viterbi decoding is publicly known, and for example, a branch metric calculation circuit that calculates a branch metric from a sample value of a reproduced waveform after equalization and a branch metric are cumulatively added every clock to calculate a path metric. It is composed of a path metric calculation circuit and a path memory for storing a signal for selecting the most probable data series having the smallest path metric. This path memory is
A plurality of candidate sequences are stored, and the candidate sequence selected according to the selection signal from the path metric calculation circuit is output as the decoded data sequence.

Note that the subtraction circuit 13 uses the resampling
You may make it insert-connect between the signal paths from the DPLL 14 to the transversal filter 21.

FIG. 5 is a block diagram of the second embodiment of the error calculator 16. In the figure, parts that are the same as the parts shown in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted. This error calculator is characterized in that the switch circuit 30 is switched based on the result of selecting the temporary discriminant value output from the temporary discriminator circuit 24 by the selector circuit 36, instead of the 0-point information from the tap delay circuit 23. . That is, the provisional discrimination value output from the provisional discrimination circuit 24 should be set to the target value for PR equalization, and the deviation from the target value is output as an error signal. Discrimination circuit 24
When “0” corresponding to the zero cross point is output as a target value, “1” is output, and when the output signal of the temporary discrimination circuit 24 is other than “0”, “0” is output.

As a result, the switch circuit 30 is connected to the terminal 30.
When the error information input to a and the fixed value 0 from the 0 generator 31 input to the terminal 30b are received as inputs, and the output signal of the selection circuit 36 is "1" (at this time, by resampling). (Indicating the timing at which the formed sample points exist), the effective component of the error information input to the terminal 30a is selected and supplied to the LPF 32,
DC integration component (DC offset component)
To output.

FIG. 6 is a block diagram of the third embodiment of the error calculator 16. In the figure, parts that are the same as the parts shown in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted. The error calculator 16 is characterized in that the switch circuit 30 is switched based on the logical sum operation result of three adjacent 0-point information from the tap delay circuit 23. That is, when at least any one of the three 0-point information of consecutive 3 clock cycles is "1", they are zero crossing of the reproduced digital signal II inputted to the resampling / DPLL 14 as shown in FIG. When the LPF 32 integrates only the error information corresponding to the zero-cross sample indicated by the white circle and the samples indicated by the white triangles before and after the zero-cross sample indicated by the white circle, it is DC.
Since it can be regarded as a deviation component, this is output.

In FIG. 6, resampling / DPLL
The 0-point information from 14 is delayed by one sample clock each by two cascaded latch circuits 38 and 39 in the tap delay circuit 23, and the OR circuit 40.
And is directly supplied to the OR circuit 40. Therefore, the OR circuit 40 outputs "1" only when at least one of the three consecutive 0-point information is "1", and the switch circuit 30 has the terminal 30a.
LPF3 by selecting the effective component of the error information input to
It is supplied to 2, and integrated here to be output as a DC shift component (DC offset component).

FIG. 8 is a block diagram of the fourth embodiment of the error calculator 16. In the figure, parts that are the same as the parts shown in FIG. 3 are given the same reference numerals, and descriptions thereof will be omitted. This error calculator operates the switch circuit 30 not by the 0 point information,
Further, it is characterized in that the output signal of the temporary discrimination circuit 24 is switched based on the result selected by the selection circuit 42 by an algorithm different from that of the selection circuit 36 of FIG.

That is, in the selection circuit 42, the input output signal of the temporary discrimination circuit 24 corresponds to 0 and the minimum inversion interval when normalized to a + b = 0 in the state transition diagram of FIG. 2C. When the level, that is, when the PR mode is (1, X) → (b−a) or − (b−a) (2, X) → b or −b, the zero cross point or its It is judged to be the value before and after, and "1" is output, otherwise "1" is output.
As a result, when the output signal of the selection circuit 42 is "1", the switch circuit 30 selects the effective component of the error information input to the terminal 30a to select the LPF 32.
To a DC offset component (DC offset component).

Next, a second embodiment of the present invention will be described. FIG. 9 shows a block diagram of a second embodiment of a digital signal reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In the embodiment shown in FIG.
In the embodiment, the offset information is fed back to the input side of the transversal filter 21.
In this embodiment, the output DC offset component of the error calculator 19 is subjected to feedforward control in which the subtraction circuit 18 subtracts the signal on the output side of the transversal filter 21.

That is, the error information output from the subtraction circuit in the temporary discrimination circuit 24 and the 0-point information output from the tap delay circuit 23 are supplied to the error calculator 19. Like the error calculator 16, the error calculator 19 has the configuration of FIG. 3, FIG. 6, FIG. 6 or FIG. 8, and extracts only the necessary DC offset information from the error information based on the 0 point information, The result of the integration processing is supplied to the subtraction circuit 18 as a DC shift component. Subtraction circuit 18
Is provided in the automatic equalization circuit 17, and outputs the output D of the error calculator 19 from the output signal of the transversal filter 21.
Subtract C offset information. As a result, the subtraction circuit 1
From 8, it is possible to obtain a signal in which DC error components such as DC deviation and DC fluctuation are significantly reduced.

Next, the data waveform of the above-described first embodiment will be described. Figures 10 to 13 actually resample a signal with DC offset and fluctuations, and perform DPL.
An eye pattern of data input to L14 and when crosstalk cancellation by the error calculator 16 is not performed, the vertical axis is the level, the horizontal axis is the time axis, and the arrow attached to the vertical axis is the original Indicates 0 level.

FIG. 10 shows the resampling / DPLL 14
The output signal of is sliced at the absolute 0 level of the circuit and the eye pattern of the resampling data of the phase 0 ° for discriminating between "1" and "0" is shown in FIG. The eye pattern of the output signal of the resampling / DPLL 14, which is the resampling data of the phase 180 ° for waveform equalization, is shown in FIG. 12, where the output signal of the automatic equalization circuit 15 is sliced at the absolute 0 level of the circuit. ”
The eye pattern of the re-sampling data of the phase 0 ° for discriminating 1 "and" 0 "is shown in FIG. The eye patterns of the sampling data are shown respectively.

As can be seen from FIGS. 10 to 13, the levels of these data are clearly offset, and the DC fluctuations existing in the input signal are output as they are.
As a result, in the case of the data of FIGS. 10 and 12, if the slice discrimination is simply performed at the 0 level (+ polarity is 1 and −polarity is 0), a large amount of data will cause a discrimination error. On the contrary, even if the adaptive equalization processing is performed using the transversal filter 21 or the like, the optimum state (coefficient)
12 and FIG. 13 that it is not possible to converge to
I understand from. In such a state, no matter how much the Viterbi decoder is used in the subsequent stage, the error cannot be eliminated (in particular, Viterbi decoding is weak in DC shift).

On the other hand, when the signal having the DC offset and the fluctuation is actually input to the resampling / DPLL 14 and the crosstalk cancellation is performed by the error calculator 16, the eye pattern of the data is as shown in FIG.
It is shown in FIG. Figure 14 shows resampling and DPL.
The output signal of L14 is sliced at the absolute 0 level of the circuit and the eye pattern of the resampling data of the phase 0 ° for discriminating between "1" and "0" is shown in FIG. The eye pattern of the output signal of the resampling / DPLL 14, which is the resampling data of the phase 180 ° for equalization, is shown in FIG. 16 by slicing the output signal of the automatic equalization circuit 15 at the absolute 0 level of the circuit. 1 ”
And an eye pattern of re-sampling data of phase 0 ° for discriminating between "0", and FIG. 17 shows phase 1 for decoding the output signal of the automatic equalization circuit 15 by the Viterbi decoding circuit in the subsequent stage.
The eye patterns of the 80 ° resampling data are shown.

As can be seen from FIGS. 14 to 17, these data show DC fluctuations and DC fluctuations as compared with FIGS. 10 to 13.
Both the shift and the shift are greatly reduced, and therefore, FIGS.
As can be seen from the above, it can be seen that a correct value can be determined even with a simple 0-level slice. Also, FIGS.
It can be seen that the sample corresponding to the zero-cross point from is controlled correctly to 0 level. In this state,
The Viterbi decoding circuit in the latter stage can exhibit a high error rate reduction effect that is closer to the theoretical value.

Next, another embodiment of the present invention will be described. FIG. 18 shows a block diagram of a third embodiment of the digital signal reproducing apparatus according to the present invention. In the figure, FIG.
The same components as in FIG. In this embodiment, the error calculator 51 receives as input the 0-point information from the tap delay circuit 23 and the output signal of the transversal filter 21, and outputs only the necessary DC offset information from the output signal of the transversal filter 21. , 0 point information is extracted and subjected to integration processing, and is supplied to the subtraction circuit 13 as a DC deviation component. The subtraction circuit 13 subtracts the output DC offset information of the error calculator 51 from the output signal of the AGC / ATC circuit 12, and can obtain a signal in which DC error components such as DC shift and DC fluctuation are significantly reduced.

FIG. 19 shows a block diagram of the fourth embodiment of the digital signal reproducing apparatus according to the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the error calculator 53 receives as an input the provisional discrimination value from the provisional discrimination circuit 24 and the error information which is the difference value between the provisional discrimination value and the output signal of the transversal filter 21. Of the DC offset information necessary for sampling the sampling point formed by the resampling obtained by the selection circuit 36 or 42 based on the tentative discriminant value, and integrating the extracted DC point. As the deviation component,
It is supplied to the subtraction circuit 13. The subtraction circuit 13 is AGC · A
From the output signal of the TC circuit 12 to the output D of the error calculator 53
By subtracting the C offset information, it is possible to obtain a signal in which DC error components such as DC deviation and DC fluctuation are significantly reduced.

FIG. 20 shows a block diagram of the fifth embodiment of the digital signal reproducing apparatus according to the present invention. In the figure,
The same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, the error calculator 55 uses the temporary discrimination value of the temporary discrimination circuit 24 and the transversal filter 21.
Of the output signal of the transversal filter 21 and only the necessary DC offset information from the output signal of the transversal filter 21, and the sampling point formed by the resampling obtained by the selection circuit 36 based on the provisional discrimination value is present. In accordance with the above, and the integrated result is supplied to the subtraction circuit 13 as a DC shift component.

21, FIG. 22 and FIG. 23 are block diagrams of the sixth, seventh and eighth embodiments of the digital signal reproducing apparatus according to the present invention, respectively. In each figure, the same components as those in FIG. In these embodiments, the error calculators 57, 59, 61 receive the output signal of the transversal filter 21 or the output error signal of the tentative discrimination circuit 24 at one input terminal, and the 0 point information from the tap delay circuit 23 or Temporary discrimination circuit 24
Receives the temporary discrimination value from the other input terminal and outputs only the necessary DC offset information as 0 point information or the temporary discrimination circuit 2.
Based on the tentative discriminant value of 4, the sampling points formed by resampling are extracted in accordance with the timing at which the sampling points exist, and the result of integration processing is supplied to the subtraction circuit 18 as a DC shift component. The subtraction circuit 18 uses the output signal of the transversal filter 21 to determine the error calculator 5
Subtract the output DC offset information of 7, 59, 61,
It is possible to obtain a signal in which DC error components such as DC shift and DC fluctuation are significantly reduced.

The present invention is not limited to the above-mentioned embodiments, and the present invention can be applied not only to recording media such as optical disks but also to transmission of non-DC-free signals that cause band limitation. .

[0056]

As described above, according to the present invention,
0 point information from the delay circuit indicating the timing at which the sampling point formed by resampling, which corresponds to the zero-cross point to which the resampling calculation phase locked loop circuit should be locked by the error calculator, or the waveform from the temporary discrimination circuit Only the effective component of the error signal output from the temporary discrimination circuit or the output signal of the transversal filter corresponding to the timing of the temporary discrimination value of the equalized signal is integrated, and the integrated value is used as the DC offset information in the A / D.
Since the digital signal output from the converter or the transversal filter is subtracted, the DC offset component in the digital signal is removed by this subtraction, and one of the resampling operation phase locked loop circuit and the transversal filter or the decoding circuit is used. Because of the input, the resampling operation phase locked loop circuit and the adaptive equalizer in the subsequent stage do not have the function of controlling the DC component, and the automatic threshold control (ATC) that should control the DC component is provided. In the device, the DC component of the input signal, the output signal of the resampling operation phase locked loop circuit, or the output signal of the adaptive equalizer, which remained due to the slow response and lack of accuracy, can be largely removed. Therefore, in the Viterbi decoding circuit in the subsequent stage, a high error rate reduction effect close to the theoretical value can be obtained. It is possible to volatilization.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a device of the present invention.

FIG. 2 is an explanatory diagram of an example of partial response equalization.

FIG. 3 is a block diagram of a first embodiment of an error calculator.

FIG. 4 is an operation explanatory diagram of FIG. 3;

FIG. 5 is a block diagram of a second embodiment of an error calculator.

FIG. 6 is a block diagram of a third embodiment of an error calculator.

FIG. 7 is an operation explanatory diagram of FIG. 6;

FIG. 8 is a block diagram of a fourth embodiment of an error calculator.

FIG. 9 is a block diagram of a second embodiment of the device of the present invention.

10 is a diagram showing an example of an eye pattern of an output signal of the resampling / DPLL circuit in FIG. 1 when DC cancellation is not performed by the error calculator.

11 is a diagram showing another example of the eye pattern of the output signal of the resampling / DPLL circuit in FIG. 1 when DC cancellation is not performed by the error calculator.

FIG. 12 is a diagram showing an example of an eye pattern of the output signal of FIG. 1 when DC cancellation by an error calculator is not performed.

FIG. 13 is a diagram showing another example of the eye pattern of the output signal of FIG. 1 when DC cancellation is not performed by the error calculator.

14 is a diagram showing an example of an eye pattern of an output signal of the resampling / DPLL circuit in FIG. 1 when an error calculator is used.

15 is a diagram showing another example of the eye pattern of the output signal of the resampling / DPLL circuit in FIG. 1 when an error calculator is used.

16 is a diagram showing an example of an eye pattern of the output signal of FIG. 1 when an error calculator is used.

FIG. 17 is a diagram showing another example of the eye pattern of the output signal of FIG. 1 when an error calculator is used.

FIG. 18 is a block diagram of a third embodiment of the device of the present invention.

FIG. 19 is a block diagram of a fourth embodiment of the device of the present invention.

FIG. 20 is a block diagram of a fifth embodiment of the device of the present invention.

FIG. 21 is a block diagram of a sixth embodiment of the device of the present invention.

FIG. 22 is a block diagram of a seventh embodiment of the device of the present invention.

FIG. 23 is a block diagram of an eighth embodiment of the device of the present invention.

FIG. 24 is a block diagram of an example of a general digital signal reproducing device.

FIG. 25 is a diagram showing an example of a vertically and asymmetrically reproduced signal waveform.

[Explanation of symbols]

11 A / D converter 12 AGC / ATC circuit 13, 18 Subtraction circuit 14 Resampling / DPLL circuit 15, 17 Automatic equalization circuit 16, 19, 51, 53, 55, 57, 59, 61 Error calculator 21 Playback signal Waveform equalization transversal filter 22 Multiplier / LPF 23 Tap delay circuit 24 Temporary discrimination circuit 25 Polarity inversion circuit 30 Switch circuit 32 Digital low-pass filter (LPF) 34, 38, 39 Latch circuit 36, 42 Selection circuit 40 OR circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-9-97476 (JP, A) JP-A-7-262694 (JP, A) JP-A-9-306105 (JP, A) JP-A-5- 227042 (JP, A) JP 2000-123487 (JP, A) JP 11-273256 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/10

Claims (3)

(57) [Claims] 1. A digital signal reproducing apparatus for reproducing a run-length limited code in a reproduced signal, performing partial response equalization on a reproduced signal obtained by reproducing the run-length limited code by using a transversal filter, and then decoding the reproduced signal. An A / D converter for converting the length limited code into a digital reproduction signal; and a resampling operation of the digital reproduction signal output from the A / D converter at a desired bit rate to generate resampling data, A resampling operation phase locked loop circuit that outputs to a transversal filter, generates a bit clock, further detects a zero cross of the resampling data, and outputs 0 point information, and a bit output from the resampling operation phase locked loop circuit. The above is taken out in synchronization with the clock. A delay circuit for outputting at least three consecutive 0-point information, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limited code in the reproduction signal, and the delay The plurality of 0-point information from the circuit and the waveform equalized reproduction signal output from the transversal filter are received as inputs, the state transition determined by the PR mode signal and the RLL mode signal, and the plurality of 0 points. A temporary discrimination circuit that calculates a temporary discrimination value of the waveform equalized signal based on the information pattern and outputs a difference value between the temporary discrimination value and the reproduced signal after the waveform equalization as an error signal; Of the transversal filter based on the output error signal of the coefficient generator for variably controlling the tap coefficient of the transversal filter so that the error signal is minimized. Means and an error signal output from the provisional discrimination circuit or an output signal of the transversal filter is input to a first input terminal, and the resampling operation phase-locked loop circuit corresponds to a zero-cross point to be locked. The 0-point information from the delay circuit indicating the timing at which a sampling point formed by sampling exists or the temporary discrimination value of the waveform equalized signal from the temporary discrimination circuit is input to a second input terminal, and An error calculator that integrates only the effective component of the input signal of the first input terminal according to the timing of the input signal of the second input terminal and outputs the integrated value as DC offset information; Difference signal between the digital reproduction signal output from the converter and the DC offset information output from the error calculator Generated and a digital signal reproducing apparatus characterized by having a subtraction circuit for inputting one to the resampling operation phase locked loop circuit and said transversal filter. 2. A digital signal reproducing apparatus for reproducing a run length limited code in a reproduced signal, performing partial response equalization using a transversal filter on the reproduced signal reproduced by the run length limited code, and then decoding the reproduced signal. An A / D converter for converting the length limited code into a digital reproduction signal; and a resampling operation of the digital reproduction signal output from the A / D converter at a desired bit rate to generate resampling data, A resampling operation phase locked loop circuit that outputs to a transversal filter, generates a bit clock, further detects a zero cross of the resampling data, and outputs 0 point information, and a bit output from the resampling operation phase locked loop circuit. The above is taken out in synchronization with the clock. A delay circuit for outputting at least three consecutive 0-point information, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limited code in the reproduction signal, and the delay The plurality of 0-point information from the circuit and the waveform equalized reproduction signal output from the transversal filter are received as inputs, the state transition determined by the PR mode signal and the RLL mode signal, and the plurality of 0 points. A temporary discrimination circuit that calculates a temporary discrimination value of the waveform equalized signal based on the information pattern and outputs a difference value between the temporary discrimination value and the reproduced signal after the waveform equalization as an error signal; Of the transversal filter based on the output error signal of the Means and an error signal output from the provisional discrimination circuit or an output signal of the transversal filter is input to a first input terminal, and the resampling operation phase-locked loop circuit corresponds to a zero-cross point to be locked. The 0-point information from the delay circuit indicating the timing at which a sampling point formed by sampling exists or the temporary discrimination value of the waveform equalized signal from the temporary discrimination circuit is input to a second input terminal, and An error calculator that integrates only the effective component of the input signal of the first input terminal according to the timing of the input signal of the second input terminal and outputs the integrated value as DC offset information, and the transversal filter Waveform-equalized reproduction signal output from the DC output from the error calculator
And a subtraction circuit for generating a difference signal with respect to the offset information and outputting the difference signal to a decoding circuit. 3. The 0-point information input to the error calculator is not only a sample point formed by resampling, which corresponds to a zero-cross point to which the resampling operation phase locked loop circuit should be locked, and It is a signal indicating the timing of the sample points before and after the sample point, the error calculator, depending on the timing of the sample point and the sample points before and after it, of the error signal or the output signal of the transversal filter 3. The digital signal reproducing apparatus according to claim 1, wherein only the effective component is integrated and the integrated value is output as DC offset information.