JP3994987B2 - Playback device - Google Patents

Description

  The present invention relates to a playback apparatus, and more particularly to a playback apparatus including a waveform equalization circuit for waveform equalizing a run-length limited code reproduced from a recording medium such as an optical disk.

  In a playback apparatus that plays back a run-length limit code from a recording medium such as an optical disc on which the run-length limit code is recorded at a high density, partial response (hereinafter also referred to as PR) equalization is performed to remove waveform distortion of the playback signal. A device using a waveform equalization circuit having characteristics is conventionally known (see, for example, Patent Document 1).

  FIG. 11 shows a block diagram of an example of this conventional reproducing apparatus. In the figure, the run length limit code reproduced from the optical disc 1 by the recording / reproducing system 2 is supplied to the transversal filter 3, where the tap coefficient input from the tap coefficient determiner 6 in the parameter setter 5 is converted to the tap coefficient. Based on this, PR equalization is performed.

  The X value selector 10 selects an X value that is an intersymbol interference value in, for example, PR (1, X, X, 1) equalization in the transversal filter 3 based on the characteristics of the reproduced waveform. Xi is sequentially obtained from the determination result of the rate determiner 9, and finally the value of X that satisfies the allowable error rate is selected. The equalization target waveform generator 8 includes the binary data given from the parameter setting binary data memory 7, the X value of the intersymbol interference imparting value in PR equalization selected by the X value selector 10 and After the equalization, a target waveform is created and given to the tap coefficient determiner 6.

  Bits corresponding to the parameter setting binary data memory 7 are recorded in advance on the optical disc 1. The tap coefficient determiner 6 obtains a tap coefficient such that the reproduced waveform matches the equalized target waveform from the reproduced waveform corresponding to this bit and the equalized target waveform, and inputs it to the transversal filter 3. The discrimination point signal level is obtained and supplied to the ML decoder 4. The ML decoder 4 decodes the equalized reproduction waveform extracted from the transversal filter 3 into binary data with reference to the discrimination point signal level and outputs the binary data.

  The decoded data extracted from the ML decoder 4 is supplied to an error rate determination unit 9, where it is compared with the parameter setting binary data from the parameter setting binary data memory 7 to obtain an error rate. A determination result as to whether or not the error rate satisfies an allowable value is supplied to the X value selector 10. When the error rate determination unit 9 determines that the error rate satisfies an allowable value, the PR (1, X, X, 1) ML method using the tap coefficient and the discrimination point signal level at that time, PR, etc. And maximum likelihood detection are performed.

  Conventionally, an optical disc signal reproduction method for performing maximum likelihood detection with a code inversion interval as a constraint condition after equalizing a reproduction signal by a run length limited code whose minimum code inversion interval is limited to a constant of 2 or more. Thus, a ternary equalization apparatus for only the amplitude excluding the point corresponding to the data string having the minimum code inversion interval among the points immediately before or after the code inversion position and only the amplitude of the code inversion position. Is also known (see, for example, Patent Document 2).

  However, the conventional playback device described in Patent Document 1 among the above-described conventional playback devices is based on the premise that bits corresponding to the parameter setting binary data memory 7 are recorded on the optical disc 1 in advance. If it is unknown whether the recording signal of the optical disc 1 corresponds to the binary data stored in the parameter setting binary data memory 7, the waveform equalization cannot be adaptively performed.

  Therefore, the known pattern data corresponding to the binary data stored in the parameter setting binary data memory 7 is reproduced, and the tap coefficient of the transversal filter 3 must be determined so that the waveform is normally equalized. I must. For this reason, when a reproduction signal is input with a reproduction characteristic different from that when the tap coefficient is determined, it cannot be handled.

  Further, among the above-described conventional reproducing apparatuses, the conventional reproducing apparatus described in Patent Document 2 requires PR threshold equalization performed by the reproducing apparatus to have multiple target values, so that a fine threshold comparison is necessary in the error rate determination unit 9. Thus, there is a problem that the determination becomes difficult due to noise and distortion. Therefore, in devices to which a plurality of types of signals are input (for example, playback devices such as CDs and DVDs), run lengths and PR characteristics to be equalized differ depending on the characteristics of the signals to be played back, so control for adjusting the threshold is complicated. Thus, there is a possibility that it takes a long time for the waveform equalization to be performed stably.

  In view of these points, the present inventor has proposed a playback device capable of performing waveform equalization by higher quality PR equalization without being affected by noise and distortion by realizing an expansion of the convergence range and a shortening of the convergence time. (See Patent Document 3). The reproduction apparatus described in Patent Document 3 reproduces a run-length control code recorded on a recording medium, performs a partial response equalization using a transversal filter, and then decodes the reproduction signal. Detecting means for detecting whether or not a zero cross point of the reproduction signal input to the signal is output and outputting 0 point information; and a delay circuit for outputting at least three consecutive 0 point information extracted from the detecting means in synchronization with the clock; A PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run-length limit code of the reproduction signal, a plurality of 0 point information from the delay circuit, a waveform output from the transversal filter, etc. After receiving the playback signal, the PR mode signal and the RLL mode signal are received. A temporary discriminant value of the waveform equalized signal is calculated based on the determined state transition and a plurality of 0 point information patterns, and a difference value between the temporary discriminant value and the waveform equalized reproduction signal is output as an error signal. The configuration includes a determination circuit and coefficient generation means that variably controls the tap coefficient of the transversal filter so that the error signal is minimized based on the output error signal of the temporary determination circuit.

  In this reproducing apparatus, a temporary determination value of the waveform equalization signal is calculated based on the state transition determined by the PR mode signal and the RLL mode signal by the temporary determination circuit and a plurality of 0 point information patterns, and the temporary determination is performed. Since the difference value between the value and the reproduced signal after waveform equalization is output as an error signal, an error signal that is an error from the convergence target is generated and output without depending on the level of the current sampling point, By variably controlling the tap coefficient of the transversal filter based on this error signal, the partial response waveform equalization characteristic by the transversal filter can be controlled to make the error signal zero.

JP-A-10-106161 JP-A-7-192270 Japanese Patent No. 3395734

  However, in the reproducing apparatus described in Patent Document 3, as the density increases, the read level of the signal having a small run length is significantly reduced, and the characteristic of the reproduced signal is based on the characteristic of PR (a, b, b, a). It will shift. If an attempt is made to match PR (a, b, b, a) forcibly, noise will also be amplified, and as a result, sufficient error rate suppression will not be possible.

  In order to solve this, it may be equalized to PR (a, b, b, b, a) having a larger constraint length, but in that case, a process with more complicated state transition is required. Further, in the reproduction apparatus described in Patent Document 3, the polarity of the waveform equalized signal corresponding to the provisional discrimination detection target is used for polarity determination. However, in a signal having a low level such as a signal having a small run length, The error of 0 point information important for provisional discrimination becomes large.

  The present invention has been made in view of the above points, and even for characteristics that are difficult to tentatively distinguish, such as PR (a, b, b, a), which have a target value of 9 or more, it is likely to be 0. It is an object of the present invention to provide a playback device that can detect point information and perform waveform equalization by higher quality PR equalization without the influence of noise and distortion of determination.

  In order to achieve the above object, the first invention is a reproduction wherein a reproduction signal obtained by reproducing an input run-length limited code is subjected to waveform equalization with a partial response equalization characteristic by an equalizer and then decoded. A / D conversion means for converting a run-length limited code into a digital reproduction signal, and a digital reproduction signal output from the A / D conversion means at a desired bit rate for resampling data. Re-sampling calculation phase-locked loop circuit means for generating and supplying zero-point information obtained by detecting the zero-cross point of the digital reproduction signal and supplying it to the equalizer. The loop circuit means is for re-sampling data, for low-frequency signals whose amplitude is larger than the threshold value. Signal processing means for providing a non-linear equalization characteristic that amplifies the amplitude without limiting the amplitude for a high frequency signal having a width smaller than the threshold, and signal processing output from the signal processing means A phase detection unit that detects a zero cross point from a rear signal, outputs a phase error using a data value at the zero cross point, and outputs 0 point information indicating the zero cross point, and a phase error output from the phase detection unit Based on the data point phase information, and interpolation means for estimating the data value of the phase point data from the data point phase information and the generated bit clock by interpolation and outputting it as resampling data. , Determined by the predetermined partial response equalization characteristics to be given to the resampling data and the run length restriction rule of the playback signal And state transitions that, by using the 0-point information, characterized by waveform equalization by applying a predetermined partial response characteristic.

  In the present invention, the amplitude is limited when the low-frequency signal has a larger amplitude than the threshold with respect to the resampling data, and the amplitude is not limited when the high-frequency signal has a smaller amplitude than the threshold. Since the zero-cross point is detected from the signal-processed signal obtained by giving the nonlinear equalization characteristic to be output and 0-point information is output, PR (a, Probable zero point information is obtained for b, b, b, a).

  In order to achieve the above object, the second invention decodes a reproduction signal obtained by reproducing an input run-length limited code after waveform equalization by giving a partial response equalization characteristic by an equalizer. An A / D converter that converts a run-length limited code into a digital playback signal, and a resampling operation by resampling the digital playback signal output from the A / D converter at a desired bit rate Resampling calculation phase-locked loop circuit means for generating and supplying data to the equalizer and generating 0 point information obtained by detecting the zero cross point of the digital reproduction signal and supplying it to the equalizer The phase-locked loop circuit means applies a low frequency signal having an amplitude larger than a threshold to the resampled data. The signal processing means for limiting the amplitude, and for the high frequency signal having an amplitude smaller than the threshold value, a non-linear equalization characteristic that amplifies the amplitude without limiting the amplitude, and the signal processing means outputs the signal. Zero detection means for detecting a zero cross point from the signal after signal processing and outputting 0 point information indicating the zero cross point; a phase detection means for detecting a phase error from the resampling data; and a next data point phase based on the phase error It is composed of interpolation means that estimates information, estimates the data value of the phase point data from the data point phase information and the generated bit clock by interpolation, and outputs it as resampling data. State transition determined by the predetermined partial response equalization characteristics to be given and the run length restriction rule of the reproduction signal, and 0 points By using the broadcast, characterized by equalizing the waveform by applying a predetermined partial response characteristic.

  Similarly to the first invention, this invention detects zero point information indicating a zero cross point from a signal obtained by giving a non-linear equalization characteristic to resampling data, and is therefore used for high-density optical disc recording. Even for PR (a, b, b, b, a) that is difficult to be temporarily determined, reliable 0-point information is obtained.

  In order to achieve the above object, the third invention decodes a reproduction signal obtained by reproducing an input run-length limited code after waveform equalization by giving a partial response equalization characteristic by an equalizer. An A / D conversion means for converting a run length limited code into a digital reproduction signal, and a digital reproduction signal output from the A / D conversion means with a low frequency having an amplitude larger than a threshold value. A signal processing unit that provides a non-linear equalization characteristic that amplifies the amplitude without limiting the amplitude for a high-frequency signal having a smaller amplitude than a threshold, and the signal processing unit. Zero-detecting means for detecting a zero-cross point of the output signal-processed signal and outputting zero-point information indicating the zero-cross point to the equalizer. The equalizer is an A / D converter. A predetermined partial response characteristic is obtained by using a state transition determined by a predetermined partial response equalization characteristic to be added and a run length restriction rule of the reproduction signal, and 0 point information. It is characterized by being given waveform equalization.

  In the present invention, with respect to the digital reproduction signal, the amplitude is limited for a low frequency signal having an amplitude larger than the threshold, and the amplitude is not limited for a high frequency signal having an amplitude smaller than the threshold. Since the zero-cross point is detected from the signal processed signal obtained by giving a nonlinear equalization characteristic for amplifying the amplitude and 0 point information is output, it is used for high-density optical disc recording, and it is difficult to make provisional discrimination. Probable zero point information is obtained for (a, b, b, b, a).

  In order to achieve the above object, the fourth aspect of the invention decodes a reproduction signal obtained by reproducing an input run-length limited code after giving a partial response equalization characteristic by an equalizer and equalizing the waveform. A reproduction apparatus for converting a run-length limited code into a digital reproduction signal, and a predetermined partial to be added to the digital reproduction signal output from the A / D conversion means by an equalizer Using the state transition determined by the response equalization characteristic and the run-length restriction rule of the reproduction signal and the 0 point information, the waveform is equalized and output by giving a predetermined partial response characteristic and output. However, the amplitude is limited when the signal is a low-frequency signal whose amplitude is larger than the threshold, and the amplitude is not limited when the signal is a high-frequency signal whose amplitude is smaller than the threshold. A signal processing means having a non-linear equalization characteristic for amplifying the width, and a zero cross point of a signal after waveform equalization output from the signal processing means is detected, and 0 point information indicating the zero cross point is output to the equalizer And zero detecting means.

  In this invention, with respect to the waveform equalized reproduction signal output from the equalizer, the amplitude is limited for a low-frequency signal having a larger amplitude than the threshold, and for a high-frequency signal having a smaller amplitude than the threshold. In other words, the zero cross point is detected from the signal after signal processing obtained by applying a nonlinear equalization characteristic that amplifies the amplitude without limiting the amplitude, and 0 point information is output. Even for PR (a, b, b, b, a) that is difficult to be temporarily determined, reliable 0-point information is obtained.

  In order to achieve the above object, according to a fifth aspect of the present invention, there is provided an equalizer according to any one of the first to fourth aspects of the present invention, wherein resampled data or a digital reproduction signal output from A / D conversion means is used. Then, a transversal filter that outputs a reproduced signal after waveform equalization by giving a predetermined partial response equalization characteristic according to the tap coefficient, and 0 point information that is input in synchronization with the bit clock, sequentially one clock at a time A first delay circuit that outputs at least four continuous 0-point information with a delay, and a waveform-equalized reproduction signal are sequentially sampled by one clock in synchronization with the delay period of the first delay circuit, A second delay circuit that outputs values of at least four consecutive sampling points, a PR mode signal indicating the type of partial response equalization, and a reproduction signal An RLL mode signal indicating a length limit rule, a plurality of 0 point information from the first delay circuit, and a plurality of sampling point values from the second delay circuit are received as inputs and designated by the PR mode signal. State transition determined by a predetermined partial response equalization characteristic and a run length restriction rule of a reproduction signal specified by the RLL mode signal, a plurality of 0 point information patterns, and a sampling point of interest among a plurality of sampling points Based on the polarity of the value, a temporary discriminant value of the reproduction signal after waveform equalization is calculated, and a difference value between the temporary discriminant value and the value of the target sampling point output from the second delay circuit is used as an error signal. Based on the temporary discrimination means to output and the error signal output from the temporary discrimination means, the error signal is the minimum tap coefficient of the transversal filter. And a coefficient generation means that variably controls so that the predetermined partial response equalization characteristic designated by the PR mode signal is expressed by PR (a, b, b, b, a). , Tentative determination is performed based on four or more consecutive 0 point information.

  According to the present invention, reliable zero point information can be obtained even for PR (a, b, b, b, a), which is difficult to tentatively discriminate and is used for high-density optical disc recording. An error signal that is an error between the zero point information and the convergence target value determined from the state transition is generated and output without depending on the level of the point, and the transversal filter that constitutes the equalizer based on the error signal By variably controlling the tap coefficient, a correct determination can be made even for a signal in the vicinity of a zero cross with a low level, and as a result, quick and accurate adaptive equalization can be performed.

  Further, according to the present invention, the signal processing means having the nonlinear equalization characteristic is used to obtain 0 point information, and is not used for a signal to which a predetermined partial response characteristic is given by the equalizer. It is possible to maintain the linearity of the reproduced signal and to fully exhibit the ability of Viterbi decoding at the subsequent stage.

  Furthermore, according to the present invention, it is possible to cope with any run-length limit code of the minimum inversion interval 2 and 3, and since it can be constituted by a digital circuit, it is more reliable than an analog circuit and has almost no circuit scale. A configuration that does not increase can be achieved.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a reproducing apparatus according to the present invention. In the figure, a signal reproduced by a known optical head (not shown) from an optical disk (not shown) on which a run-length limit code is recorded at a high density is supplied to an A / D converter 15 where a master is recorded. It is sampled by a clock, converted into a digital signal, and supplied to the AGC / ATC circuit 16 in the next stage, where the amplitude of the amplitude is controlled to be constant and the threshold value of the binary comparison is appropriately DC. (DC) Automatic threshold control (ATC) is performed.

  The digital reproduction signal output from the AGC / ATC circuit 16 is supplied to the resampling DPLL 17. The resampling DPLL 17 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block, and is generated by resampling (decimating interpolation) an input signal with a desired bit date. (That is, resampling data of 180 ° out of the phase 0 ° and 180 ° of the resampling data) is supplied to the transversal filter in the equalizer 18.

  Further, the resampling DPLL 17 detects a zero cross of the resampling data, and supplies 0 point information obtained thereby to a tap delay circuit and an error calculator (both not shown) in the equalizer 18. The 0 point information indicates the point at which bit sampling data crosses the zero level in bit clock units. Further, the resampling DPLL 17 locks the resampling timing, that is, the frequency so that the phase error becomes 0 based on the value of the resampling data corresponding to the zero cross point indicated by the 0 point information.

  FIG. 2 shows a block diagram of a first embodiment of the resampling DPLL 17. In the figure, an interpolator 171 receives a digital reproduction signal output from the AGC / ATC circuit 16 of FIG. 1 and a signal from a timing generator 174 described later as input signals, and a data point input from the timing generator 174. The data value of the phase point data is estimated by interpolation from the phase information and the bit clock and output. The output data value of the interpolator 171 is supplied to the phase adjuster 175 and the signal processor 176, respectively.

  The phase adjuster 175 performs a phase shift or pre-equalization operation by interpolation or the like as necessary so that the supplied data value has a phase necessary for the partial response characteristic of the subsequent stage, and then, FIG. To the equalizer 18. The signal processor 176 is a signal processing operation that imparts non-linear equalization characteristics with a known configuration for the purpose of boosting only 2T (T is the bit period of the reproduction signal) (specifically, the recording mark on the optical disc is long). For low-frequency signals with large amplitudes, the amplitude is limited and the effective filter gain is suppressed. On the other hand, the limiter works for high-frequency signals such as the 2T mark with the shortest recording mark. (Equalization operation for amplifying the amplitude without performing the process), and then the signal after signal processing is supplied to the phase detector 172.

The phase detector 172 detects a zero cross point from the signal after signal processing, and outputs a phase error using a data value at the zero cross point. For example detecting a zero cross point from the 1-bit preceding data _{D t-1} and the data _{D t} at the current _time, by multiplying the polarity of _{D t-1} the _{(D t-1 + D t} ) / 2, the phase error can get.

  Conventionally, only the phase error is output from the phase detector 172, but in this embodiment, 0 point information indicating the zero cross point is also output from the phase detector 172. This 0 point information indicates the timing at which there is a sample point corresponding to the zero cross point that the resampling DPLL 17 should lock.

  The output phase error signal of the phase detector 172 is integrated by the loop filter 173 and then supplied to the timing generator 174, where the next data point phase of the output of the loop filter 173 is estimated, and this data point A bit clock generated in the same manner as the phase information is supplied to the interpolator 171.

  Next, a second embodiment of the resampling DPLL 17 will be described with reference to the drawings. FIG. 3 shows a block diagram of a second embodiment of the resampling DPLL 17 in FIG. In the figure, the same components as those in FIG. In the resampling DPLL 17 shown in FIG. 3, the phase detector 172 receives the output signal of the interpolator 171 directly as an input, and does not use the signal-processed signal. Further, the signal processor 176 supplies a signal after signal processing obtained by the signal processing operation to the zero detector 177 instead of the phase detector 172.

  The zero detector 177 detects and outputs 0 point information indicating a zero cross point from the signal after signal processing. As long as the DPLL loop comprising the interpolator 171, phase detector 172, loop filter 173, and timing generator 174 operates normally, the delay in this embodiment is less than the configuration of FIG. Etc. are advantageous.

  According to the present embodiment, it is possible to obtain probable 0-point information even for partial response characteristics PR (a, b, b, b, a), which are used for high-density optical disc recording and are difficult to temporarily determine. Therefore, the waveform equalization can be performed quickly and accurately by the equalizer 18 that performs waveform equalization based on the 0 point information without depending on the level of the current sample point.

  In addition, according to the present embodiment, the amplitude of the low-frequency signal having a long recording mark on the optical disc and having an amplitude larger than the threshold is limited to suppress the effective filter gain. A signal processor 176 that performs a well-known equalization operation that amplifies the amplitude of a signal having a smaller amplitude and higher frequency than the threshold, such as the shortest 2T mark, without using an amplitude limiter (limiter) is reproduced. Since it is used not for the signal but for obtaining 0 point information, the resampling data can maintain the linearity and fully exhibit the ability of Viterbi decoding in the subsequent stage.

  Returning to FIG. 1 again, the re-sampling DPLL 17 having the configuration shown in FIG. 2 or FIG. 3 described above uses the re-sampling data generated by re-sampling (decimating interpolation) the input signal at a desired bit rate. It is supplied to the equalizer 18 together with the point information. The equalizer 18 imparts a partial response (PR) equalization characteristic to the input resampling data to equalize the waveform.

  FIG. 4 shows a block diagram of an example of the equalizer 18 described above. As shown in the figure, the equalizer 18 provides a transversal filter 31 that outputs a resampling data output from the resampling DPLL 17 with a PR equalization characteristic, and tap coefficients of the transversal filter 31. A multiplier / low-pass filter (LPF) 32 that varies according to an error signal, a tap delay circuit 33 that delays 0-point information output from the resampling DPLL 17, and a waveform that is output from the transversal filter 31 after equalization Based on the reproduction signal and the delay signal from the tap delay circuit 33, a temporary determination circuit 34 that generates an error signal and an inverter (INV) 35 that inverts the polarity of the error signal and supplies it to the multiplier / LPF 32 are provided.

  The tap delay circuit 33 and the provisional discrimination circuit 34 are configured as shown in the circuit diagram of FIG. 5, for example, when the equalizer 18 imparts PR (a, b, b, a) equalization characteristics. As shown in FIG. 5, the tap delay circuit 33 includes a delay adjuster 331 that delays the above-described 0 point information input via the terminal 42, and delay 0 point information output from the delay adjuster 331, respectively. It consists of D-type flip-flops 332 to 334 that are cascaded in three stages that are delayed by time (one cycle of the system clock). In FIG. 5, circuit portions other than the tap delay circuit 33 constitute a provisional determination circuit 34.

  The temporary discriminator 51 includes a waveform equalized reproduction signal input from the transversal filter 31 of FIG. 4 input via the terminal 41, and four 0-point information having different delay times supplied from the tap delay circuit 33. , Receiving a PR mode signal input via a terminal 43 and an RLL mode signal input via a terminal 44 as inputs, and making a provisional discrimination (convergence target setting) using the characteristics of partial response (PR) characteristics. ) The operation is performed and the provisional discrimination value Q is output. The PR mode signal is a signal indicating the type of PR characteristic of the run length limit code reproduced from the optical disc, and the RLL mode signal is a signal indicating the run length limit rule of the reproduction run length limit code.

  That is, as described in Patent Document 3, in the state transition diagram indicated by the PR characteristics specified by the PR mode signal and the RLL specified by the RLL mode signal, when the input value in a certain state is a predetermined value Only when the output value after PR equalization becomes a predetermined value and transitions to the next state, when the input value is other than that, the transition to the next state is not made, so an input value other than the above predetermined value should not be input. Therefore, if an input value other than the predetermined value is input, it is understood that it is an error.

  In addition, the transition of each state in the state transition diagram is synchronized with the output of the value of 0 point information (indicating zero crossing point when 1 and 0 otherwise), and the state corresponding to the zero crossing point is determined. Therefore, by referring to the value before or after the zero-cross point (that is, by referring to the value of four or more consecutive 0 point information with the value of the target point of interest as the median), the state transition If the state transition path in the figure is known and the interval from one zero cross point to the next zero cross point is known, the above path is determined. Therefore, the temporary discriminator 51 performs a temporary discrimination (convergence target setting) operation according to an algorithm focusing on the above points, and outputs a temporary discrimination value Q.

  The subtractor 52 generates an error signal by subtracting the output temporary discrimination value Q of the temporary discriminator 51 from the waveform-equalized reproduction signal from the transversal filter 31 of FIG. 4 input via the terminal 41. This error signal is determined from the state transition of the 0 point information and the reproduction run length limit code (the state transition represented by the state transition diagram when the original data is the input value and the reproduction signal after PR equalization is output). The error from the convergence target value.

  The error signal is supplied to the data input terminal of the D-type flip-flop 53. Here, the bit clock supplied from the terminal 40 is synchronized with the system clock supplied to the clock terminal via the terminal 45. After being latched at the high level, it is output to the output terminal 54. The error signal output from the output terminal 54 is supplied to the multiplier / LPF 32 via the polarity inversion circuit 35 of FIG.

  A bit clock is input to each enable terminal of each of the D-type flip-flops 332 to 334 and 53 via a terminal 40, and a system clock is input to each clock terminal via a terminal 45. Further, a reset signal is input to each clear terminal via a terminal 46.

  FIG. 6 is a circuit diagram showing another example of a circuit unit including the tap delay circuit 33 and the temporary determination circuit 34 shown in FIG. In FIG. 6, the same components as those in FIG. FIG. 6 shows a configuration in which the equalizer 18 imparts PR (a, b, b, b, a) equalization characteristics, and reproduction after waveform equalization from the transversal filter 31 input via the terminal 41. The signal is delayed by unit time (one cycle of the system clock) by the D-type flip-flops 501 to 503 that are cascade-connected in three stages constituting the delay circuit unit 50.

  As a result, three delay waveform equalized reproduction signals (sampling point values) D4, D3, and D2 sequentially sampled one clock at a time in synchronization with the delay period of the tap delay circuit 33 are not delayed from the delay circuit unit 50. The delayed waveform equalized reproduction signal D3 is supplied to the subtractor 52 while the waveform equalized reproduction signal D5 is supplied to the temporary discriminator 55. That is, the delay circuit unit 50 outputs at least four consecutive sampling point values D2 to D5 obtained by sequentially sampling the waveform-equalized reproduction signal by one clock in synchronization with the delay period of the first delay circuit. Is done.

  The temporary discriminator 55 is a state transition determined by a partial response characteristic and a run length restriction rule specified by the PR mode signal and the RLL mode signal, respectively, and 0 point information of four consecutive sampling points supplied from the tap delay circuit 33. A total of four value patterns consisting of the values Z2, Z3, Z4, and Z5, and the value of the sampling point to be processed from the delay circuit unit 50 (usually the data D3 of the current time, which is the system clock The provisional discrimination value Q is determined based on the polarity of data D4 or D2 having different time periods.

  Note that the values Z2 to Z5 of the 0 point information indicate zero cross points when 1 respectively, and 0 otherwise. The provisional discriminant value Q is subtracted from the reproduced signal data D3 after waveform equalization at the current time by the subtractor 52 to be an error signal, latched by the D-type flip-flop 53, and output to the output terminal 54.

  The multiplier / LPF 32 in FIG. 4 is output from the tap output from the transversal filter 31 and the output terminal 54 of the provisional discrimination circuit 34 having the configuration shown in FIG. 5 or FIG. After multiplying the error signal, a tap coefficient (filter coefficient) that reduces the high frequency component to make the error signal zero is generated and supplied to the transversal filter 31.

  In this way, the equalizer 18 having the configuration shown in FIG. 4 adaptively equalizes the input resampling data (waveform equalization) using the transversal filter 31, and the obtained post-waveform equalization reproduction signal is converted into a Viterbi decoding circuit. (Not shown) for Viterbi decoding.

  The circuit configuration of this Viterbi decoding is well known. For example, a branch metric calculation circuit that calculates a branch metric from sample values of an equalized reproduction waveform, and a path that calculates a path metric by accumulating the branch metrics every clock. A metric calculation circuit and a path memory for storing a signal for selecting a most probable data series having a minimum path metric. The path memory stores a plurality of candidate sequences, and outputs the candidate sequences selected according to the selection signal from the path metric calculation circuit as a decoded data sequence.

  Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 shows a block diagram of a second embodiment of the reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. In the second embodiment shown in FIG. 7, the resampling DPLL 17 is not used, and the sampling clock of the A / D converter 15 is controlled by a phase-locked loop (not shown). Further, the output signal of the AGC / ATC circuit 16 is supplied to the equalizer 18 and is also supplied to the signal processor 19 having a known configuration and subjected to signal processing with the same nonlinear equalization characteristic as the signal processor 176. .

  From the signal processed signal obtained by the signal processing by the signal processor 19, zero point information indicating a zero cross point is detected by the zero detector 20, and the zero point information is supplied to the equalizer 18. This embodiment also has the following effects similar to those of the first embodiment of FIG.

  Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows a block diagram of a second embodiment of the reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. In the second embodiment shown in FIG. 7, the resampling DPLL 17 is not used, and the sampling clock of the A / D converter 15 is controlled by a phase-locked loop (not shown).

  The digital reproduction signal output from the AGC / ATC circuit 16 is supplied to the equalizer 18 and is subjected to waveform equalization according to a predetermined waveform equalization characteristic. The waveform-equalized reproduction signal output from the equalizer 18 is supplied to the signal processor 22 where signal processing with a known non-linear equalization characteristic similar to the signal processor 176 is performed.

  From the signal processed signal obtained by the signal processing by the signal processor 22, zero point information indicating a zero cross point is detected by the zero detector 23, and the zero point information is supplied to the equalizer 21. Although the present embodiment is different from the second embodiment in that predetermined signal processing and zero detection are performed on the waveform equalized reproduction signal output from the equalizer 21, this embodiment is different. 1 has the same effects as described later in the first embodiment of FIG. 1 and the second embodiment of FIG.

  Next, the effect of the present invention will be described with reference to the drawings. 9 and 10 show examples of the eye pattern of the output signal of the decoding circuit that performs Viterbi decoding of the output signals of the equalizers 18 and 21 of the playback apparatus according to the present invention. 9 and 10, the vertical axis indicates the quantization level, and the horizontal axis indicates time. In the example shown in FIG. 10, the partial response characteristic PR (a, b, b, b, a) is PR (1, 2, 2, 2, 1), the minimum inversion interval is “2”, and the maximum inversion In this example, the run length limit code of the run length limit rule RLL (1, X) having a predetermined value X whose interval differs depending on the modulation method is reproduced. 0, a, 2a, a + b, 2a + b, 2b, a + 2b, 3b It converges to 9 values of 0, 1, 2, 3, 4, 5, 6, 7, and 8 corresponding to a + 3b and 2a + 3b (however, the actual data is a value quantized with 8 bits or the like) Because there is, it is the value multiplied by the gain.)

  Further, in the example shown in FIG. 10, the partial response characteristic PR (a, b, b, b, a) is PR (1, 3, 3, 3, 1), and the run length restriction rule RLL (1, X ) Run length limited code is reproduced, and 0, 1, 2, 4, 5, 6, 7 corresponding to 0, a, 2a, a + b, 2a + b, 2b, a + 2b, 3b, a + 3b, 2a + 3b. , 9, 10, and 11 (however, since actual data is a value quantized with 8 bits or the like, it is a value multiplied by the gain). As shown in FIG. 9 and FIG. 10, according to the reproducing apparatus of the present embodiment, it can be seen that the reproduced signal is well converged to each value, and an accurate waveform equalization is achieved.

  The present invention is not limited to the above embodiment. For example, the partial response characteristics are PR (1, 1, 1, 1, 1), PR (3,4, 4, 4, 3), etc. The run length restriction rule can also be applied to a run length restriction code of RLL (2, X) having a predetermined value X whose minimum inversion interval is “3” and the maximum inversion interval is different depending on the modulation method. Is possible.

It is a block diagram of 1st Embodiment of this invention apparatus. It is a block diagram of a first embodiment of a resampling DPLL. It is a block diagram of 2nd Embodiment of resampling DPLL. It is a block diagram of an example of the equalizer in this invention apparatus. FIG. 5 is a circuit diagram of an example of a temporary determination circuit and a tap delay circuit in FIG. 4. FIG. 5 is a circuit diagram of another example of the temporary determination circuit and the tap delay circuit in FIG. 4. It is a block diagram of 2nd Embodiment of this invention apparatus. It is a block diagram of 3rd Embodiment of this invention apparatus. It is a figure which shows an example of the eye pattern of the output signal of the decoding circuit of this invention apparatus. It is a figure which shows the other example of the eye pattern of the output signal of the decoding circuit of this invention apparatus. It is a block diagram of an example of the conventional reproducing | regenerating apparatus.

Explanation of symbols

15 A / D converter 16 AGC / ATC circuit 17 Resampling DPLL
18, 21 Equalizer 19, 22, 176 Signal processor 20, 23 Zero detector 171 Interpolator 172 Phase detector 173 Loop filter 174 Timing generator 175 Phase adjuster

Claims (5)

A reproduction device that decodes a reproduction signal obtained by reproducing an input run-length limited code, after giving a partial response equalization characteristic by an equalizer and equalizing the waveform,
A / D conversion means for converting the run length limited code into a digital reproduction signal;
The digital reproduction signal output from the A / D conversion means is resampled at a desired bit rate to generate resampling data and supply it to the equalizer, and the zero cross point of the digital reproduction signal is detected. Re-sampling calculation phase-locked loop circuit means for generating the obtained 0-point information and supplying the generated zero-point information to the equalizer A signal processing means for imparting a non-linear equalization characteristic that limits the amplitude for a low-frequency signal having a large amplitude and amplifies the amplitude without limiting the amplitude for a high-frequency signal having a smaller amplitude than the threshold value And detecting the zero cross point from the signal processed signal output from the signal processing means, and at the zero cross point A phase detection unit that outputs a phase error using a data value and outputs the zero point information indicating the zero-cross point, and a next data point phase information based on the phase error output from the phase detection unit And interpolating means for estimating the data value of the phase point data by interpolation from the data point phase information and the generated bit clock, and outputting it as the resampling data,
The equalizer uses the state transition determined by a predetermined partial response equalization characteristic to be added to the resampled data and a run length restriction rule of the reproduction signal, and the predetermined point information, and the predetermined point information. A reproduction apparatus characterized by imparting partial response characteristics and performing waveform equalization. A reproduction device that decodes a reproduction signal obtained by reproducing an input run-length limited code, after giving a partial response equalization characteristic by an equalizer and equalizing the waveform,
A / D conversion means for converting the run length limited code into a digital reproduction signal;
The digital reproduction signal output from the A / D conversion means is resampled at a desired bit rate to generate resampling data and supply it to the equalizer, and the zero cross point of the digital reproduction signal is detected. Re-sampling calculation phase-locked loop circuit means for generating the obtained 0-point information and supplying the generated zero-point information to the equalizer A signal processing means for imparting a non-linear equalization characteristic that limits the amplitude for a low-frequency signal having a large amplitude and amplifies the amplitude without limiting the amplitude for a high-frequency signal having a smaller amplitude than the threshold value And detecting the zero cross point from the signal processed signal output from the signal processing means and indicating the zero cross point. Zero detection means for outputting the zero point information, phase detection means for detecting a phase error from the resampling data, estimation of the next data point phase information based on the phase error, and the data point phase information The interpolation means for estimating the data value of the phase point data from the generated bit clock by interpolation and outputting as the resampling data,
The equalizer uses the state transition determined by a predetermined partial response equalization characteristic to be added to the resampled data and a run length restriction rule of the reproduction signal, and the predetermined point information, and the predetermined point information. A reproduction apparatus characterized by imparting partial response characteristics and performing waveform equalization. A reproduction device that decodes a reproduction signal obtained by reproducing an input run-length limited code, after giving a partial response equalization characteristic by an equalizer and equalizing the waveform,
A / D conversion means for converting the run length limited code into a digital reproduction signal;
For the digital reproduction signal output from the A / D conversion means, the amplitude is limited for a low-frequency signal having a larger amplitude than the threshold, and for a high-frequency signal having a smaller amplitude than the threshold. Signal processing means for imparting a non-linear equalization characteristic that amplifies the amplitude without limiting the amplitude,
Zero detection means for detecting a zero-cross point of the signal-processed signal output from the signal processing means and outputting the zero-point information indicating the zero-cross point to the equalizer, and the equalizer includes the A / D Using the state transition determined by a predetermined partial response equalization characteristic to be added to the digital reproduction signal output from the conversion means and the run length restriction rule of the reproduction signal, and the 0 point information, A reproduction apparatus characterized by imparting a predetermined partial response characteristic and performing waveform equalization. A reproduction device that decodes a reproduction signal obtained by reproducing an input run-length limited code, after giving a partial response equalization characteristic by an equalizer and equalizing the waveform,
A / D conversion means for converting the run length limited code into a digital reproduction signal;
State transition determined by a predetermined partial response equalization characteristic to be added to the digital reproduction signal output from the A / D conversion means and a run length restriction rule of the reproduction signal by the equalizer, and 0 point Using the information, the waveform-equalized reproduction signal output after waveform equalization by giving the predetermined partial response characteristic is limited in amplitude when the signal is a low frequency signal whose amplitude is larger than a threshold value, A signal processing means having a non-linear equalization characteristic for amplifying the amplitude without limiting the amplitude when the signal is a high-frequency signal having an amplitude smaller than a threshold;
And zero detecting means for detecting a zero cross point of a waveform-equalized reproduction signal after signal processing outputted from the signal processing means, and outputting the zero point information indicating the zero cross point to the equalizer. Playback device. The equalizer is
A transversal that outputs a reproduction signal after waveform equalization by giving a predetermined partial response equalization characteristic according to a tap coefficient to the digital reproduction signal outputted from the resampling data or the A / D conversion means Filters,
A first delay circuit that sequentially delays the zero point information input in synchronization with the bit clock by one clock and outputs at least four consecutive zero point information;
A second delay circuit that sequentially samples the reproduced signal after waveform equalization in synchronization with a delay period of the first delay circuit by one clock and outputs values of at least four consecutive sampling points;
A PR mode signal indicating the type of partial response equalization; an RLL mode signal indicating a run length restriction rule of the reproduction signal; a plurality of pieces of 0-point information from the first delay circuit; and the second delay. A plurality of sampling point values from a circuit as inputs, and a predetermined partial response equalization characteristic specified by the PR mode signal and a run length restriction rule of the reproduction signal specified by the RLL mode signal. Based on the determined state transition, the pattern of the plurality of 0 point information, and the polarity of the value of the target sampling point among the plurality of sampling points, the provisional discrimination value of the reproduced signal after waveform equalization is calculated, The difference value between the provisional discrimination value and the value of the target sampling point output from the second delay circuit is used as an error signal. And the provisional determination means for force,
Coefficient generation means for variably controlling the tap coefficient of the transversal filter based on the error signal output from the temporary determination means so that the error signal is minimized, and is designated by the PR mode signal When the predetermined partial response equalization characteristic is expressed by PR (a, b, b, b, a), the temporary determination means makes a temporary determination based on the four or more consecutive 0-point information. The playback apparatus according to claim 1, wherein:

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