JP4612615B2 - PRML detector - Google Patents

Description

  The present invention relates to a technique for equalizing a waveform of a signal read from a recording medium such as an optical disk.

  In an information reproducing apparatus that reproduces information recorded on a recording medium such as an optical disk, conventionally, a slicing method is adopted in which “1” is determined if the waveform level of the signal is greater than a predetermined value, and “0” if the signal waveform level is smaller. I came. However, with this method, it is difficult to reproduce data with high reliability on a recording medium having a greatly improved recording density. Therefore, in recent years, a PRML (Partial Response Maximum Likelihood) method capable of reproducing data with high reliability has attracted attention. The PRML system is a technique used as a high-density signal processing technique for recording media such as a HDD (hard disk drive), a digital recording camera-integrated VTR, and a recordable / rewritable optical disk. This is because as the recording density increases, the necessity of restoring correct data from a reproduction signal having a low S / N (signal to noise) or a non-linear reproduction signal has become stronger.

  FIG. 16 is a block diagram showing a general configuration of an information reproducing apparatus 181 using the PRML method. First, the optical pickup 183 irradiates the optical disk 182 with laser light. The information reproducing device 181 detects the intensity of the reflected light, reads information (data) recorded on the optical disk 182, converts it into an electrical signal, and outputs it to an FEP (Front End Processor) 184. The FEP 184 amplifies the read electrical signal and adjusts the gain. The FEP 184 further performs unnecessary high-frequency noise component removal processing and necessary signal band enhancement processing. An output signal from the FEP 184 is converted into a digital signal by an A / D (analog / digital) converter 185 and input to a waveform equalizer 186. The waveform equalizer 186 equalizes the digital signal to a preset PR characteristic. The maximum likelihood decoder 187 decodes the signal equalized to the PR characteristic and outputs it as reproduced data.

  The waveform equalizer 186 of the information reproducing device 181 generates a waveform so as to have a desired PR characteristic, for example, a PR (3, 4, 4, 3) characteristic. FIG. 17 is a block diagram illustrating an example of the configuration of the waveform equalizer 186. The waveform equalizer 186 is called a transversal filter or an FIR (Finite Impulse Response) filter. The waveform equalizer 186 generally has a plurality of delay elements 192, a plurality of equalization coefficients (coefficients A to E) for realizing desired PR characteristics, and a plurality of equalization coefficients multiplied by the output of the delay element 192. It comprises a multiplier 193 and an adder 194 that adds the outputs of a plurality of multipliers 193.

  A technique for automatically adaptively controlling the equalization coefficient (tap) of the FIR filter is employed in order to equalize the desired PR characteristic with high accuracy. This technique is effective against various stresses during reproduction (disc tilt, laser beam defocus, optical head off-track, etc.). Many algorithms such as LMS (Least-mean square) algorithm, Normalized LMS algorithm, RLS (Recursive Least Square) algorithm, projection algorithm, and neural network algorithm are known as adaptive control algorithms.

  Here, an adaptive waveform equalizer using the LMS algorithm will be briefly described. In this algorithm, in order to calculate an adaptive equalization coefficient, a temporary determination value used in LMS is required. This LMS algorithm is a feedback operation that minimizes the square error between the “desired response” and the “transmission path response”. This “desired response” is a PR equalization target value. The “transmission path response” is a digital reproduction signal input from the FIR filter and equalized to the PR frequency characteristics. In the LMS algorithm, a signal representing a difference between a temporary determination value and a digital reproduction signal value after equalization obtained in a block for adaptively controlling the coefficients of the FIR filter is referred to as an equalization error signal.

  The block that adaptively controls the coefficient of the FIR filter updates the equalization coefficient of the FIR filter as needed so as to minimize the square value of the equalization error signal. This is called adaptive equalization. An equation for setting the equalization coefficient of LMS is shown in the following equation (for example, S. Haykin, Introduction to Adaptive Filter, Hyundai Engineering Co., Ltd.).

w (n (T + 1)) = w (nT) + A · e (nT) · x (nT) (Formula 1)
(However, T = 0, 1, 2, 3, ...)
w (nT) is a current coefficient, w (n (T + 1) is a coefficient to be updated, A is a tap gain, e (nT) is an equalization error, x (nT) is an FIR filter input signal, and n is This is a parameter for selecting the coefficient update period, and the equalization coefficient of the FIR filter is updated by the above-described equation 1.

  Here, asymmetry of the optical disk 182 (FIG. 16) will be described. Asymmetry means that there is no symmetry between optical disk pits and non-pits. Information is recorded on the optical disk 182 (FIG. 16) by the arrangement and length of minute embossed portions called pits. When the reference length is T, the pit has a length of 3T, 5T, for example. The pits are arranged with 3T and 5T spaces. The length of the pit is preferably 3T or 5T. However, there is some variation in pit length. This is because, for example, a master master having a variation in pit length is produced as a result of slight fluctuations in the power of the recording light used for mastering the optical disc. When the recording power is not appropriate, each formed pit is slightly longer or shorter by the same amount than the standard value before and after the length direction. That is, the symmetry between pits and non-pits is lost. This is asymmetry. Hereinafter, in this specification, it is assumed that the relationship between pits and non-pits in an optical disc is the same as the relationship between a recorded portion (mark) and an unrecorded portion (space) of a hard disk or the like. Note that the words "pit" and "non-pit" are used for read-only optical discs, and for recordable optical discs, the location where information is recorded (that is, the location where the laser is irradiated strongly) is marked with ", And the space between marks may be called" space ". In this specification, “pit” and “mark” are synonymous. “Non-pit”, “space” and “non-mark” are synonymous. A signal when an optical disc without symmetry between pits and non-pits (that is, an asymmetry) is called an asymmetry signal, and a signal when an optical disc that is not asymmetry is played is called a symmetry signal.

  FIG. 18 is a diagram showing a simple asymmetry model. FIG. 18 shows a pit arrangement of a 3T mark, a 3T space, a 5T mark, and a 5T space. Here, the reference length is 1, and the detection window (window) width is adopted. FIG. 18B shows a standard pit arrangement in which both marks and spaces are symmetrical. On the other hand, in FIG. 18A, the mark width is uniformly reduced by the length x. Further, in FIG. 18C, the mark width is uniformly increased by the length y. In either case, no symmetry is observed in both marks and spaces. Since this asymmetry is also generated by the wavelength variation of the laser used, it is generally difficult to adjust and maintain the symmetry between pits and non-pits during recording.

  Next, a specific hardware configuration and procedure for binarizing the analog data signal (reproduction signal) read from the optical disc will be described. FIG. 19 is a block diagram showing a configuration of the PRML detector 210. The PRML detector 210 performs adaptive equalization and updates the equalization coefficient of the FIR filter as needed. First, the A / D converter 221 of the PRML detector 210 converts the reproduction signal from an analog signal to a digital signal. The phase comparator 222 generates binarized data based on a certain threshold value. Next, the PR temporary determiner 223 receives the binarized data. The temporary PR determination unit 223 temporarily determines the target value of the PR method and outputs the target value to the coefficient adaptive controller 224. The target value of the PR method can be determined based on the amplitude zero-cross information obtained by the phase comparator 222 (for example, ITE Technical Report Vol. 24, No. 46, PP. 13 to 18). MMS2000-14 (Jul. 2000)). Next, the coefficient adaptive controller 224 updates the equalization coefficient (tap) of the FIR equalizer 225 using the adaptive algorithm described above. The Viterbi decoder 226 converts the waveform equalized to a predetermined PR in the FIR equalizer 225 into binary data.

  Note that the phase comparator 22 detects the phase error from the output of the A / D converter 21 and uses the loop filter and digital signal as an analog signal for the clock used by the A / D converter 21. It is generated by the DAC that converts the signal to the voltage and the voltage control oscillator VCO (both not shown) perform predetermined processing.

  FIG. 20 is a block diagram showing the configuration of the PRML detector 220. The PRML detector 220 outputs a judgment value by PR (1, 1) equalization using the output of the FIR equalizer as described in, for example, Japanese Patent Laid-Open No. 2000-123487, and the judgment value Is used to calculate a target value for PR (a, b, b, a) equalization in the FIR equalizer. The A / D converter 231 converts the reproduction signal from an analog signal to a digital signal. The FIR equalizer 32 performs predetermined PR equalization on the digital signal. The PR temporary determination unit 233 uses the data obtained by binarizing the output of the FIR equalizer 32 to temporarily determine the PR system target value and outputs the target value to the coefficient adaptive controller 234. The coefficient adaptive controller 234 updates the tap of the FIR equalizer 232 using the temporary determination value. The PRML detector 220 can reduce the probability of occurrence of a determination error by reducing the determination threshold.

Conventionally, there have been problems shown in the following (1) and (2), and thus a reproduction signal appropriately binarized cannot be obtained. That is,
(1) When there is no symmetry between the pits and non-pits of the optical disk (that is, asymmetry), the performance of the PRML method is degraded. That is, the information reproducing apparatus 181 using the conventional PRML system generates an error due to the asymmetry reproduction signal.

  The above (1) is explained as follows. 21A and 21B show histograms of output signals of the A / D converter 185 in the information reproducing apparatus 81 (FIG. 16). The horizontal axis indicates the level of the reproduction signal, and the vertical axis indicates the frequency of the signal level. This waveform example uses 8-16 modulation used in the DVD (Digital Versatile Disc) standard. That is, the reproduction waveform has a mark length and space length of 3T to 14T (including sync code).

  The phase error is detected based on the center of the reproduction signal level (for example, when the effective bit number of the A / D converter is 7, and the median value 64 (40h) of 0 to 128 that can be expressed), and the reproduction signal is sampled. The frequency and phase of the clock to be controlled are controlled. In such control, the histogram is divided so as to have five distributions. This is because the number of signal levels (signal distribution) is 5 when the PRML system has a PR coefficient like the PR (a, b, b, a) ML system (a and b are , With a positive coefficient). The waveform equalizer 86 controls the clock phase to facilitate PR equalization.

  21A shows a histogram of a reproduction signal that is not asymmetry, and FIG. 21B shows a histogram of an asymmetry reproduction signal. In FIG. 21C, the waveform equalizer 86 performs PR equalization (in this case, PR (3, 4, 4, 3) equalization) on the reproduction signal that is not asymmetry ((A) in FIG. 21). Shows a histogram of the output signal. As can be seen from FIG. 21C, the variance is minimal and each level is clearly separated.

  On the other hand, FIG. 21D shows a histogram of the equalizer output signal when the asymmetry reproduction waveform is PR-equalized. As is apparent from the figure, when the asymmetry reproduction waveform is PR-equalized, the dispersion increases. This is because PRML originally targets symmetrical waveforms and automatically equalizes the waveforms so that all levels are equally spaced. That is, when an asymmetry signal having a minimum variance in a predetermined unequal interval state is supplied, the signal is forcibly equalized at an equal interval, and the variance becomes rather large.

  FIG. 22 is a graph showing the frequency characteristics of the reproduction waveform based on the asymmetry reproduction waveform histogram of FIG. In addition, FIG. 22 also shows the frequency characteristics of the desired PR characteristics. In FIG. 21B, the left side from the center of the reproduction signal level is marked and the right side is a space. In the graph of FIG. 22, when the horizontal axis is the normalized frequency and the vertical axis is the gain, the mark side characteristic and the space side characteristic are different due to the influence of asymmetry. As can be easily understood, in order to equalize the reproduction waveform to a desired PR characteristic, the equalizer needs to perform equalization with different characteristics on the mark side and the space side. However, since the conventional waveform equalizer 6 performs the same equalization processing on the mark side and the space side, it cannot be equalized to a desired PR characteristic with high accuracy. As a result, the variance in the output signal of the maximum likelihood decoder 6 (FIG. 16) increases, leading to performance degradation.

  (2) When the adaptive equalization process is automatically performed, an error may occur in the result of temporary determination (temporary determination value) used in the LMS. Specifically, first, in the systems shown in FIGS. 19 and 20, when the reproduced signal has relatively little noise and the signal quality is good to some extent, satisfactory convergence characteristics can be obtained. However, if the noise caused by the various stresses described above is mixed in the reproduction signal and the jitter becomes large, the bit error rate BER (Bit Error Rate) is deteriorated, and the probability of erroneous provisional determination is increased. If the provisional determination is wrong, the equalization error signal becomes abnormal, so that the LMS operation itself also becomes abnormal. Therefore, an appropriate adaptive equalization coefficient cannot be calculated, and PR equalization cannot be performed accurately. This deteriorates the bit error rate of the binarized data after Viterbi decoding.

  An object of the present invention is to obtain a provisional judgment value when an accurate equalization error is obtained and an FIR filter coefficient is adaptively controlled even in an asymmetry reproduction waveform or a noisy environment. It is to output accurately. Thereby, desired PR characteristics with higher accuracy can be obtained.

The present invention includes a waveform equalizer that equalizes a waveform of a reproduction signal from a recording medium, and a decoder that generates binary data of the reproduction signal based on the waveform equalized by the waveform equalizer. A PRML detector provided, wherein the decoder outputs a temporary data string which is data before or after the binarized data is obtained, and the waveform equalizer propagates the reproduction signal. A delay element to delay, a plurality of multipliers for multiplying each of the reproduction signal and the reproduction signal delayed by the delay element by a predetermined coefficient, and an adder for adding the outputs of the plurality of multipliers, etc. And a target value determiner for determining a target value to be equalized based on the temporary data sequence output from the decoder, an output from the adder of the equalizer, and a target value determiner. And calculating the predetermined coefficient based on the target value. A coefficient adaptive controller that adaptively updates the predetermined coefficient to each of a plurality of multipliers, while the decoder has a path memory that forms a plurality of data paths, and outputs the equalizer When the plurality of data paths in the path memory converge, the binarized data obtained by the converged data path is output, and the plurality of data paths are output in the middle of the data path in the path memory. If the signal does not converge, a merge check signal indicating that the signal does not converge is output, and the coefficient adaptive controller stops updating the calculated predetermined coefficient based on the merge check signal output from the path memory. Or a PRML detector that initializes the coefficients. This achieves the above object.

  According to the present invention, by switching the equalization characteristic in the waveform equalizer between the mark side and the space side according to the amount of asymmetry, the shift and dispersion at the detection points are suppressed, and the performance of the PRML method is improved. Can do. Furthermore, by providing a coefficient learning circuit, an appropriate equalization coefficient can be learned and determined even when there is asymmetry. By using the waveform equalizer of the present invention, errors in data decoding can be kept low in PRML signal processing for optical disks such as DVD and MO, and magnetic disks such as HDD.

  According to the present invention, provisional determination information for determining the PR equalization target is extracted from the Viterbi decoder. Thereby, the error rate of provisional determination can be reduced. As a result, by determining the target value from the provisional determination information based on the state transition rule of the PR method, an accurate equalization error can be obtained, and good convergence characteristics can be obtained. That is, errors during data decoding can be kept low. Further, according to the present invention, it is possible to prevent deterioration of the performance of the loop of the feedback system and avoid an increase in delay by detecting whether or not the merge is performed in the path memory of the Viterbi decoder.

  Embodiments 1 and 2 of the present invention will be described below with reference to the accompanying drawings. In the first embodiment, the error rate after PRML processing is also applied to an asymmetry waveform of a reproduction signal caused by asymmetry between pits provided on an optical disc and non-pits (for example, a space between pits). A waveform equalizer that can be greatly improved will be described. In the second embodiment, the provisional judgment value necessary for adaptive control of the equalization coefficient (tap) of the FIR filter can be accurately obtained even in a noisy environment. A PRML detector that can accurately obtain an equalization error signal representing a difference from a later digital reproduction signal value will be described.

(Embodiment 1)
FIG. 1 is a block diagram showing a general configuration of an information reproducing apparatus 1 that performs PRML (Partial Response Maximum Likelihood) signal processing. The signal processing of the PRML method is a reproduction that includes a data error by actively utilizing the waveform equalization technique for correcting the reproduction distortion generated when reproducing information and the redundancy of the equalization waveform itself. This is a technique combined with a signal processing technique for selecting the most probable data series from the signal. Here, Viterbi decoding is used for the probabilistic estimation for determining “most probable”. In the following description, an example in which PRML system signal processing is performed on a reproduction signal from an optical disk such as a DVD (Digital Versatile Disc) will be described. However, the reproduction signal from a magnetic disk such as an HDD (hard disk drive) will be described. Even available.

  The information reproducing apparatus 1 includes an optical pickup 3, a front end processor (FEP) 4, an analog / digital (A / D) converter 5, a waveform equalizer 11, and a maximum likelihood decoder 6. It has. The optical pickup 3 irradiates a laser on the optical disk 2 on which information is recorded, detects the intensity of light reflected from the optical disk 2, and outputs an electrical reproduction signal. The FEP 4 amplifies the read reproduction signal and adjusts its gain. The FEP 4 further performs an unnecessary high-frequency noise component removal process and a necessary signal band enhancement process. The output signal from the FEP 4 is converted into a digital signal by the A / D converter 5 and input to the waveform equalizer 11. The waveform equalizer 11 equalizes the digital signal to a preset PR characteristic. The maximum likelihood decoder 6 decodes the signal equalized to the PR characteristic and outputs it as reproduced data. In the present specification, the maximum likelihood decoder 6 is also referred to as a Viterbi decoder. When the waveform equalizer 11 performs PR equalization, the waveform equalizer 11 and the maximum likelihood decoder 6 are collectively referred to as a PRML detector.

  Information is recorded on the optical disc 2 as pits or marks. Assume that the pits are formed in so-called asymmetry. That is, it is assumed that the pits and the space between the pits are not formed with exactly 3T and 5T lengths when the detection window (window) width is the reference length T, for example. See (a) or (c) of FIG. 18 for specific examples of asymmetry.

  FIG. 2 is a block diagram showing a specific configuration of the waveform equalizer 11. The waveform equalizer 11 multiplies the delay elements 12 connected in series, equalization coefficients (coefficients A to E) for realizing desired characteristics, and the output signals of the delay elements 12 by the respective equalization coefficients. A plurality of multipliers 13 and an adder 14 for adding each multiplier output signal. The delay amount of the delay element 12 is a parameter that determines the cutoff frequency for the input signal X from the A / D converter 5 (FIG. 1), and may be adjusted appropriately. The number of delay elements 12 may be inserted in accordance with the number of equalization coefficients (taps) that realize the desired equalization. In the example shown in FIG. 2, since it is a 5-tap filter, four delay elements are inserted. The number of taps can be changed to meet the required performance.

  The waveform equalizer 11 further includes an asymmetry detector 15, a polarity discriminator 16, and a coefficient C selector 17. The asymmetry detector 15 calculates an asymmetry amount from the input signal X. The asymmetry amount is the ratio (B / A) of the deviation amount B from the center of the signal waveform to the entire amplitude A of the input signal X. For example, when the overall amplitude A is 1, if the deviation B from the center is 0.241, the asymmetry amount is 24.1%. The polarity discriminator 16 discriminates the polarity of the input signal X. “Determination of the polarity of the input signal X” is to determine the mark side and the space side based on the input signal X. For example, the polarity may be determined by “0” or “1” of the most significant bit (MSB) of the input signal X. The coefficient C selector 17 calculates the mark-side coefficient C and the space-side coefficient C ′ based on the amount of asymmetry detected by the asymmetry detector 15 and the difference between the waveform of the input signal X and the target value. The coefficient C and the coefficient C ′ are switched and output according to the signal from the polarity discriminator 16. Note that the difference between the waveform of the input signal X and the target value corresponds to an equalization error in the LMS (Least-mean square) algorithm described later. A procedure for generating coefficients based on the equalization error will be described later.

  The waveform equalizer 11 of the present invention has an impulse response in which the absolute value of the center coefficient (center tap) is larger than the absolute values of the other coefficients and has a value that is substantially symmetrical about the center tap. FIG. 3 is a graph showing an example of an impulse response. Coefficients A to E are indicated by white circles. The interval between the coefficients in the horizontal axis direction (tap interval) corresponds to the delay amount of the delay element 12 (FIG. 2). The vertical axis indicates the tap value. In particular, the value of the center tap adjusts the gain of the output signal of the waveform equalizer 11 (FIG. 2), and the ratio of each tap determines the boost amount of the waveform equalizer 11 (FIG. 2).

  The waveform equalizer 11 (FIG. 2) is provided on the mark side of the optical disc (for example, the negative side centered on the reproduction signal level “0” in FIG. 9A) and the space side (for example, FIG. 9). In (A), the center tap is switched between the coefficient C and the coefficient C ′ on the positive side centered on the reproduction signal level “0”. More specifically, the waveform equalizer 11 (FIG. 2) performs equalization on the mark side and the space side by changing the gain and the boost amount. The difference As between the value of the coefficient C and the value of the coefficient C ′ is calculated from the amount of asymmetry detected by the asymmetry detector 15 (FIG. 2). Needless to say, when the waveform equalizer 11 (FIG. 2) receives an input waveform X that is not asymmetry, the asymmetry detector 15 determines that it is not asymmetry, and the coefficient C and the coefficient C ′ have the same value. become. Therefore, the difference As is 0.

  FIG. 4 shows a histogram of the reproduction signal when the waveform of the asymmetry signal ((B) of FIG. 21) is equalized. Compared with the reproduction signal histogram (FIG. 21D) of the conventional waveform equalizer 186 (FIG. 16), it is understood that the variance is small. In this way, only the center tap value is adaptively switched on each of the mark side and the space side, and equalization is performed by changing the equalization characteristics. A small equalized waveform can be output.

  It is very important to determine the amount of change of the center tap of the waveform equalizer according to the asymmetry amount from the input signal X. In this embodiment, an adaptive waveform equalizer that automatically detects an asymmetry amount and determines an appropriate equalization coefficient on the mark side and the space side by using an LMS (Least-mean square) algorithm will be described.

  FIG. 5 is a block diagram showing a configuration of an adaptive waveform equalizer 41 that determines and updates an appropriate equalization coefficient. The adaptive waveform equalizer 41 includes a plurality of delay elements 42 connected in series, a coefficient learning circuit 45 that determines equalization coefficients (coefficients A to E) that realize desired PR characteristics, and each delay element 42. A plurality of multipliers 43 for multiplying the output signal by an equalization coefficient, and an adder 44 for adding each multiplier output signal are provided. The functions and operations of the delay element 42, the coefficients A to E, the multiplier 43, and the adder 44 are the same as those of the delay element 12, the coefficients A to E, the multiplier 13, and the waveform equalizer 11 (FIG. 2). Since it is the same as the adder 14, its description is omitted.

FIG. 6 is a block diagram showing a configuration of the coefficient learning circuit 45. The coefficient learning circuit 45 includes an error signal detection unit 51, a PR equalization teacher signal generation unit 52, a correlation detection unit 53, a loop gain setting unit 54, a coefficient calculation unit 55, a polarity determination circuit 56, and a recovery circuit. 57. Each component of the coefficient learning circuit 45 is configured based on the above-described LMS equalization coefficient setting formula (formula (1)). In other words,
w (n (T + 1)) = w (nT) + A · e (nT) · x (nT) (Formula 1)
(However, T = 0, 1, 2, 3, ...)
w (nT) is a current coefficient, w (n (T + 1) is a coefficient to be updated, A is a tap gain, e (nT) is an equalization error, x (nT) is an FIR filter input signal, and n is This parameter selects the coefficient update cycle.

  First, the error signal detection unit 51 detects an error between the output signal Y of the FIR filter 46 and the signal from the PR equalization teacher signal generation unit 52 that outputs the PR equalization teacher signal. The teacher signal is a target signal for PR equalization. This error signal corresponds to the above-described equalization error e (nT) of (Equation 1). The correlation detection unit 53 detects the correlation between the error signal e (nT) and the input signal X. The correlation is expressed as a product of two signals. Therefore, the correlation detection signal corresponds to e (nT) · x (nT) in (Equation 1). The loop gain setting unit 54 adjusts the response speed of LMS feedback control. (Equation 1) corresponds to the tap gain A. The coefficient calculation unit 55 calculates the updated equalization coefficient by adding the updated value (A · e (nT) · x (nT)) calculated in the previous block to the current equalization coefficient W (nT). To do.

  FIG. 7 is a block diagram illustrating a configuration of the coefficient calculation unit 55. The coefficient calculation unit 55 includes an adder 61, selectors 62 to 68, a coefficient update counter 69, and a register group 70 that holds the updated values of the coefficients A to C, C ′, D, and E, respectively. ing. First, the coefficient update counter 69 controls the selectors 62, 65, 66 to add the value output from the loop gain setting unit 54 and the value held in the register group 70 to each coefficient register group. 70 is updated sequentially. Since the number of bits of the counter can be determined in advance according to the design specifications, the change in the coefficient update rate can be controlled.

  The features of the invention according to this embodiment will be described below. The polarity determination circuit 56 determines the polarity based on whether the value output from the loop gain setting unit 54 is a calculated value on the mark side or a calculated value on the space side of the optical disk. The selectors 63, 64, and 67 switch the register to be updated between the mark side and the space side based on the determination result of the polarity determination circuit 56. The polarity discrimination circuit 56 can discriminate the polarity from either the input signal X or the output signal Y shown in FIG. The stage subsequent to the selector 66 has a function of outputting the calculated value held in the register to the FIR filter 46 as a tap coefficient. More specifically, there are a function for holding a value obtained by adjusting a bit width (coefficient value) and a function for holding an initial value at the initial learning stage. The polarity discrimination circuit 56 discriminates between the mark side and the space side based on the input signal X and outputs a discrimination signal. The selector 68 outputs a coefficient C when the determination signal indicates the mark side, and outputs a coefficient C ′ when the determination signal indicates the space side.

  With this configuration, it is possible to learn center taps (coefficient C and coefficient C ′) on the mark side and the space side for an asymmetry signal, and appropriate equalization is performed on each of the mark side and the space side. realizable. Even if the asymmetry is large on the mark side or on the space side, appropriate waveform equalization is possible without worrying about the polarity of the asymmetry.

  Next, the recovery circuit 57 (FIG. 6) will be described. The waveform equalizer 11 (FIG. 1) of the present embodiment has an impulse response characteristic in which the absolute value of the center tap is larger than the absolute values of the other taps and has a value close to left-right symmetry about the center tap. However, the learning convergence value of the coefficient may converge to an unexpected impulse response due to various disturbances such as defects.

  FIG. 8A is a waveform diagram showing three types of impulse responses. The three types of impulse responses are A-TAP, B-TAP, and C-TAP, respectively. On the other hand, FIG. 8B is a graph showing the amplitude frequency characteristics of the three types of impulse responses. FIG. 8B is an example using a 7-tap FIR filter. A-TAP is an impulse response in which the absolute value of the center tap is larger than the absolute values of the other taps and has a value close to left-right symmetry about the center tap. On the other hand, in both B-TAP and C-TAP, the absolute values of the two protruding taps are larger than the absolute values of the other taps, and the values of the two taps are almost the same. As is clear from FIGS. 8A and 8B, although the impulse response (FIG. 8A) is different, the amplitude frequency characteristic (FIG. 8B) shows almost the same tendency. Is understood. Specifically, in the 8-16 modulation which is a recording modulation code of the DVD standard, a standardized frequency up to about 0.16 is used. Therefore, the amplitude frequency characteristics are almost the same in any of A-TAP, B-TAP, and C-TAP. In the (1,7) RLL (Run Length Limited) modulation code, a normalized frequency up to about 0.25 is used. Also in this case, it can be said that the amplitude frequency characteristics are almost the same in any of A-TAP, B-TAP, and C-TAP. Since the waveform equalizer 11 (FIG. 1) is configured on the assumption that an impulse response having a characteristic such as A-TAP is employed, inconvenience occurs in the impulse response having a characteristic such as B-TAP and C-TAP. . Therefore, the recovery circuit 57 (FIG. 6) generates an impulse response such as B-TAP or C-TAP when a tap value corresponding to the above-described B-TAP or C-TAP tap characteristic is obtained. It is judged that it has fallen, learning is returned to the initial value, and re-learning is started.

  In the above description, the waveform equalizer 11 (FIG. 1) has an odd number of tap coefficients, and only the center tap coefficient changes the equalization characteristics using different tap values on the mark side and the space side. It was. However, the present invention is not limited to such a configuration. For example, the waveform equalizer may have an even number of tap coefficients. Also, the tap coefficient used on the mark side and the space side may not adopt a value located at the center. Further, instead of changing only one tap coefficient, a plurality of tap coefficients may be changed on the mark side and the space side.

  Further, although the case where 8-16 modulation of DVD is used as the recording modulation code has been described, the present invention is a case where another modulation code, for example, (1, 7) RLL (Run Length Limited) modulation code is used. It can also be applied to. FIG. 9A shows a histogram when the asymmetry reproduction waveform is sampled by the A / D converter 5 (FIG. 1) when the (1,7) RLL modulation code is used. This histogram also shows the reproduction signal when the phase error is detected with reference to the reproduction signal level (0) and the frequency and phase of the clock for sampling the reproduction signal are controlled, as in the present embodiment. If the reference for detecting the phase error is changed, the histograms shown in FIGS. 21A and 21B and FIG. 9A are not obtained.

  FIG. 9B shows a histogram of the output signal of the conventional waveform equalizer. The conventional waveform equalizer does not change the equalization characteristics between the mark side and the space side. According to FIG. 9B, when equalizing to PR (1, 2, 2, 1) characteristics, the output of the waveform equalizer is predicted to be divided into seven signal distributions. However, since the reproduced waveform has asymmetry, it is not distributed well in the seven signal level bands. Note that “equalization to PR (1, 2, 2, 1) characteristics” means 1 × 1 + 2 × 0 + 2 × 0 + 1 × 1 when the signal read from the disk is (1, 0, 0, 1). Is a characteristic that outputs = 2. When the width of the mark representing 1 and the space representing 0 is “2T or more”, the input signal does not include the patterns (1, 0, 1) and (0, 1, 0). Can be limited to species. As a result, the output signal from the waveform equalizer is predicted to be divided into seven signal distributions.

  On the other hand, FIG. 9C shows a histogram of the output signal of the waveform equalizer according to the present invention. As shown in FIG. 9C, the signal distribution of the output of the waveform equalizer according to the present invention is clearly divided into seven signal level bands, and the variance is small. As described above, the waveform equalizer of the present invention can improve the performance of the PRML system by suppressing the shift and dispersion at the detection point even when the (1, 7) RLL modulation code is used.

  Not only the influence of the asymmetry shown in FIG. 9A but also the case where the variance of each level of the reproduction signal becomes large due to the influence of noise and various stresses. When the variance is small, the sample value at the time of switching by the control signal from the polarity discrimination circuit 56 (FIG. 6) becomes a value close to the reproduction signal level 0 on the horizontal axis in FIG. Here, when the reproduction signal level is set to 0, the tap coefficient is multiplied by 0, and is the same value before and after switching the tap coefficient, so it is considered that there is no adverse effect. However, there are cases where the sample value at the time of switching (near the reproduction signal level 0) has a relatively large value due to various causes. In that case, the multiplication result may be greatly different before and after the tap coefficient is switched, which adversely affects waveform equalization. Therefore, it is desirable that the sample value at the time of switching by the control signal by the polarity discriminating circuit 56 (FIG. 6) is a value close to the reproduction signal level 0. Therefore, in order to avoid an adverse effect, the sample value at the time of switching by the control signal from the polarity discrimination circuit 56 (FIG. 6) may be reduced, such as 1/2, 1/4, or 1/8.

(Embodiment 2)
FIG. 10 is a block diagram showing the configuration of the PRML detector 100 according to the second embodiment. The feature of the PRML detector 100 is that the Viterbi decoder 112 outputs a PR temporary determination result. As described with reference to FIG. 19 or FIG. 20, the conventional PR temporary determination is performed based on a signal before being input to the Viterbi decoder (maximum likelihood decoder). A more accurate desired PR characteristic can be obtained by using a more accurate binary data string in the Viterbi decoder for this preliminary PR determination.

  The PRML detector 100 includes an FIR equalizer 111, a Viterbi decoder 112, a PR equalization target value determiner 113, and a coefficient adaptive controller 114. The PRML detector 100 has functions corresponding to the waveform equalizer 11 and the maximum likelihood decoder 6 of the information reproducing apparatus 1 described with reference to FIG. The FIR equalizer 111, the PR equalization target value determination unit 113, and the coefficient adaptive controller 114 are also referred to as an adaptive equalizer and correspond to the waveform equalizer 11 (FIG. 1). More specifically, the FIR equalizer 111 of the PRML detector 100 corresponds to the FIR filter 46 (FIG. 6), and the PR equalization target value determiner 113 corresponds to the error signal detection unit 51 (FIG. 6). The coefficient adaptive controller 114 mainly corresponds to the correlation detection unit 53, the loop gain setting unit 54, the coefficient calculation unit 55, and the polarity determination circuit 56.

  A digital signal after AD conversion is input to the FIR equalizer 111. The FIR equalizer 111 can equalize to a desired PR characteristic. The PR method will be described below.

  An optical disc recording / reproducing system has various low-frequency component fluctuations. When the recording density is increased, it is used up to the upper limit of the frequency band of the recording / reproducing system, and when the adjacent marks are read, the respective reproduced waveforms are likely to cause interference. If the reproduced waveform causes interference, a read error occurs. This phenomenon is called intersymbol interference. PR equalization actively uses the intersymbol interference. Thereby, meaning can be given to the data at the sampling points according to the transfer characteristics. This means that the reproduction signal from the disc can be equalized to a desired shape (characteristic).

  There are various methods for PR equalization. Therefore, it is necessary to select a method that matches the frequency characteristics of the recording medium. In the case of an optical disk, particularly a DVD, it is necessary to select a PR system that matches the modulation transfer function (MTF), which is the frequency characteristic of the optical system, and considers the modulation frequency characteristic of the recording code. The DVD uses a reproduction signal using a code word having a minimum code length of 3T, such as EFM (Eight to Fourteen Modulation) or EFM-Plus code. When the DVD playback signal is PR-equalized and the PR (a, b, b, a) method with a PR length of 4 is adopted, five signal levels (0, a, a + b, a + 2b) are used. , 2a + 2b). Therefore, the number of states of the Viterbi decoder is five. An integer is entered in “a” and “b”. Further, when a code word having a minimum code length of 2T, such as a (1, 7) RLL (Run Length Limited) code, is used for an optical disc, and PR (a, b, b) having a PR length of 4 is further used. , A), the signal level has seven values (0, a, 2a, a + b, 2b, a + 2b, 2a + 2b), and the number of states of the Viterbi decoder is seven. The larger the PR length, the higher the signal level and the number of states of the Viterbi decoder. That is, the system becomes more complicated.

  As described above, when PR equalization is performed using an adaptive algorithm, it is difficult to calculate an accurate equalization error for all equalization targets if the probability of erroneous provisional determination increases, and satisfactory convergence characteristics can be obtained. I can't. Therefore, as shown in FIG. 10, by extracting from the Viterbi decoder 12 a binarized data string to be used for provisional judgment, the provisional judgment error rate can be reduced.

  In the following, a system combining a code word with a minimum code length of 2T and the PR (a, b, b, a) method is taken as an example, and a more accurate equalization error is calculated for a desired equalization target. Then, it will be explained that satisfactory convergence characteristics can be obtained.

  FIG. 11 shows a state transition diagram of the Viterbi decoder 112 (FIG. 10) when a codeword having a minimum code length of 2T and the PR (a, b, b, a) method are combined. When a code word having a minimum code length of 2T is used, since there are no “010” and “101” patterns in the encoded sequence, the number of states is limited to 6 and the number of passes is limited to 10. When the signal level is calculated from these 6 states and 10 paths, the output for the signal sequence input “0000” is “0”, the output for the input “0001” is “a”, the output for the input “0011” is “a + b”, the input The output for “0110” is “2b”, the output for input “0111” is “a + 2b”, the output for input “1000” is “a”, the output for input “1001” is “2a”, the output for input “1100” is The output for “a + b”, the input “1110” is “a + 2b”, and the output for the input “1111” is “2a + 2b”.

  As a result, there are seven output signal levels: “0”, “a”, “a + b”, “2a”, “2b”, “a + 2b”, “2a + 2b”, and each level is the above-described PR equalization. Target value. That is, the coefficient adaptive controller 114 (FIG. 10) updates the taps of the FIR equalizer 111 (FIG. 10) so that the input signal is equalized to the equalization target value. Equalization is performed by reducing the difference (equalization error) between the output signal of the FIR equalizer 111 (FIG. 10) and the PR equalization target value.

  Next, the operation of the Viterbi decoder 112 (FIG. 10) for the above-described PR equalization method will be described. The Viterbi decoder 112 (FIG. 10) does not determine whether the input data is “0” or “1” (so-called hard decision) with a certain threshold as in the level detection method. The Viterbi decoder 112 (FIG. 10) determines the most probable data sequence (so-called soft decision) based on the past digitized data sequence.

FIG. 12 is a block diagram showing a specific configuration of the Viterbi decoder 112. The Viterbi decoder 112 generally includes a branch metric calculation circuit 151, a path metric calculation circuit 152, and a path memory 153. The branch metric calculation circuit 151 includes a signal (sample data) input from the FIR equalizer 111 (FIG. 10) for each channel clock and seven different seven inputs input from the coefficient adaptive controller 114 (FIG. 10). A branch metric that is a square error with the expected values [d0, d1, d2, d3, d4, d5, d6] is calculated. These seven expected values correspond to the signal levels of “0”, “a”, “a + b”, “2a”, “2b”, “a + 2b”, “2a + 2b”, respectively. Specifically, the branch metric calculation circuit 151 calculates the branch metric BM _k (i) according to the following Expression 2.

BM _k (i) = (y _k −di) ² (Formula 2)
Here, y _k is a signal (sample data) input from the FIR equalizer 111 (FIG. 10), and di (i = 0, 1,..., 6) is seven expected values [d0, d1. , D2, d3, d4, d5, d6].

  Next, the path metric calculation circuit 152 cumulatively adds the branch metrics for each channel clock to calculate a path metric. Specifically, the path metric calculation circuit 152 calculates a path metric according to the following Equation 3.

(Formula 3)
PM _k ^S0 = min [PM _k−1 ^S0 + BM _k (0), PM _k−1 ^S5 + BM _k (1)]
PM _k ^S1 = min [PM _k−1 ^S0 + BM _k (1), PM _k−1 ^S5 + BM _k (2)]
PM _k ^S2 = PM _k−1 ^S1 + BM _k (3)
PM _k ^S3 = min [PM _k-1 ^S3 + BM _k (6), PM _k-1 ^S2 + BM _k (5)]
PM _k ^S4 = min [PM _k-1 ^S3 + BM _k (5), PM _k-1 ^S2 + BM _k (4)]
PM _k ^S5 = PM _k-1 ^S4 + BM _k (3)

  In Equation 3, “min” is a mathematical symbol, and for example, min [a, b] represents the smaller one of a and b (when a = b, either one).

  Then, the path metric calculation circuit 152 calculates a signal [sel0, sel1, sel2, sel3] for selecting the most probable data series based on the equations 4 to 7 with the smallest path metric. And output to the path memory 153.

(Formula 4)
When PM _k-1 ^S0 + BM _k (0) ≧ PM _k-1 ^S5 + BM _k (1), Sel0 = 1
When PM _k-1 ^S0 + BM _k (0) <PM _k-1 ^S5 + BM _k (1), Sel0 = 0
(Formula 5)
When PM _k−1 ^S0 + BM _k (1) ≧ PM _k−1 ^S5 + BM _k (2), Sel1 = 1
When PM _k−1 ^S0 + BM _k (1) <PM _k−1 ^S5 + BM _k (2), Sel1 = 0
(Formula 6)
When PM _k−1 ^S3 + BM _k (6) ≧ PM _k−1 ^S2 + BM _k (5), Sel2 = 1
When PM _k-1 ^S3 + BM _k (6) <PM _k-1 ^S2 + BM _k (5), Sel2 = 0
(Formula 7)
When PM _k−1 ^S3 + BM _k (5) ≧ PM _k−1 ^S2 + BM _k (4), Sel3 = 1
When PM _k-1 ^S3 + BM _k (5) <PM _k-1 ^S2 + BM _k (4), Sel3 = 0

  The path memory 153 stores a predetermined candidate string and outputs a data string according to the selection signals [sel0, sel1, sel2, sel3] received from the path metric calculation circuit 152. If the memory length of the path memory 153 for storing the data string is increased, the probability of being correctly selected increases, but conversely if it is too long, the circuit scale increases. Therefore, the probability of correct selection and circuit scale are in a trade-off relationship, and are determined by comparing performance and circuit scale. Further, in the present embodiment, the path memory 153 outputs a temporary determination data series from the middle thereof. The outputted temporary determination data series is used as a temporary determination value for determining the PR equalization target value.

  FIG. 13 is a circuit diagram showing a detailed configuration of the path memory 153 (FIG. 12). The path memory 153 includes a plurality of flip-flops FF and a selector. Six flip-flops FF, which are state registers, are arranged in the vertical direction in the drawing, and the number “6” corresponds to the number of states. The horizontal direction corresponds to the memory length of the path memory 153. A set of four selectors and six flip-flops FF arranged in the vertical direction in the figure constitutes one stage. The path memory 153 (FIG. 12) is composed of 20 to 30 stages. The path memory 153 (FIG. 12) receives the selection signals sel0, sel1, sel2, and sel3 from the path metric calculation circuit 152 (FIG. 12), and data “0” input to the FF based on the received selection signals. Alternatively, “1” is selected. In the figure, [011101] is input to the leftmost flip-flop FF as an initial value in order from the top. The selection signal is controlled to select the most probable path. As a result, the paths are unified, and the output of the flip-flop FF of each stage becomes the same for a certain path memory length. That is, in the final stage, the output of every flip-flop FF has the same value. The final output is output from the Viterbi decoder 112 as a Viterbi detection output.

  The path memory length for outputting the temporary judgment value series must be appropriately selected according to the combination of the code word to be used and the PR method. Specifically, it is necessary to select a length at which the error rate does not deteriorate significantly compared to the final stage of the path memory in the Viterbi decoder. However, if the path memory length for outputting the temporary judgment value series is too long, the delay of the feedback loop until the tap coefficient is updated increases. Feedback loop delays sometimes degrade overall system performance. Therefore, in view of these two points, it is necessary to appropriately select a path / memory length for temporary determination output.

  Hereinafter, a method for facilitating recovery when the performance of the loop in the feedback system is degraded or when there is a risk of degradation will be described. According to this method, even when the error rate of the provisional decision sequence from the Viterbi decoder 112 (FIG. 10) in the present invention increases, the PRML detector 100 does not operate unstablely.

  FIG. 14 is a block diagram showing a detailed configuration for performing a provisional determination output (FIG. 13) in the path memory 153 (FIG. 12) of the Viterbi decoder 112. As already described, in the Viterbi decoder 112 (FIG. 12), if the most probable path is selected, the path is unified. That is, the output of the flip-flop FF converges to the same value in a certain flip-flop FF (status register) before the propagation through the path memory 153 (FIG. 12) is completed. This is called “merge”. However, there are cases where the paths are not unified, that is, they do not converge even though the most probable path is selected. At this time, the flip-flop FF keeps a plurality of candidate paths. This is called "do not merge". When merging is not performed, if the flip-flop FF continues to propagate the output, there is a high possibility that the provisional decision output and the final output (Viterbi detection output) of the Viterbi decoder 112 (FIG. 12) will be erroneous.

  Therefore, in this embodiment, a merge check signal (Merge Check signal) indicating whether or not merging has been performed is output. FIG. 14 is a diagram illustrating a circuit that outputs a merge check signal, which is formed using two NOR circuits and an AND circuit. The outputs of the six flip-flops FF at a predetermined stage are input to the first NOR circuit and the AND circuit, respectively, and the output is input to the second NOR circuit. The merge check signal is obtained as an output from the second NOR circuit. The merge check signal is at a low level when merged, and is at a high level when not merged.

  As shown in FIG. 10, the coefficient adaptive controller 114 (FIG. 10) may determine whether to feed back the temporary determination sequence using the merge check signal. For example, when the merge check signal is high level or the number of times of high level in a certain channel clock interval exceeds a predetermined value, the coefficient adaptive controller 114 (FIG. 10) stops updating the tap coefficient. Alternatively, the tap coefficient may be reset (initialized) to a predetermined initial value. Further, switching may be made so as to return to the conventional feedforward processing (FIG. 19). Furthermore, in this case, the binarized data output from the phase comparator 222 (FIG. 19) may be output as the final binarized data as it is so as not to perform PRML detection. Or you may switch to the processing method (FIG. 20) in which a feedback delay becomes smaller. By changing the circuit to be used and the output in accordance with the merge check signal, further fail-safe measures can be taken.

  Referring to FIG. 10 again, how the PR equalization target value determiner 13 determines a desired PR target value based on the temporary determination output of the Viterbi decoder 112 will be described. Here, the PR (a, b, b, a) method described above is taken as an example, and the PR equalization target value determiner 13 includes a code word having a minimum code length of 2T and PR (a, b, b, a). Assume that the PR target value is determined based on the state transition diagram (FIG. 11) determined by the method.

More specifically, the PR equalization target value determiner 113 includes a 4-channel bit table. The value of each channel bit is a provisional determination output value from the Viterbi decoder 12. The table defines the correspondence between input values and output values based on the state transition diagram (FIG. 11). That is, the PR target value for the case of “0000” is “0”,
The PR target value for “0001” is “a”,
The PR target value for “0011” is “a + b”,
The PR target value for “0110” is “2b”,
The PR target value for “0111” is “a + 2b”,
The PR target value for “1000” is “a”,
The PR target value for the case of “1001” is “2a”,
The PR target value for the case of “1100” is “a + b”,
The PR target value for “1110” is defined as “a + 2b”, and the PR target value for “1111” is defined as “2a + 2b”.

FIG. 15 is a diagram for explaining the output of the FIR equalizer 111 (FIG. 1) and the procedure for determining the PR equalization target value. The output of the FIR equalizer 111 (FIG. 1) is a signal waveform when a 5T mark, a 2T space, and a 3T mark are read, and sampling values for each channel clock are yk [0] to yk [14]. . On the other hand, the provisional determination output from the Viterbi decoder 112 (FIG. 10) obtained based on the output of the FIR equalizer 111 (FIG. 1) is “00111110011100”. According to the above table and the provisional determination output, the PR equalization target value determination unit 113 (FIG. 10)
(1) The PR target value for “0011” in the first to fourth bits is “a + b”,
(2) The PR target value for “0111” of the second to fifth bits is “a + 2b”,
(3) The PR target value for “1111” in the third to sixth bits is “2a + 2b”.
(4) The PR target value for “1111” in the 4th to 7th bits is “2a + 2b”,
(5) It is determined as “a + 2b” in the case of “1110” of the fifth to eighth bits.

  The PR equalization target value determiner 113 (FIG. 10) determines the PR target value of (1) as the target value for the FIR equalizer output yk [2]. Further, the PR equalization target value determiner 113 (FIG. 10) determines the PR target value of (2) as the target value for yk [3]. Similarly, the PR target value of (3) is set as the target value for yk [4], the PR target value of (4) is set as the target value for yk [5], and the PR target value of (5) is set as the target value for yk [6]. Using the target value as the target value for yk [7], the PR target value of (5) is determined.

  The coefficient adaptive controller 114 (FIG. 10) taps the FIR equalizer 111 (FIG. 10) so that the input signal is equalized to the equalization target value, that is, the equalization error becomes smaller. Update. The equalization error can be obtained from the difference between the PR equalization target value and the output value of the FIR equalizer 111 (FIG. 10) corresponding to the PR equalization target value.

  When a sequence that does not conform to the state transition rule (FIG. 11) is input during the PR equalization target value determination by the PR equalization target value determiner 113 (FIG. 10), an error in the provisional determination sequence is clearly detected. Can be determined. In this case, the PR equalization target value determiner 113 (FIG. 10) causes the coefficient adaptive controller 114 (FIG. 10) to stop updating the tap coefficients of the FIR equalizer 111 (FIG. 10). By canceling the updating of the tap coefficient, an erroneous tap update can be avoided.

  The first and second embodiments of the present invention have been described above. The first embodiment reduces errors in data decoding caused by asymmetry of the physical shape of the mark on the recording medium. On the other hand, the second embodiment improves the accuracy of provisional determination when adaptively controlling the coefficients of the FIR equalizer, and reduces errors during data decoding. Since the inventions of the first and second embodiments aim to reduce errors due to different causes, they can be combined. Specifically, the asymmetry detector 15, the polarity discriminator 16, and the coefficient C selector 17 of FIG. 2 may be incorporated into the FIR equalizer 111 of FIG. Thereby, the effects of both Embodiments 1 and 2 can be obtained, and errors during data decoding can be further reduced.

  The present invention can be used for a waveform equalizer and a PRML detector.

It is a block diagram which shows the general structure of the information reproducing | regenerating apparatus which performs the signal processing of a PRML system. It is a block diagram which shows the specific structure of a waveform equalizer. It is a graph which shows the example of an impulse response. The histogram of the reproduction signal when the waveform of an asymmetry signal is equalized is shown. It is a block diagram which shows the structure of the adaptive waveform equalizer which determines and updates an appropriate equalization coefficient. It is a block diagram which shows the structure of a coefficient learning circuit. It is a block diagram which shows the structure of a coefficient calculating part. (A) is a wave form diagram which shows three types of impulse responses. (B) is a graph showing the amplitude frequency characteristics of three types of impulse responses. (A) shows a histogram when an asymmetry reproduction waveform is sampled by an A / D converter when a (1, 7) RLL modulation code is used. (B) shows the histogram of the output signal of the conventional waveform equalizer. (C) shows a histogram of the output signal of the waveform equalizer according to the present invention. FIG. 5 is a block diagram showing a configuration of a PRML detector according to a second embodiment. The state transition diagram of a Viterbi decoder when a codeword having a minimum code length of 2T and a PR (a, b, b, a) method is combined is shown. It is a block diagram which shows the specific structure of a Viterbi decoder. 3 is a circuit showing a detailed configuration of a path memory. It is a block diagram which shows the detailed structure which performs temporary determination output in the path memory of a Viterbi decoder. It is a figure explaining the output of a FIR equalizer, and the determination procedure of PR equalization target value. It is a block diagram which shows the general structure of the information reproduction apparatus using a PRML system. It is a block diagram which shows the example of a structure of a waveform equalizer. It is a figure which shows the model of simple asymmetry. It is a block diagram which shows the structure of a PRML detector. It is a block diagram which shows the structure of a PRML detector. (A) shows a histogram of a reproduction signal that is not asymmetry. (B) shows a histogram of an asymmetry reproduction signal. (C) shows a histogram of the output signal when the waveform equalizer performs PR equalization on a reproduction signal that is not asymmetry. (D) shows a histogram of the equalizer output signal when the asymmetry reproduction waveform is PR-equalized. It is a graph which shows the frequency characteristic of the reproduction | regeneration waveform based on the histogram of the asymmetry reproduction | regeneration waveform of (B) of FIG.

Explanation of symbols

1 Information playback device,
2 optical discs,
3 Optical pickup,
4 front-end processor,
5 A / D converter,
6 Maximum likelihood decoder,
11 Waveform equalizer,
15 Asymmetry detector,
16 polarity discriminator,
17 coefficient C selector,
45 coefficient learning circuit,
63, 64, 67, 68 selector,
70 registers,
111 FIR equalizer 111,
112 Viterbi decoder 112,
113 PR equalization target value determiner,
114 coefficient adaptive controller,
151 branch metric arithmetic circuit,
152 path metric arithmetic circuit,
153 path memory

Claims (1)

PRML detection comprising: a waveform equalizer that equalizes the waveform of a reproduction signal from a recording medium; and a decoder that generates binary data of the reproduction signal based on the waveform equalized by the waveform equalizer A vessel,
The decoder outputs a temporary data string which is data before or after the binarized data is obtained,
Waveform equalizer is
A delay element for delaying propagation of the reproduction signal, a plurality of multipliers for multiplying each of the reproduction signal and the reproduction signal delayed by the delay element by a predetermined coefficient, and outputs of the plurality of multipliers are added. An equalizer having an adder;
A target value determiner for determining a target value to be equalized based on the temporary data string output from the decoder;
The predetermined coefficient is calculated based on the output from the adder of the equalizer and the target value determined by the target value determiner, and the calculated predetermined coefficient is applied to each of the plurality of multipliers. while Ru and a coefficient adaptation controller for updating,
The decoder has a path memory constituting a plurality of data paths, and when the plurality of data paths of the path memory converge based on the output of the equalizer, the decoder obtains the converged data path When binarized data is output and the plurality of data paths do not converge in the middle of the data path of the path memory, a merge check signal indicating that the data paths do not converge is output.
The coefficient adaptive controller stops updating the predetermined coefficient calculated or initializes the coefficient based on the merge check signal output from the path memory.
PRML detector.

Images