JP2003085764A - Waveform equalizer and prml detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an accurate equalization error and to accurately output a temporary decision value at the time of adaptive control of the coefficient of an FIR filter, even in the case of an asymmetrical reproduced waveform or even in a noise environment. SOLUTION: A waveform equalizer for equalizing the waveform of a reproduced signal obtained by reproducing a mark and a non-mark recorded on a recording medium is provided with a detection part which detects asymmetry of the reproduced signal, which is caused by physical shapes of the mark and the non-mark, and outputs a detection signal representative of the extent of asymmetry, a discrimination part which discriminates the mark and the non- mark on the basis of the reproduced signal to output a discrimination signal, and a selection part which calculates a first coefficient to be multiplied by the reproduced signal obtained by reproducing the mark and a second coefficient different from the first coefficient, which is to be multiplied by the reproduced signal obtained by reproducing the non-mark, on the basis of the detection signal outputted from the detection part and selects the first or second coefficient on the basis of the discrimination signal outputted from the discrimination part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for equalizing a waveform of a signal read from a recording medium such as an optical disc.

[0002]

2. Description of the Related Art In an information reproducing apparatus for reproducing information recorded on a recording medium such as an optical disk, conventionally, if the waveform level of a signal is larger than a predetermined value, it is "1".
A slice method of determining “0” has been adopted. However, with this method, it is difficult to reproduce data with high reliability on a recording medium having a significantly improved recording density. Therefore, in recent years, PRML (Partial Responses) capable of reproducing data with high reliability.
The e-Maximum Likelihood method is drawing attention. The PRML system is a technique used as a high-density signal processing technique for HDDs (hard disk drives), camera-integrated VTRs for digital recording, and recording media such as recordable and rewritable optical disks. This is because as the recording density increases, it becomes more necessary to restore correct data from a reproduction signal having a low S / N (signal to noise) or a non-linear reproduction signal.

FIG. 16 is a block diagram showing a general structure of an information reproducing apparatus 181 using the PRML system. First, the optical pickup 183 irradiates the optical disc 182 with laser light. The information reproducing device 181 detects the intensity of the reflected light, reads the information (data) recorded on the optical disc 182, converts it into an electric signal, and then the FEP.
(Front End Processor) 184. The FEP 184 amplifies the read electrical signal and adjusts the gain. The FEP 184 further performs a process of removing unnecessary high-frequency noise components and a process of enhancing a necessary signal band. The output signal from FEP184 is A / D
It is converted into a digital signal by the (analog / digital) converter 185 and input to the waveform equalizer 186.
The waveform equalizer 186 waveform-equalizes the digital signal to a preset PR characteristic. The maximum likelihood decoder 187 is
The signal waveform-equalized to the PR characteristic is decoded and output as reproduced data.

Waveform equalizer 186 of information reproducing apparatus 181
Is the desired PR characteristic, eg PR (3,4,4,3)
A waveform is generated so that it has characteristics. FIG. 17 is a block diagram showing an example of the configuration of the waveform equalizer 186. The waveform equalizer 186 is a transversal filter or FI.
R (Finite Impulse Responses)
e) It is called a filter. The waveform equalizer 186 generally includes a plurality of delay elements 192, a plurality of equalization coefficients (coefficients A to E) that realize desired PR characteristics, and a delay element 192.
Of multipliers 193 that multiplies the output of the above by the equalization coefficient, and an adder 194 that adds the outputs of the plurality of multipliers 193.

In order to accurately equalize the desired PR characteristics,
A technique for automatically adaptively controlling the equalization coefficient (tap) of the FIR filter is adopted. This technique is effective against various stresses during reproduction (tilt of disc, defocus of laser light, off-track of optical head, etc.). As an adaptive control algorithm, LMS (Leas
t-mean square) algorithm, Norm
aligned LMS algorithm, RLS (Recu
Many algorithms are known, such as the rsive least square algorithm, the projection algorithm, and the neural network algorithm.

Here, the adaptive waveform equalizer using the LMS algorithm will be briefly described. In this algorithm,
Since the adaptive equalization coefficient is calculated, a temporary judgment value used in LMS is required. This LMS algorithm is a feedback operation that minimizes the squared error between the "desired response" and the "transmission path response". This "desired response" is P
R equalization target value. The “response of the transmission line” is a digital reproduction signal that is input from the FIR filter and equalized to the PR frequency characteristic. In the LMS algorithm, F
A signal representing the difference between the temporary judgment value and the digital reproduction signal value after equalization, which is obtained in the block for adaptively controlling the coefficient of the IR filter, is called an equalization error signal.

The block for adaptively controlling the coefficient of the FIR filter is designed so as to minimize the square value of the equalization error signal.
The equalization coefficient of the IR filter is updated at any time. This is called adaptive equalization. The equation for setting the equalization coefficient of LMS is shown in the following equation (for example, S. Heikin, Introduction to Adaptive Filter, Hyundai Engineering Co.).

W (n (T + 1)) = w (nT) + A.e (nT) .x (nT) (Equation 1) (where T = 0, 1, 2, 3, ...) W (nT) is Current coefficient, w (n (T + 1) is updated coefficient, A is tap gain, e (nT) is equalization error, x
(NT) is the FIR filter input signal. n is a parameter for selecting the coefficient update period. The above equation 1 updates the equalization coefficient of the FIR filter.

Here, the asymmetry of the optical disc 182 (FIG. 16) will be described. Asymmetry means that there is no symmetry between pits and non-pits on an optical disc. Information is recorded on the optical disc 182 (FIG. 16) by the arrangement and length of minute embossed portions called pits. When the reference length is T, the pit is, for example, 3T,
It has a length of 5T. The pits are arranged with a space of 3T and 5T. The pit length is exactly 3
It is preferable that it is T, 5T. However, there are some variations in the pit length. This is because, for example, the power of the recording light used for mastering the optical disc is slightly deviated, and as a result, a master master disc having pit length variations is manufactured. If the recording power is not appropriate, each pit formed will be slightly longer or shorter than the standard value by the same amount before and after the lengthwise direction. That is, there is no symmetry between pits and non-pits. This is asymmetry. Hereinafter, in this specification, the relationship between pits and non-pits in an optical disc is
It is assumed that the relationship between the recorded portion (mark) and the unrecorded portion (space) of a hard disk is the same. It should be noted that "pit" and "non-pit" for the read-only optical disc
With respect to a recordable optical disc, a part where information is recorded (that is, a part where a laser is strongly irradiated) is sometimes called a “mark” and a space between marks is called a “space”. In this specification, "pit",
"Mark" is synonymous. Also, "non-pit",
"Space" and "non-mark" are synonymous. Also,
A signal when an optical disc having no symmetry between pits and non-pits (that is, asymmetry) is reproduced is called an asymmetric signal, and a signal when an optical disc which is not asymmetry is reproduced is called a symmetrical signal.

FIG. 18 is a diagram showing a simple asymmetry model. FIG. 18 shows a pit arrangement of 3T marks, 3T spaces, 5T marks, and 5T spaces. Here, the reference length is 1, and the detection window width is adopted. FIG. 18B shows a standard pit arrangement, and both marks and spaces are symmetrical. On the other hand, in FIG. 18A, the mark width is uniform and shortened by the length x. Further, in FIG. 18C, the mark width is uniform and is increased by the length y. In both cases, no symmetry is observed in either the mark or the space. Since this asymmetry also occurs due to the wavelength variation of the laser used, it is generally difficult to adjust and maintain the symmetry between pits and non-pits during recording.

Next, a specific hardware configuration and procedure for binarizing the analog data signal (reproduction signal) read from the optical disk will be described. Figure 19 shows PR
3 is a block diagram showing a configuration of an ML detector 210. FIG. PR
The ML detector 210 performs adaptive equalization and updates the equalization coefficient of the FIR filter as needed. First, the PRML detector 2
The A / D converter 221 of 10 converts the reproduction signal from an analog signal to a digital signal. The phase comparator 222 is
Binarized data is generated based on a certain threshold. Then P
The R provisional determiner 223 receives the binarized data. The PR provisional determiner 223 provisionally determines the target value of the PR method and outputs it to the coefficient adaptive controller 224. The target value of the PR system can be determined based on the amplitude zero-cross information obtained by the phase comparator 222 (for example, ITE Technical Report Vol.24, No.46, PP.13-1).
8 MMS2000-14 (Jul.2000)). Next, the coefficient adaptive controller 224 uses the adaptive algorithm described above to
The equalization coefficient (tap) of the R equalizer 225 is updated. Then, the Viterbi decoder 226 converts the waveform equalized into a predetermined PR in the FIR equalizer 225 into binary data.

The clock used in the A / D converter 21 is detected by the phase comparator 22 from the output of the A / D converter 21, and based on the detected phase error, a loop filter and a digital signal are output. DA to convert analog to analog signal
C and the voltage control oscillator VCO (both not shown) are generated by performing a predetermined process.

FIG. 20 is a block diagram showing the configuration of the PRML detector 220. The PRML detector 220 uses the output of the FIR equalizer, for example, PR (1,1), as described in Japanese Patent Laid-Open No. 2000-123487.
The judgment value by equalization is output, and the FI is used by using the judgment value.
In the R equalizer, a target value for PR (a, b, b, a) equalization is calculated. The A / D converter 231 converts a reproduction signal from an analog signal into a digital signal. FIR equalizer 3
2 performs a predetermined PR equalization on the digital signal.
The PR provisional determiner 233 provisionally determines the target value of the PR method using the binarized data of the output of the FIR equalizer 32, and outputs it to the coefficient adaptive controller 234. The coefficient adaptive controller 234 uses the tentative judgment value to calculate the FIR equalizer 232.
Update the tap. The PRML detector 220 can reduce the probability that a determination error will occur by reducing the determination threshold.

[0014]

Conventionally, the following (1) has been used.
Due to the problems shown in (2) and (2), it was not possible to obtain an appropriately binarized reproduction signal. That is,
(1) If the pits and non-pits of the optical disc do not have symmetry (that is, asymmetry), the performance of the PRML system deteriorates. That is, the information reproducing apparatus 181 using the conventional PRML system causes an error due to the reproduction signal of asymmetry.

The above (1) is explained as follows. 21A and 21B show the information reproducing device 81.
16 shows a histogram of the output signal of the A / D converter 185 in FIG. The horizontal axis shows the level of the playback signal,
The vertical axis represents the frequency of the signal level. This waveform example is for DVD
The 8-16 modulation used in the (Digital Versatile Disc) standard is used. That is,
The reproduction waveform has a mark length and space length of 3T to 1
The waveform is 4T (including sync code).

The center of the reproduction signal level (for example, when the number of effective bits of the A / D converter is 7, 0 to 1 representable)
A phase error is detected based on the median value of 64 (40 h) of 28, and the frequency and phase of the clock for sampling the reproduction signal are controlled. In such control, the histogram is divided into five distributions. This is because when the PRML system has a PR coefficient like the PR (a, b, b, a) ML system, the number of signal levels (signal distribution) becomes five (a and b are , With a positive coefficient). The waveform equalizer 86 controls the phase of the clock to facilitate PR equalization.

FIG. 21A shows a histogram of a reproduced signal which is not asymmetrical, and FIG. 21B shows a histogram of asymmetrical reproduced signal. In FIG. 21C, the waveform equalizer 86 performs PR equalization (here, PR) on the reproduction signal that is not asymmetry (FIG. 21A).
The histogram of the output signal in the case of (3, 4, 4, 3) equalization) is shown. As can be seen from FIG. 21C, the variance is minimal and the levels are clearly separated.

On the other hand, FIG. 21D shows a histogram of the output signal of the equalizer in the case of PR equalizing the asymmetric reproduction waveform. As is clear from the figure, if PR equalization is performed on an asymmetric reproduction waveform, the dispersion will be expanded.
This is because PRML originally targets a symmetrical waveform for processing and automatically equalizes the waveform so that all levels are at equal intervals. That is, when an asymmetrical signal with a minimum dispersion in a predetermined unequal interval state is supplied, the signals are forcibly equalized at equal intervals and the dispersion becomes large.

FIG. 22 is a graph showing the frequency characteristic of the reproduced waveform based on the asymmetric reproduced waveform histogram of FIG. 21 (B). In addition, FIG.
The frequency characteristic of the R characteristic is also shown. In FIG. 21B, the left side from the center of the reproduction signal level is a mark, and the right side is a space. In the graph of FIG. 22, the horizontal axis represents the normalized frequency,
When the vertical axis is the gain, the characteristic on the mark side and the characteristic on the space side are different due to the influence of asymmetry. As can be easily understood, in order to equalize the reproduced waveform to a desired PR characteristic, the equalizer needs to perform equalization having different characteristics on the mark side and the space side. However, since the conventional waveform equalizer 6 performs the same equalization processing on the mark side and the space side, it is not possible to perform equalization to a desired PR characteristic with high accuracy. As a result, the variance in the output signal of the maximum likelihood decoder 6 (FIG. 16) becomes large, leading to deterioration in performance.

(2) When the adaptive equalization processing is automatically performed,
An error may occur in the result of the temporary judgment (temporary judgment value) used in the LMS. Specifically, first, FIGS.
In the system shown in FIG. 0, when the reproduced signal had relatively little noise and the signal quality was good to some extent, satisfactory convergence characteristics could be obtained. However, if the noise caused by the various stresses described above is mixed in the reproduced signal to increase the jitter, the bit error rate BER (Bit Error Rate) deteriorates, and the probability of erroneous tentative determination increases. If you make a false decision,
Since the equalization error signal becomes abnormal, the LMS operation itself becomes abnormal. Therefore, an appropriate adaptive equalization coefficient cannot be calculated,
PR equalization cannot be performed accurately. This is 2 after Viterbi decoding.
The bit error rate of the digitized data deteriorates.

An object of the present invention is to temporarily calculate an accurate equalization error and adaptively control the coefficient of an FIR filter even in an asymmetrical reproduced waveform or in a noisy environment. It is to output the judgment value accurately.
This makes it possible to obtain a desired PR characteristic with higher accuracy.

[0022]

The waveform equalizer of the present invention comprises:
A waveform equalizer for equalizing a waveform of a reproduction signal obtained by reproducing marks and non-marks recorded on a recording medium, the delay element delaying propagation of the reproduction signal, and the delay signal delayed by the reproduction signal and the delay element. A plurality of multipliers for multiplying each of the reproduction signals by a predetermined coefficient, and a detection signal indicating an asymmetry amount by detecting the asymmetry of the reproduction signal caused by the physical shapes of the mark and the non-mark. Based on the detection unit that outputs, and the reproduction signal,
A discriminator that discriminates between the mark and the non-mark and outputs a discriminant signal; a first coefficient that is multiplied by the reproduced signal that reproduces the mark based on the detection signal output from the detector; The first coefficient calculated by multiplying the reproduction signal obtained by reproducing the non-mark and calculating a second coefficient different from the first coefficient, and further calculating the first coefficient based on the determination signal output from the determination unit. And a selector for selecting one of the second coefficients, and an adder for adding the outputs of a plurality of multipliers. This achieves the above object.

The waveform equalizer may be an FIR filter, and the selection unit may change the predetermined coefficient to switch the equalization characteristic of the reproduction signal in the pit and the non-pit.

There may be an odd number of the predetermined coefficients, and the first coefficient and the second coefficient selected by the selection unit may be central coefficients.

The impulse response of the waveform equalizer is specified based on the predetermined coefficient, and the absolute value of the first coefficient and the absolute value of the second coefficient are absolute values of the other predetermined coefficients. It may be larger than the value.

The waveform equalizer may be equalized by a partial response method, which is composed of an impulse response of (a, b, b, a) type.

The waveform equalizer of the present invention is a waveform equalizer for equalizing the waveform of a reproduced signal obtained by reproducing marks and non-marks recorded on a recording medium, and a delay for delaying propagation of the reproduced signal. An element, a plurality of multipliers for multiplying each of the reproduction signal delayed by the reproduction signal and the delay element by a predetermined coefficient, and a coefficient for adaptively updating the predetermined coefficient to each of the plurality of multipliers The coefficient learning circuit includes a learning circuit and an adder that adds outputs of a plurality of multipliers, and the coefficient learning circuit includes a teacher signal generation unit that generates a teacher signal to be equalized.
Error detection for detecting an error signal representing an error between the teacher signal generated by the teacher signal generation unit and the output signal equalized by the partial response method, which is composed of the impulse response of the type (a, b, b, a) Based on the error signal detected by the error detection unit, a determination unit that outputs a determination signal by determining the mark and the non-mark based on the reproduction signal, A plurality of registers for updating and outputting the predetermined coefficient so that the root mean square of the error is minimized, the first register holding a first coefficient by which the reproduction signal obtained by reproducing the mark is multiplied. And a second register that holds the second coefficient that is different from the first coefficient and that is multiplied by the reproduction signal that reproduces the non-mark, and is output from the determination unit. A register selecting unit that selects and outputs one of the first coefficient held in the first register and the second coefficient held in the second register based on the determination signal. ing. This achieves the above object.

There are an odd number of the predetermined coefficients, and the first coefficient and the second coefficient selected by the register selection unit.
The coefficient of may be the central coefficient.

The impulse response of the waveform equalizer is specified based on the predetermined coefficient, and the absolute value of the first coefficient and the absolute value of the second coefficient are the absolute values of the other predetermined coefficients. It may be larger than the value.

The PRML detector of the present invention is based on the waveform equalizer for equalizing the waveform of the reproduced signal reproduced from the marks and non-marks recorded on the recording medium, and the waveform equalized by the waveform equalizer. And a decoder for generating binarized data of the reproduced signal, wherein the decoder outputs a temporary data string which is data before the binarized data is obtained, and a waveform The equalizer includes a delay element that delays propagation of the reproduction signal, a plurality of multipliers that multiply each of the reproduction signal and the reproduction signal delayed by the delay element by a predetermined coefficient, and a plurality of multipliers. Of the equalizer having an adder for adding the outputs of the, the target value determiner for determining the target value to be equalized based on the temporary data string output from the decoder, and the adder of the equalizer. The output and the value determined by the target value determiner Based on the target value, and a coefficient adaptation controller said predetermined coefficient is calculated and adaptively updating the calculated predetermined coefficients to each of the plurality of multipliers.
This achieves the above object.

The decoder has a path memory which constitutes a plurality of data paths, and when the plurality of data paths of the path memory have converged based on the output of the equalizer, the converged data paths You may output the binarized data obtained by.

When the plurality of data paths converge in the middle of the data path of the path memory, a merge check signal indicating convergence and the temporary data string may be output.

If the plurality of data paths do not converge in the middle of the data path of the path memory, a merge check signal indicating that the data paths do not converge may be output.

The coefficient adaptive controller may stop updating the calculated predetermined coefficient based on the merge check signal output from the path memory.

The coefficient adaptive controller may initialize the calculated predetermined coefficient based on the merge check signal output from the path memory.

The target value determiner has a table that defines the correspondence between each of the plurality of data strings and each of the plurality of target values. The target value determiner follows a predetermined state transition rule. Based on, based on the extracted data string and the table, the data string is sequentially extracted from the temporary data string,
The target value may be determined.

When the temporary data string violates the predetermined state transition rule, the target value determining unit may cause the coefficient adaptive controller to stop updating the coefficient.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments 1 and 2 of the present invention will be described below with reference to the accompanying drawings. Embodiment 1
Can significantly improve the error rate after PRML processing even for an asymmetrical waveform of a reproduction signal due to the asymmetry between pits provided on the optical disc and non-pits (for example, spaces between pits). The waveform equalizer will be described. In the second embodiment, the tentative decision value necessary for adaptively controlling the equalization coefficient (tap) of the FIR filter can be accurately obtained even in a noisy environment, whereby the tentative decision value and the equalization can be obtained. A PRML detector capable of accurately obtaining an equalization error signal representing a difference from a subsequent digital reproduction signal value will be described.

(Embodiment 1) FIG. 1 shows PRML (Pa
rial Response Maximium Li
FIG. 1 is a block diagram showing a general configuration of an information reproducing device 1 that performs signal processing of a Kelihood system. The signal processing of the PRML method is a waveform equalization technique that corrects a reproduction distortion that occurs when information is reproduced, and a reproduction that includes a data error by positively utilizing the redundancy of the equalized waveform itself. This is a technology that combines with signal processing technology that selects the most probable data sequence from the signal. Viterbi decoding is used for the probabilistic estimation for determining "most likely" here. In the following description, a DVD (Digital
An example in which PRML method signal processing is performed on a reproduction signal from an optical disc such as Versatile Disc) will be described, but the present invention can also be used for a reproduction signal from a magnetic disc such as an HDD (hard disk drive).

The information reproducing apparatus 1 comprises an optical pickup 3 and
Front End Processor (Front End Pr)
processor (FEP) 4, an analog / digital (A / D) converter 5, a waveform equalizer 11, and a maximum likelihood decoder 6. The optical pickup 3 irradiates the optical disc 2 on which information is recorded with a laser, detects the intensity of the light reflected from the optical disc 2, and outputs an electrical reproduction signal. The FEP 4 amplifies the read reproduction signal and adjusts the gain. The FEP 4 further performs a process of removing unnecessary high-frequency noise components and a process of enhancing a necessary signal band. The output signal from the FEP 4 is converted into a digital signal by the A / D converter 5 and input to the waveform equalizer 11. The waveform equalizer 11 waveform-equalizes the digital signal into a preset PR characteristic. Maximum likelihood decoder 6
Outputs a signal whose waveform is equalized to the PR characteristic and which is decoded as reproduced data. In this specification, the maximum likelihood decoder 6
Is also called a Viterbi decoder. And the waveform equalizer 1
When 1 performs PR equalization, the waveform equalizer 11 and the maximum likelihood decoder 6 are also collectively called a PRML detector.

Information is recorded on the optical disc 2 as pits or marks. The pits are supposed to be formed in so-called asymmetry. That is, it is assumed that the pits and the spaces between the pits are not accurately formed with the lengths of 3T and 5T when the detection window (window) width is the reference length T, for example. For specific examples of asymmetry, see (a) or (c) of FIG. 18.

FIG. 2 is a block diagram showing a concrete configuration of the waveform equalizer 11. The waveform equalizer 11 multiplies a plurality of delay elements 12 connected in series, an equalization coefficient (coefficients A to E) that realizes a desired characteristic, and each output signal of the delay element 12 by each equalization coefficient. And a plurality of multipliers 13 for adding the output signals of the respective multipliers. The delay amount of the delay element 12 is a parameter that determines the cutoff frequency for the input signal X from the A / D converter 5 (FIG. 1) and may be adjusted appropriately. The number of delay elements 12 depends on the number of equalization coefficients (tap) that achieves desired equalization.
Just insert it. In the example shown in FIG. 2, since it is a 5-tap filter, four delay elements are inserted. The number of taps can be changed to meet the required performance.

The waveform equalizer 11 further includes an asymmetry detector 15, a polarity discriminator 16, and a coefficient C selector 17. The asymmetry detector 15 receives the input signal X
Calculate the amount of asymmetry from. The asymmetry amount is a ratio (B / A) of the deviation amount B from the center of the signal waveform to the entire amplitude A of the input signal X. For example, when the overall amplitude A is 1, the deviation amount B from the center is 0.2
If it is 41, the amount of asymmetry is 24.1%. The polarity determiner 16 determines the polarity of the input signal X. “Determining the polarity of the input signal X” means determining the mark side and the space side based on the input signal X. For example, the polarity may be determined by the most significant bit (MSB) “0” or “1” of the input signal X. Coefficient C selector 17
Calculates the coefficient C for the mark side and the coefficient C ′ for the space side based on the asymmetry amount detected by the asymmetry detector 15 and the difference between the waveform of the input signal X and the target value, and the polarity discriminator 16 The coefficient C and the coefficient C'are switched and output according to the signal from. It should be noted that the difference between the waveform of the input signal X and the target value is determined by the LMS (Least-me
This corresponds to an equalization error in the (an square) algorithm. The procedure for generating the coefficient based on the equalization error will be described later.

The waveform equalizer 11 of the present invention produces an impulse response in which the absolute value of the center coefficient (center tap) is larger than the absolute values of the other coefficients, and the value of which is substantially symmetrical about the center tap. To have. FIG. 3 is a graph showing an example of the impulse response. Coefficients A to E are indicated by white circles.
The distance between the coefficients in the horizontal axis direction (interval between taps) corresponds to the delay amount of the delay element 12 (FIG. 2). The vertical axis represents the tap value. In particular, the value of the center tap is the waveform equalizer 11
The gain of the output signal of FIG. 2 is adjusted and the ratio of each tap determines the boost amount of the waveform equalizer 11 (FIG. 2).

The waveform equalizer 11 (FIG. 2) has a mark side (for example, a negative side around the reproduction signal level "0" in FIG. 9A) of the optical disc and a space side (for example, 9A, the center taps are switched to the coefficient C and the coefficient C ′, respectively, on the positive side around the reproduction signal level “0”). More specifically, the waveform equalizer 11 (FIG. 2) changes the gain and the boost amount,
Equalization is performed on each of the mark side and the space side.
The difference As between the value of the coefficient C and the value of the coefficient C ′ is calculated from the asymmetry amount detected by the asymmetry detector 15 (FIG. 2). Needless to say, the waveform equalizer 11 (Fig. 2)
However, when the input waveform X that is not asymmetry is received, the asymmetry detector 15 determines that it is not asymmetry, and the coefficient C and the coefficient C ′ have the same value. Therefore,
The difference As is zero.

FIG. 4 shows a histogram of a reproduced signal when the waveform of an asymmetrical signal ((B) of FIG. 21) is equalized. It can be understood that the variance is small as compared with the histogram of the reproduced signal of the conventional waveform equalizer 186 (FIG. 16) ((D) of FIG. 21). in this way,
By adaptively switching only the center tap value on each of the mark side and space side and changing the equalization characteristics to perform equalization, an equalized waveform with a small dispersion value at the detection point even for asymmetrical reproduced signals. Can be output.

According to the asymmetry amount from the input signal X,
Determining the amount of change in the center tap of the waveform equalizer is very important. Further, in the present embodiment, the LM
The amount of asymmetry is automatically detected by using the S (Least-mean square) algorithm,
An adaptive waveform equalizer that determines appropriate equalization coefficients on the mark side and the space side will be described.

FIG. 5 is a block diagram showing the configuration of the adaptive waveform equalizer 41 which determines and updates an appropriate equalization coefficient.
The adaptive waveform equalizer 41 includes a plurality of delay elements 42 connected in series and an equalization coefficient (coefficient A that realizes a desired PR characteristic).
To E), the coefficient learning circuit 45 and each delay element 42
A plurality of multipliers 43 for multiplying the output signal of
An adder 44 for adding the output signals of the multipliers is provided. The delay element 42, the coefficients A to E, the multiplier 43, and the adder 4
4 has the same function and operation as the delay element 12, the coefficients A to E, the multiplier 13, and the waveform equalizer 11 (FIG. 2) described above.
Since it is the same as the adder 14, its description is omitted.

FIG. 6 is a block diagram showing the configuration of the coefficient learning circuit 45. The coefficient learning circuit 45 includes an error signal detection unit 51, a PR equalization teacher signal generation unit 52, and a correlation detection unit 5.
3, a loop gain setting unit 54, a coefficient calculation unit 55,
A polarity determination circuit 56 and a recovery circuit 57 are provided. Each component of the coefficient learning circuit 45 is the above-mentioned LMS.
It is configured based on the equation (equation (1)) for setting the equalization coefficient of. That is, to show again, w (n (T + 1)) = w (nT) + A · e (nT) · x (nT) (Equation 1) (where T = 0, 1, 2, 3, ...) W ( nT) is the current coefficient, w (n (T + 1) is the coefficient to be updated, A is the tap gain, e (nT) is the equalization error, x
(NT) is the FIR filter input signal. n is a parameter for selecting the coefficient update period.

First, the error signal detector 51 detects an error between the output signal Y of the FIR filter 46 and the signal from the PR equalization teacher signal generator 52 which outputs the teacher signal for PR equalization. The teacher signal is a target signal for PR equalization. This error signal is the equalization error e (n
Equivalent to T). The correlation detector 53 uses the error signal e (n
The correlation between T) and the input signal X is detected. The correlation is represented by the product of two signals. Therefore, the correlation detection signal corresponds to e (nT) · x (nT) in (Equation 1). The loop gain setting unit 54 adjusts the response speed of feedback control of the LMS. In (Equation 1), it corresponds to the tap gain A. The coefficient calculation unit 55 uses the current equalization coefficient W (nT) as
Update value calculated in the previous block (Ae (nT) x
(NT)) is added to calculate the updated equalization coefficient.

FIG. 7 is a block diagram showing the configuration of the coefficient calculator 55. The coefficient calculator 55 includes an adder 61, selectors 62 to 68, a coefficient updating counter 69, and a register group 70 that holds updated values of the coefficients A to C, C ′, D, and E, respectively. ing. First, the coefficient updating counter 69 controls the selectors 62, 65, 66 to add the value output from the loop gain setting unit 54 and the value held in the register group 70, and each coefficient register group 70 are sequentially updated. Since the number of bits of this counter can be determined in advance by design specifications, it is possible to control the change of the coefficient update rate.

The features of the invention according to the present embodiment will be described below. The polarity determination circuit 56 includes a loop gain setting unit 5
The polarity is determined based on whether the value output from 4 is the calculated value on the mark side or the calculated value on the space side of the optical disc. Then, the selectors 63, 64 and 67 switch the register to be updated between the mark side and the space side based on the discrimination result of the polarity discriminating circuit 56. The polarity determining circuit 56 can determine the polarity from either the input signal X or the output signal Y in FIG. The stage subsequent to the selector 66 has a function of outputting the calculated value held in the register to the FIR filter 46 as a tap coefficient. More specifically, it has a function of holding a value obtained by adjusting a bit width (coefficient value) and a function of holding an initial value at the beginning of learning. The polarity discrimination circuit 56 discriminates between the mark side and the space side based on the input signal X and outputs a discrimination signal. The selector 68 uses the coefficient C when the discrimination signal indicates the mark side.
Is output, and the coefficient C ′ is output when the space side is indicated.

With this configuration, center taps (coefficients C and C ') can be learned on the mark side and the space side for an asymmetrical signal, and appropriate values can be learned on the mark side and the space side. Equalization can be realized. Further, even if the asymmetry is large on the mark side or large on the space side, appropriate waveform equalization can be performed without paying attention to the polarity of the asymmetry.

Next, the recovery circuit 57 (FIG. 6) will be described. In the waveform equalizer 11 (FIG. 1) of this embodiment, the absolute value of the center tap is larger than the absolute values of the other taps,
It has impulse response characteristics with values that are almost symmetrical with respect to the center tap. However, the learning convergence value of the coefficient may converge to an unexpected impulse response due to various disturbances such as a defect.

FIG. 8A is a waveform diagram showing three types of impulse responses. The three types of impulse responses are A-TAP, B-TAP, and C-TAP, respectively. On the other hand, FIG. 8B is a graph showing the amplitude frequency characteristics of the three types of impulse responses. Note that FIG. 8B is an example using a 7-tap FIR filter. A-TAP is an impulse response in which the absolute value of the center tap is larger than the absolute values of the other taps and which has a value close to left-right symmetry around the center tap. For it,
In both B-TAP and C-TAP, the absolute values of the two protruding taps are larger than the absolute values of the other taps, and the values of the two taps are almost the same. As is clear from FIGS. 8A and 8B, the impulse response (FIG.
It is understood that the amplitude frequency characteristics ((B) in FIG. 8) show almost the same tendency, although (A)) in FIG. Specifically, the recording modulation code of the DVD standard, 8−
In 16 modulation, a standardized frequency up to about 0.16 is used. Therefore, A-TAP, B-TAP, C-
The amplitude frequency characteristics are almost the same in any of the TAPs. (1,7) RLL (Run Length
In the (Limited) modulation code, the normalized frequency is 0.
Up to about 25 is used. Also in this case, A-TAP,
It can be said that the amplitude-frequency characteristics are almost the same in both B-TAP and C-TAP. The waveform equalizer 11 (FIG. 1) is A-
Since it is configured on the assumption that the impulse response having the characteristic like TAP is adopted, the impulse response having the characteristic like B-TAP or C-TAP causes a problem. Therefore,
The recovery circuit 57 (FIG. 6) includes the B-TAP,
When a tap value corresponding to the characteristics of the tap of C-TAP is obtained, it is determined that the impulse response such as B-TAP or C-TAP has fallen, the learning is returned to the initial value, and the relearning is started. To do.

In the above description, the waveform equalizer 11 (FIG. 1) has an odd number of tap coefficients, and only the center tap coefficient uses different tap values on the mark side and the space side. Was changed. However, the present invention is not limited to such a configuration. For example, you may have an even number of tap coefficients of a waveform equalizer. Further, the tap coefficients used on the mark side and the space side do not have to adopt the values located at the center. Further, instead of changing only one tap coefficient, a plurality of tap coefficients may be changed on the mark side and the space side.

Further, as the recording modulation code, the 8-
Although the case where 16 modulations are used has been described, the present invention can be applied to other modulation codes such as (1,7) RLL (Run Len).
It is also applicable when using a gth Limited) modulation code. FIG. 9A shows an asymmetrical reproduced waveform in the case of using the (1,7) RLL modulation code.
3 shows a histogram when sampled by the converter 5 (FIG. 1). This histogram also shows the reproduction signal when the phase error is detected based on the reproduction signal level (0) and the frequency and phase of the clock for sampling the reproduction signal are controlled, as in the present embodiment. When the reference for detecting the phase error is changed, (A), (B) of FIG. 21 and (A) of FIG.
It does not become the histogram shown in.

Further, FIG. 9B shows a histogram of the output signal of the conventional waveform equalizer. The conventional waveform equalizer does not change the equalization characteristics on the mark side and the space side. According to FIG. 9B, when equalizing to the PR (1,2,2,1) characteristic, the output of the waveform equalizer is predicted to be divided into seven signal distributions. However, since the reproduced waveform has asymmetry, it is not well distributed in the seven signal level bands. Note that "equalize to PR (1, 2, 2, 1) characteristic" means that the signal read from the disc is (1, 0,
0, 1), 1 × 1 + 2 × 0 + 2 × 0 + 1 × 1 =
It means the characteristic of outputting 2. When the width of the mark representing 1 and the space representing 0 is “2T or more”, the input signal does not include the patterns of (1, 0, 1) and (0, 1, 0). Can be limited to seeds. This allows
The output signal from the waveform equalizer is expected to be divided into seven signal distributions.

On the other hand, FIG. 9C shows a histogram of the output signal of the waveform equalizer according to the present invention. FIG. 9C
As shown in, the signal distribution of the output of the waveform equalizer according to the present invention is clearly divided into seven signal level bands, and the dispersion is small. As described above, the waveform equalizer of the present invention has (1,
7) Even when the RLL modulation code is used, it is possible to suppress the deviation and dispersion at the detection point and improve the performance of the PRML system.

In some cases, not only the asymmetry shown in FIG. 9A, but also noise and various stresses may increase the dispersion of each level of the reproduced signal. When the variance is small, the sample value at the time of switching by the control signal from the polarity determination circuit 56 (FIG. 6) becomes a value close to the reproduction signal level 0 on the horizontal axis of FIG. Here, when the reproduction signal level is 0, the tap coefficient is multiplied by 0, and before and after switching the tap coefficient,
Since the values are the same, it is considered that there is no adverse effect. However, there are cases where the sample value at the time of switching (around the reproduction signal level 0) has a relatively large value due to various reasons. In that case, the multiplication result may be significantly different before and after switching the tap coefficient, which adversely affects waveform equalization. Therefore, it is desired that the sample value at the time of switching by the control signal by the polarity determination circuit 56 (FIG. 6) be a value close to the reproduction signal level 0. Therefore, in order to avoid the adverse effect, the sample value at the time of switching by the control signal by the polarity determination circuit 56 (FIG. 6) may be reduced, such as by 1/2, 1/4, or 1/8.

(Second Embodiment) FIG. 10 shows a second embodiment.
3 is a block diagram showing the configuration of a PRML detector 100 according to FIG. The feature of the PRML detector 100 is that the Viterbi decoder 1 is used.
12 is to output the PR provisional determination result. As described with reference to FIG. 19 or 20, the conventional PR provisional determination is performed based on the signal before being input to the Viterbi decoder (maximum likelihood decoder). By using a more accurate binarized data string in the Viterbi decoder for this PR temporary determination, it is possible to obtain a desired PR characteristic with high accuracy.

The PRML detector 100 includes the FIR equalizer 1
11, a Viterbi decoder 112, a PR equalization target value determiner 113, and a coefficient adaptive controller 114. PR
The ML detector 100 has a function corresponding to the waveform equalizer 11 and the maximum likelihood decoder 6 of the information reproducing apparatus 1 described with reference to FIG. The FIR equalizer 111, the PR equalization target value determiner 113, and the coefficient adaptive controller 114 are also called adaptive equalizers and correspond to the waveform equalizer 11 (FIG. 1). More specifically, the FIR equalizer 111 of the PRML detector 100 corresponds to the FIR filter 46 (FIG. 6),
The PR equalization target value determiner 113 includes an error signal detector 51
The coefficient adaptive controller 114 mainly corresponds to the correlation detection unit 53, the loop gain setting unit 54, the coefficient calculation unit 55, and the polarity determination circuit 56.

The digital signal after AD conversion is input to the FIR equalizer 111. This FIR equalizer 111 can equalize a desired PR characteristic. The PR method will be described below.

The recording / reproducing system of the optical disk has various fluctuations of low frequency components. When the recording density is increased, the recording / reproducing system is used up to near the upper limit of the frequency band, and when the adjacent marks are read, respective reproduced waveforms are likely to cause interference. When the reproduced waveform interferes, a read error occurs. This phenomenon is called intersymbol interference. PR equalization is
The intersymbol interference is positively used. This makes it possible to add meaning to the data at the sampling points according to the transfer characteristics. This means that the reproduction signal from the disc can be equalized into a desired shape (characteristic).

There are various methods for PR equalization. Therefore, it is necessary to select a method that matches the frequency characteristics of the recording medium. In the case of optical discs, especially DVDs, the modulation transfer function (Modulation Transfe
It is necessary to select a PR method that matches the r function (MTF) and considers the modulation frequency characteristic of the recording code. DVD
Is EFM (Eight to Fourteen Modulation) or EF
A reproduction signal using a code word having a minimum code length of 3T, such as the M-Plus code, is used. In the case of PR equalizing a DVD reproduction signal, PR (a,
When the (b, b, a) method is adopted, it can be limited to five signal levels (0, a, a + b, a + 2b, 2a + 2b). Therefore, the number of Viterbi decoder states is five.
An integer is entered in each of "a" and "b". Further, when a code word having a minimum code length of 2T, such as a (1,7) RLL (Run Length Limited) code, is used for the optical disc, and PR (a, b, b) having a PR length of 4 is used. , A) method, there are seven signal levels (0, a, 2a,
a + b, 2b, a + 2b, 2a + 2b), and the number of states of the Viterbi decoder is 7. The larger the PR length, the higher the signal level and the number of states of the Viterbi decoder. That is, a more complex system.

As described above, in the case of PR equalization using the adaptive algorithm, if the probability of erroneous tentative decision increases,
It is difficult to calculate an accurate equalization error for all equalization targets, and it is not possible to obtain satisfactory convergence characteristics. Therefore,
As shown in FIG. 10, by extracting from the Viterbi decoder 12 the binarized data string used for temporary determination, the error rate of temporary determination can be reduced.

In the following, a code word having a minimum code length of 2T and P
A system combining the R (a, b, b, a) method is adopted as an example, and a more accurate equalization error is calculated for a desired equalization target, and a satisfactory convergence characteristic is obtained. To do.

FIG. 11 shows a codeword having a minimum code length of 2T and P.
FIG. 11 shows a state transition diagram of the Viterbi decoder 112 (FIG. 10) when combined with the R (a, b, b, a) method. When the codeword having the minimum code length of 2T is used, since the patterns of “010” and “101” do not exist in the coded sequence,
The number of states is limited to 6 and the number of paths is limited to 10. When the signal level is calculated from these 6 states and 10 paths, the output for the signal sequence input “0000” is “0” and the input “000”.
The output for "1" is "a", the output for "0011" is "a + b", the output for "0110" is "2b", and the output for "0111" is "a + 2".
b ", the output for the input" 1000 "is" a ", the output for the input" 1001 "is" 2a ", the input" 110 "
The output for "0" is "a + b", the output for input "1110" is "a + 2b", and the output for input "1111" is "2a + 2b".

As a result, the output signal level is "0",
"A", "a + b", "2a", "2b", "a + 2"
There are 7 levels of "b" and "2a + 2b", and each level is
It becomes the PR equalization target value described above. That is, the coefficient adaptive controller 114 (FIG. 10) updates the taps of the FIR equalizer 111 (FIG. 10) so that the input signal is equalized to the equalization target value. The equalization is performed by reducing the difference (equalization error) between the output signal of the FIR equalizer 111 (FIG. 10) and the PR equalization target value.

Next, the operation of the Viterbi decoder 112 (FIG. 10) for the above PR equalization method will be described. The Viterbi decoder 112 (FIG. 10) does not make a judgment (so-called hard judgment) of "0" or "1" with respect to the input data with a certain threshold, as in the level detection method. Viterbi decoder 112 (see FIG.
0) is based on the past digitized data sequence,
The most probable data string is judged (so-called soft judgment).

FIG. 12 is a block diagram showing a concrete configuration of the Viterbi decoder 112. The Viterbi decoder 112
In general, the branch metric arithmetic circuit 151, the path metric arithmetic circuit 152, and the path memory 153 are provided. The branch metric calculation circuit 151 has 1
FIR equalizer 111 (FIG. 10) for each channel clock
Error between the signal (sample data) input from the device and seven different expected values [d0, d1, d2, d3, d4, d5, d6] input from the coefficient adaptive controller 114 (FIG. 10) Compute a branch metric that is These seven expected values are "0", "a", and "a +".
b "," 2a "," 2b "," a + 2b "," 2a + 2 "
This corresponds to the signal level of b ″.
The metric calculation circuit 151 calculates the branch metric BM _k (i) by the following Expression 2.

BM _k (i) = (y _k −di) ² (Equation 2) Here, y _k is a signal (sample data) input from the FIR equalizer 111 (FIG. 10), and di ( i =
0, 1, ..., 6) are the seven expected values [d0, d1, d2,
d3, d4, d5, d6].

Next, the path metric calculation circuit 152
Calculates the path metric by cumulatively adding the branch metrics for each channel clock. Specifically, the path metric calculation circuit 152 calculates the path metric by the following Expression 3.

(Equation 3) PM _k ^S0 = min [PM _k−1 ^S0 + BM _k (0),
PM _k-1 ^S5 + BM _k (1)] PM _k ^S1 = min [PM _k-1 ^S0 + BM _k (1),
PM _k-1 ^S5 + BM _k (2)] PM _k ^S2 = PM _k-1 ^S1 + BM _k (3) PM _k ^S3 = min [PM _k-1 ^S3 + BM _k (6),
PM _k-1 ^S2 + BM _k (5)] PM _k ^S4 = min [PM _k-1 ^S3 + BM _k (5),
PM _k-1 ^S2 + BM _k (4)] PM _k ^S5 = PM _k-1 ^S4 + BM _k (3)

In Expression 3, "min" is a mathematical symbol, and, for example, min [a, b] represents the smaller of a and b (either one when a = b).

Then, the path metric calculation circuit 152
Is a signal [sel0, s for selecting the most probable data sequence with the smallest path metric.
[el1, sel2, sel3] are calculated based on Expressions 4 to 7 and output to the path memory 153.

(Equation 4) PM _k-1 ^S0 + BM _k (0) ≧ PM _k-1 ^S5 + BM
_{When k} (1), Sel0 = 1 PM _k-1 ^S0 + BM _k (0) <PM _k-1 ^S5 + BM
_{When k} (1), Sel0 = 0 (Equation 5) PM _k-1 ^S0 + BM _k (1) ≧ PM _k-1 ^S5 + BM
_{When k} (2), Sel1 = 1 PM _k-1 ^S0 + BM _k (1) <PM _k-1 ^S5 + BM
_{When k} (2), Sel1 = 0 (Equation 6) PM _k-1 ^S3 + BM _k (6) ≧ PM _k-1 ^S2 + BM
_{When k} (5), Sel2 = 1 PM _k-1 ^S3 + BM _k (6) <PM _k-1 ^S2 + BM
_{When k} (5), Sel2 = 0 (Equation 7) PM _k-1 ^S3 + BM _k (5) ≧ PM _k-1 ^S2 + BM
_{When k} (4), Sel3 = 1 PM _k-1 ^S3 + BM _k (5) <PM _k-1 ^S2 + BM
_{When k} (4), Sel3 = 0

The path memory 153 stores a predetermined candidate sequence, and selects signals [sel0, sel1, sel2, se received from the path metric operation circuit 152.
13], the data string is output. If the memory length of the path memory 153 for storing the data string is increased, the probability of correct selection increases, but if it is too long, the circuit scale increases. Therefore, there is a trade-off relationship between the probability of being correctly selected and the circuit scale, and it is determined by checking the performance and the circuit scale. Further, in the present embodiment, the path memory 153 outputs the temporary judgment data series from the middle of the path. The output temporary judgment data series is PR
It is used as a temporary judgment value for judging the equalization target value.

FIG. 13 shows the path memory 153 (FIG. 12).
2 is a circuit showing a detailed configuration of Path memory 153
Includes a plurality of flip-flops FF and a selector.
Six flip-flops FF, which are state registers, are arranged side by side in the vertical direction of the figure, and the number "6" corresponds to the number of states. The horizontal direction corresponds to the memory length of the path memory 153. One stage is composed of a set of four selectors and six flip-flops FF arranged in the vertical direction of the figure. Path memory 153 (Fig. 12)
Is composed of 20 to 30 stages. The path memory 153 (FIG. 12) is the path metric operation circuit 1
52 (FIG. 12) to select signals sel0, sel1, se
12 and sel3 are received, and the data “0” or “1” input to the FF is selected based on the received selection signal. In the figure, [011101] is sequentially input from the top to the leftmost flip-flop FF as an initial value. The selection signal is controlled to select the most probable path. As a result, the paths are unified, and the output of the flip-flop FF of each stage becomes the same for a certain path memory length. That is, in the final stage, the outputs of all the flip-flops FF have the same value.
The final output is the Viterbi decoder 11 as the Viterbi detection output.
It is output from 2.

The path memory length for outputting the series of temporary judgment values must be appropriately selected depending on the combination of the code word used and the PR system. Specifically, the error rate is
It is necessary to select a length that does not significantly deteriorate compared to the final stage of the path memory in the Viterbi decoder. However, if the path memory length for outputting the series of temporary determination values is too long, the delay of the feedback loop until the tap coefficient is updated increases. Feedback loop delays sometimes degrade overall system performance. Therefore, in view of these two points, it is necessary to appropriately select the path / memory length for temporary determination output.

A method for facilitating the recovery of the feedback system when the loop performance deteriorates or is likely to deteriorate will be described below. According to this method, the Viterbi decoder 1 according to the present invention is
Even if the error rate of the tentative decision sequence from 12 (FIG. 10) becomes large, the PRML detector 100 will not operate unstablely.

FIG. 14 shows the temporary decision output (FIG. 13) in the path memory 153 (FIG. 12) of the Viterbi decoder 112.
It is a block diagram which shows the detailed structure which performs. As described above, the Viterbi decoder 112 (FIG. 12) unifies the paths by selecting the most probable path. That is, in a certain flip-flop FF (state register) before the propagation through the path memory 153 (FIG. 12) is completed, the output of the flip-flop FF converges to the same value. This is called “merge”. However, even though the most probable path is selected, there are cases where the paths are not unified, that is, they do not converge. At this time, the flip-flop FF is in a state of holding a plurality of candidate paths. This is called "do not merge". If merging is not performed, if the flip-flop FF continues to propagate its output, the tentative determination output and the final output (Viterbi detection output) of the Viterbi decoder 112 (FIG. 12) are likely to be erroneous.

Therefore, in this embodiment, a merge check signal (Merge Check) indicating whether or not a merge has been performed.
k signal) is output. FIG. 14 is a diagram showing a circuit for outputting a merge check signal, which is formed by using two NOR circuits and an AND circuit. The outputs of the six flip-flops FF in a predetermined stage are input to each of the first NOR circuit and the AND circuit, and the outputs thereof are input to the second NOR circuit. The merge check signal is the second
It is obtained as the output from the NOR circuit of. The merge check signal has a low level when merged, and has a high level when not merged.

As shown in FIG. 10, the coefficient adaptive controller 11
4 (FIG. 10) may use the merge check signal to determine whether or not to feed back the temporary determination sequence. For example, when the merge check signal is at a high level, or when the number of times the signal is at a high level in a certain channel clock section becomes a predetermined value or more, the coefficient adaptive controller 114
In FIG. 10, the tap coefficient update may be stopped or the tap coefficient may be reset (initialized) to a predetermined initial value.
Furthermore, conventional feedforward processing (see FIG.
You may switch so that it may return to 9). Furthermore, in this case,
The binary data output from the phase comparator 222 (FIG. 19) may be directly output as the final binary data so that PRML detection is not performed. Alternatively, the processing method (FIG. 20) that reduces the feedback delay may be switched. By changing the circuit to be used and the output according to the merge check signal, a further fail-safe measure can be taken.

Referring again to FIG. 10, the Viterbi decoder 11
The PR equalization target value determiner 13 based on the temporary determination output of 2
How to determine a desired PR target value will be described. Here, the PR (a, b, b, a) method described above is taken as an example, and the PR equalization target value determiner 13 determines that the minimum code length is 2
It is assumed that the PR target value is determined based on the state transition diagram (FIG. 11) determined by the codeword of T and the PR (a, b, b, a) method.

More specifically, the PR equalization target value determiner 113 has a table of 4 channel bits. The value of each channel bit is a temporary determination output value from the Viterbi decoder 12. The table defines the correspondence between input values and output values based on the state transition diagram (FIG. 11). That is, the table shows that the PR target value for "0000" is "0", the PR target value for "0001" is "a", and the PR target value for "0011" is "a + b", "0110". The PR target value for the case is "2b", the PR target value for the case of "0111" is "a + 2b", the PR target value for the case of "1000" is "a", and the PR target value for the case of "1001" is "2a". , PR target values for “1100” are “a + b”, PR target values for “1110” are “a + 2b”, and “111”.
The PR target value for the case of "1" is defined to be "2a + 2b".

FIG. 15 is a diagram for explaining the output of the FIR equalizer 111 (FIG. 1) and the procedure for determining the PR equalization target value. The output of the FIR equalizer 111 (FIG. 1) is a signal waveform when a 5T mark, a 2T space, and a 3T mark are read, and the sampling value for each channel clock is yk [0] to yk [14]. . On the other hand, the provisional determination output from the Viterbi decoder 112 (FIG. 10) obtained based on the output of the FIR equalizer 111 (FIG. 1) is “001.
11110011100 ". With the above table,
According to this tentative determination output, the PR equalization target value determiner 113
(FIG. 10) shows that (1) the PR target value for “0011” of the first to fourth bits is “a + b”, and (2) the PR target value for “0111” of the second to fifth bits is “a + 2b”.
(3) The PR target value for "1111" of the 3rd to 6th bits is "2a + 2b", and (4) "11" of the 4th to 7th bits.
PR target value for "11" is "2a + 2b", (5)
It is determined to be "a + 2b" in the case of "1110" of the 5th to 8th bits.

PR equalization target value decision unit 113 (FIG. 10)
Determines the PR target value of (1) as the target value for the FIR equalizer output yk [2]. The PR equalization target value determiner 113 (FIG. 10) determines the PR target value of (2) as the target value for yk [3]. Similarly, yk
As the target value for [4], the PR target value of (3) is set to y
As the target value for k [5], the PR target value of (4) is
The PR target value of (5) is determined as the target value for yk [6], and the PR target value of (5) is determined as the target value for yk [7].

The coefficient adaptive controller 114 (FIG. 10) uses the FIR equalizer 111 (FIG. 10) so that the input signal is equalized to the equalization target value, that is, the equalization error becomes smaller. Update the tap. The equalization error is the PR equalization target value and the FIR equalizer 111 corresponding to the PR equalization target value.
It can be obtained by the difference from the output value of (FIG. 10).

The PR equalization target value determiner 113 (see FIG.
0), the state transition rule (Fig.
When a sequence that does not conform to 1) is input, it can be clearly determined as an error in the provisional determination sequence. In this case, the PR equalization target value determiner 113 (FIG. 10) causes the coefficient adaptive controller 114 (FIG. 10) to stop updating the tap coefficient of the FIR equalizer 111 (FIG. 10). By stopping the update of the tap coefficient, it is possible to avoid erroneous tap update.

The first and second embodiments of the present invention have been described above. The first embodiment reduces the error at the time of data decoding due to the asymmetry of the physical shape of the mark on the recording medium. On the other hand, the second embodiment improves the accuracy of temporary determination when adaptively controlling the coefficient of the FIR equalizer, and reduces the error at the time of decoding the data. Embodiments 1 and 2
The invention is aimed at reducing errors due to different causes, so they can be combined. Specifically, the FIR equalizer 111 in FIG. 10 may include the asymmetry detector 15, the polarity discriminator 16, and the coefficient C selector 17 in FIG. Thereby, the first embodiment
Both the effects 1 and 2 can be obtained, and the error at the time of data decoding can be further suppressed.

[0092]

According to the present invention, the equalization characteristic of the waveform equalizer is switched between the mark side and the space side in accordance with the asymmetry amount, thereby suppressing the deviation and dispersion at the detection point, thereby reducing the PRML system. The performance can be improved. Furthermore, by providing a coefficient learning circuit, even if there is asymmetry, appropriate equalization coefficients can be learned and determined. By using the waveform equalizer of the present invention, D
In PRML signal processing of optical disks such as VD and MO, and magnetic disks such as HDD, it is possible to suppress errors during data decoding to a low level.

Further, according to the present invention, provisional determination information for determining the PR equalization target is extracted from the Viterbi decoder.
As a result, the error rate of provisional determination can be reduced. As a result, an accurate equalization error can be obtained by determining the target value from the provisional determination information based on the PR system state transition rule,
Good convergence characteristics can be obtained. That is, the error at the time of decoding the data can be suppressed low. Further, according to the present invention, it is possible to prevent the performance of the loop of the feedback system from deteriorating and to avoid the increase of the delay by detecting whether or not the path memory of the Viterbi decoder has been merged.

[Brief description of drawings]

FIG. 1 is a block diagram showing a general configuration of an information reproducing device that performs PRML signal processing.

FIG. 2 is a block diagram showing a specific configuration of a waveform equalizer.

FIG. 3 is a graph showing an example of impulse response.

FIG. 4 shows a histogram of a reproduced signal when the waveform of an asymmetrical signal is equalized.

FIG. 5 is a block diagram showing a configuration of an adaptive waveform equalizer that determines and updates an appropriate equalization coefficient.

FIG. 6 is a block diagram showing a configuration of a coefficient learning circuit.

FIG. 7 is a block diagram showing a configuration of a coefficient calculation unit.

FIG. 8A is a waveform diagram showing three types of impulse responses. (B) is a graph showing the amplitude frequency characteristics of each of the three types of impulse responses.

FIG. 9A shows a histogram when an asymmetric reproduction waveform is sampled by an A / D converter when a (1,7) RLL modulation code is used. (B) is
7 shows a histogram of an output signal of a conventional waveform equalizer.
(C) shows a histogram of the output signal of the waveform equalizer according to the present invention.

FIG. 10 is a block diagram showing a configuration of a PRML detector according to a second embodiment.

FIG. 11 is a codeword having a minimum code length of 2T and PR (a,
The state transition diagram of a Viterbi decoder at the time of combining with (b, b, a) system is shown.

FIG. 12 is a block diagram showing a specific configuration of a Viterbi decoder.

FIG. 13 is a circuit showing a detailed configuration of a path memory.

FIG. 14 is a block diagram showing a detailed configuration for performing provisional determination output in a path memory of a Viterbi decoder.

FIG. 15 is a diagram illustrating an output of a FIR equalizer and a procedure for determining a PR equalization target value.

FIG. 16 is a block diagram showing a general configuration of an information reproducing apparatus using the PRML system.

FIG. 17 is a block diagram showing an example of the configuration of a waveform equalizer.

FIG. 18 is a diagram showing a simple asymmetry model.

FIG. 19 is a block diagram showing a configuration of a PRML detector.

FIG. 20 is a block diagram showing a configuration of a PRML detector.

FIG. 21 (A) shows a histogram of a reproduced signal that is not asymmetry. (B) shows a histogram of an asymmetric reproduction signal. (C) is a waveform equalizer,
In the case of PR equalization of a reproduced signal that is not asymmetry,
7 shows a histogram of an output signal. (D) shows a histogram of the equalizer output signal in the case of PR equalizing the asymmetric reproduction waveform.

22 is a graph showing frequency characteristics of a reproduced waveform based on the histogram of the asymmetrical reproduced waveform shown in FIG. 21 (B).

[Explanation of symbols]

1 Information playback device, 2 optical disc, 3 optical pickup, 4 front-end processor, 5 A / D converter, 6 maximum likelihood decoder, 11 waveform equalizer, 15 Asymmetry detector, 16 polarity discriminator, 17 coefficient C selector, 45 coefficient learning circuit, 63, 64, 67, 68 selector, 70 registers, 111 FIR equalizer 111, 112 Viterbi decoder 112, 113 PR equalization target value determiner, 114 coefficient adaptive controller, 151 branch metric arithmetic circuit, 152 path metric calculation circuit, 153 path memory

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Junichi Minamino             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Atsushi Nakamura             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Shinichi Konishi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5D044 BC02 CC04 FG01 FG02 FG05                       FG11 GL32                 5D090 AA01 BB02 BB03 BB04 CC04                       CC12 DD03 EE14 EE17 GG03                 5K046 AA07 BB00 CC11 EE02 EF04                       EF11 EF27

Claims (16)

[Claims] 1. A waveform equalizer for equalizing a waveform of a reproduction signal obtained by reproducing marks and non-marks recorded on a recording medium, the delay element delaying propagation of the reproduction signal, the reproduction signal, and A plurality of multipliers for multiplying each of the reproduction signals delayed by the delay element by a predetermined coefficient, and due to the physical shapes of the mark and the non-mark,
A detection unit that detects asymmetry of the reproduction signal and outputs a detection signal that represents an asymmetry amount; a determination unit that determines the mark and the non-mark based on the reproduction signal and outputs a determination signal; A first coefficient that is multiplied by the reproduction signal that reproduces the mark, and a reproduction signal that reproduces the non-mark, based on the detection signal output from
And selecting a second coefficient different from the first coefficient, and selecting one of the calculated first coefficient and the second coefficient based on the determination signal output from the determination unit. Waveform equalizer including a section and an adder that adds outputs of a plurality of multipliers. 2. The waveform equalizer is an FIR filter, and the selection unit changes the predetermined coefficient to switch the equalization characteristic of the reproduction signal in the pit and the non-pit. The waveform equalizer described in 1. 3. The waveform equalizer according to claim 1, wherein there are an odd number of the predetermined coefficients, and the first coefficient and the second coefficient selected by the selection unit are central coefficients. . 4. The impulse response of the waveform equalizer is specified based on the predetermined coefficient, and the absolute value of the first coefficient and the absolute value of the second coefficient are different from the predetermined coefficient. The waveform equalizer according to claim 1, wherein the waveform equalizer is larger than the absolute value of. 5. The waveform equalizer is (a, b, b, a)
2. The waveform equalizer according to claim 1, wherein the waveform equalizer is a partial response equalizer that is formed of a pulse-shaped impulse response. 6. A waveform equalizer for equalizing a waveform of a reproduction signal obtained by reproducing marks and non-marks recorded on a recording medium, wherein the waveform equalizer is a delay element for delaying propagation of the reproduction signal. A plurality of multipliers for multiplying each of the reproduction signal and the reproduction signal delayed by the delay element by a predetermined coefficient, and coefficient learning for adaptively updating the predetermined coefficient to each of the plurality of multipliers The coefficient learning circuit includes: a circuit and an adder that adds outputs of a plurality of multipliers; a coefficient learning circuit; a teacher signal generation unit that generates a target teacher signal to be equalized; and a (a, b, b, a) type Consisting of impulse response,
An error detection unit that detects an error signal representing an error between the output signal equalized by the partial response method and the teacher signal generated by the teacher signal generation unit, and the mark and the non-mark based on the reproduction signal. A discriminating unit that discriminates and outputs a discriminating signal, holds the predetermined coefficient, and updates the predetermined coefficient so that the root mean square of the error is minimized based on the error signal detected by the error detecting unit. A plurality of registers for outputting the same, the first register holding a first coefficient by which the reproduction signal reproduced from the mark is multiplied, and the reproduction signal reproduced from the non-mark, and A plurality of registers including a second register that holds a second coefficient different from the first coefficient, and a first register based on the determination signal output from the determination unit. The first coefficient is, and a waveform equalizer and a register selection unit that selects one of the second of said second held in the register coefficients output. 7. The waveform equalization according to claim 6, wherein there are an odd number of the predetermined coefficients, and the first coefficient and the second coefficient selected by the register selection unit are central coefficients. vessel. 8. The impulse response of the waveform equalizer is specified based on the predetermined coefficient, and the absolute value of the first coefficient and the absolute value of the second coefficient are different from the predetermined coefficient. The waveform equalizer according to claim 6, wherein the waveform equalizer is larger than the absolute value of. 9. A waveform equalizer for equalizing the waveform of a reproduced signal obtained by reproducing a mark and a non-mark recorded on a recording medium, and 2 of the reproduced signal based on the waveform equalized by the waveform equalizer. PRML with decoder for generating binarized data
A detector, wherein the decoder outputs a temporary data string that is data before the binarized data is obtained, and the waveform equalizer includes a delay element that delays propagation of the reproduction signal, the reproduction signal And an equalizer having a plurality of multipliers for multiplying each of the reproduction signals delayed by the delay elements by a predetermined coefficient, and an adder for adding the outputs of the plurality of multipliers, and an output from the decoder Based on the provisional data sequence, the target value determiner for determining the target value to be equalized, the output from the adder of the equalizer, and the target value determined by the target value determiner, A PRML detector comprising: a coefficient adaptive controller that calculates the predetermined coefficient and adaptively updates the calculated predetermined coefficient to each of a plurality of multipliers. 10. The decoder has a path memory which constitutes a plurality of data paths, and when the plurality of data paths of the path memory converge based on the output of the equalizer,
The PRML detector according to claim 9, which outputs binarized data obtained by a converged data path. 11. The method according to claim 10, wherein when the plurality of data paths converge in the middle of the data path of the path memory, a merge check signal indicating convergence and the temporary data string are output. The described PRML detector. 12. The PRML detector according to claim 10, wherein if the plurality of data paths do not converge in the middle of the data path of the path memory, a merge check signal indicating that the data paths do not converge is output. 13. The P according to claim 12, wherein the coefficient adaptive controller stops updating the calculated predetermined coefficient based on a merge check signal output from the path memory.
RML detector. 14. The PRM according to claim 12, wherein the coefficient adaptive controller initializes the calculated predetermined coefficient based on a merge check signal output from the path memory.
L detector. 15. The target value determiner has a table that defines the correspondence between each of the plurality of data strings and each of the plurality of target values, and the target value determiner has a predetermined state transition. The PRML detector according to claim 9, wherein a data string is sequentially extracted from the temporary data string based on a rule, and the target value is determined based on the extracted data string and a table. 16. The PRML according to claim 9, wherein when the temporary data string violates the predetermined state transition rule, the target value determiner causes the coefficient adaptive controller to stop updating the coefficient.
Detector.