JP2010033656A - Data reproducing device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reproducing device capable of suppressing occurrence of determination errors even when the value of the identification point of an equalizing signal deviates from a reference value. <P>SOLUTION: An equalizer circuit 30 generates an equalizing signal by equalizing an input signal of predetermined characteristics. A Viterbi detector 40 outputs a data string where a maximum likelihood is obtained with respect to the equalizing signal as reproduction data on the basis of the equalizing signal and reference values at least some of which are selectable within a predetermined range. A reference value selection circuit 44 selects a reference value among the selectable reference values within the predetermined range according to the equalizing signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data reproduction apparatus and a reproduction method, and more specifically, an equalization process is performed on an input signal having a predetermined characteristic from an information recording medium, and a data string that provides the maximum likelihood for the equalization signal is obtained. The present invention relates to a data reproducing apparatus and a reproducing method for outputting as reproduced data.

  In order to store a large amount of data on an information recording medium, it is necessary to form a fine pattern on the medium and read it efficiently. For example, an optical disc apparatus changes the temperature of the information recording surface by changing the power of the laser beam condensed on the information recording surface of the disc, and forms a minute mark using the temperature. In the portion where the mark is formed, optical characteristics such as reflectance and phase change. Similarly, during reproduction, the information recording surface is irradiated with condensed laser light, the amount of reflected light is detected, the presence or absence of a recording mark is determined, and data reproduction is performed.

  At the time of data reproduction, the laser beam focused on the information recording surface is irradiated in a range slightly wider than the size of the recording mark. For this reason, the reproduction signal obtained by detecting the reflected light amount includes interference from the surrounding recording marks in addition to the reflected light from the recording marks corresponding to the central portion of the condensed laser light. When determining an original data string from a signal including interference, PRML (Partial Response Maximum likelihood) detection that combines partial response equalization and maximum likelihood detection is often used (see, for example, Patent Document 1).

  FIG. 9 shows a general data reproducing apparatus. The reproduction signal including interference is converted into digital data by the A / D converter 201, and is subjected to partial response equalization by the equalization circuit 203, and data is determined by the Viterbi detector 204. The synchronous clock extraction circuit 202 outputs a sampling clock that determines the sampling timing of the A / D converter 201. The synchronous clock extraction circuit 202 detects the phase error and frequency difference of the sampling clock based on the digital data output from the A / D converter 201, and controls the sampling timing. Partial response equalization is a technique of assuming a predetermined waveform as a response waveform per recording mark unit length and equalizing a reproduction signal so as to be superimposed. The response waveform per unit length is determined in consideration of the recording density and the spread of the laser beam.

  The reproduced signal is pseudo-multivalued because the amount of intersymbol interference in the signal is adjusted by partial response equalization. FIG. 10 shows a state transition diagram in PR (1, 2, 2, 1). The state transition diagram of FIG. 10 shows all the signal level change patterns that can be taken by the PR (1, 2, 2, 1) equalized signal having the shortest mark length of 2. S0 to S5 are names of states, and each of the branches connecting the states indicates a reference value of the signal level when the corresponding transition is performed. A signal level obtained when a PR (1, 2, 2, 1) equalized signal is sampled at an identification point using a code having a shortest mark length of 2 is a state transition diagram shown in FIG. Transition according to

  In PRML detection, a data series is determined based on an equalized signal pseudo-multivalued by partial response equalization. In the determination of the data series, all data series represented by the state transition diagram shown in FIG. 10 are selected, and the data series that maximizes the likelihood for the obtained equalized signal is selected. The Viterbi detection method is well known as a method for efficiently selecting a data series that maximizes the likelihood from a plurality of candidates. Normally, instead of calculating directly using the likelihood L, a path metric P (P = −log (L)) corresponding to a negative log likelihood is used. Selecting a sequence that maximizes the likelihood L is equivalent to selecting a sequence that minimizes the path metric P.

FIG. 11 shows a trellis diagram in which the state transition diagram shown in FIG. 10 is developed along the time axis. The Viterbi detection method will be described with reference to the trellis diagram shown in FIG. A signal sequence X obtained by sampling the equalized signal at the discrimination point is defined as (X [t], X [t + 1], X [t + 2],...). At each time, the number of candidate surviving paths is the same as the number of states, and the path metric for the surviving path corresponding to the state Sn at time t is P _n (t). Viterbi detection is advanced by updating the path metric value for each identification point and selecting the surviving path for each surviving path.

When X [t] is given, the survival path is selected as follows. There are two branches that transition to the state S0: a branch that transitions from S2 to S0 and a branch that transitions from S0 to S0. When the path metric corresponding to the state S2 immediately before X [t] is given is P ₂ [t−1] and the path metric corresponding to the state S0 is P ₀ [t−1], the transition from S2 to S0 is performed. The path metric when adopted is
P ₀ [t] = P ₂ [t−1] + (X [t] +0.67) ²
(S2 → S0) (1)
The path metric when the transition from S0 to S0 is adopted is
P ₀ [t] = P ₀ [t−1] + (X [t] +1.0) ²
(In the case of S0 → S0) (2)
It becomes. The second term on the right side of Equation 1 and Equation 2 is called the branch metric, which is the square of the Euclidean distance between the reference value corresponding to each branch and the equalized signal.

Since the surviving path selects the one with the smaller path metric value among these, Equation 1 and Equation 2 are combined,
P ₀ [t] = min [P ₂ [t−1] + (X [t] +0.67) ² ,
P ₀ [t−1] + (X [t] +1.0) ² ]
It is expressed. Similarly, the path metrics corresponding to states S1 to S5 are
P ₁ [t] = min [P ₂ [t−1] + (X [t] +0.33) ² ,
P ₀ [t−1] + (X [t] +0.67) ² ]
P ₂ [t] = P ₄ [t−1] + X [t] ²
P ₃ [t] = P ₁ [t−1] + X [t] ²
P ₄ [t] = min [P ₅ [t−1] + (X [t] −0.67) ² ,
_{P 3 [t-1] +} (X [t] -0.33) 2]
P ₅ [t] = min [P ₅ [t−1] + (X [t] −1.0) ² ,
_{P 3 [t-1] +} (X [t] -0.67) 2]
It is expressed as The survival path is updated according to which branch is selected in the function min []. By sequentially updating the path metric according to such an expression, a route that gives the minimum path metric from a plurality of candidates can be determined.

  When the survival path as described above is selected for each discrimination point for the signal series, the survival path is always kept at 6 as the number of states. If these six survivor paths are traced back for a certain period of time, all survivor paths will take the same path. By outputting the portion where all the paths of the surviving paths match as a confirmed data sequence, a data sequence that maximizes the likelihood can be selected.

The Viterbi detector 204 (FIG. 9) includes a branch metric calculation circuit 241, a path metric calculation circuit 242, and a path memory 243. The branch metric calculation circuit 241 calculates a branch metric. The path metric calculation circuit 242 calculates a path metric. The path memory 243 sequentially receives a signal indicating which branch has been selected from the path metric calculation circuit 242, and holds selection information for a certain period of time necessary to determine the determined path. The path memory 243 functions to output a data string (determination data) corresponding to the determined path.
JP-A-8-153370

  When the response waveform of the reproduction signal is close to the desired partial response equalization waveform, the identification point of the equalization signal can be detected without performing an operation of greatly amplifying or suppressing a specific frequency component by the equalization circuit. The value can be brought close to the reference value. However, if the spread of the focused laser beam or the recording mark density changes, the sample value of the discrimination point deviates from the reference value assumed by the desired partial response. For example, when the sample value at the discrimination point is shifted due to a decrease in the amplitude of the high frequency component, the sample value can be brought close to the reference value by emphasizing the high frequency component with an equalization circuit. However, at this time, high-frequency noise components are also enhanced. The maximum likelihood detector is designed on the assumption of white noise. For this reason, if the noise deviates from white, a determination error tends to occur.

  An object of the present invention is to provide a data reproducing apparatus and a reproducing method that can suppress the occurrence of a determination error even when the value of the discrimination point of an equalized signal deviates from a reference value.

  In order to achieve the above object, the data reproducing apparatus of the present invention performs an equalization process on an input signal having a predetermined characteristic to generate an equalized signal, and based on the equalized signal and the reference value. A maximum likelihood detector that outputs a data string that provides the maximum likelihood for the equalized signal as reproduced data, and at least a part of the reference value can be selected within a predetermined range, A selectable reference value is provided with a reference value selection circuit that selects the reference value from the predetermined range according to the equalization signal.

  The data reproduction method of the present invention is a method for generating an equalized signal by performing an equalization process on an input signal having a predetermined characteristic, and based on the equalized signal and a reference value, A step of outputting a data string from which likelihood is obtained as reproduction data, and at least a part of the reference value is selectable within a predetermined range, and the selectable reference value is determined according to the equalization signal And selecting the reference value from the predetermined range.

  The data reproducing apparatus and reproducing method of the present invention can suppress the occurrence of a determination error even when the value of the discrimination point of the equalized signal deviates from the reference value.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a data reproducing apparatus according to a first embodiment of the present invention. The data reproduction device includes an A / D converter 10, a synchronous clock extraction circuit 20, an equalization circuit 30, and a Viterbi detector 40. The data reproducing device is mounted on, for example, an optical disk device. The reproduction signal input to the data reproduction apparatus is, for example, a reproduction signal obtained by irradiating a focused beam onto an optical recording medium and detecting the amount of reflected light.

  The A / D converter 10 samples the reproduction signal based on the sampling clock provided by the synchronous clock extraction circuit 20 and converts it into digital data. The digital data converted by the A / D converter 10 is fed back to the synchronous clock extraction circuit 20. The synchronous clock extraction circuit 20 detects the phase error and frequency difference of the sampling clock based on the given digital data, and operates to maintain the correct sampling timing according to the data rate of the reproduction signal.

  An equalization circuit (equalization means) 30 performs filtering based on the sampled reproduction signal and outputs an equalization signal. It is assumed that the response characteristics of the equalization circuit 30 are determined in advance according to the reproduction signal so that the equalization signal becomes close to a partial response waveform. In the following description, it is assumed that the equalized waveform is PR (1, 2, 2, 1) equalized. When the reproduction signal is originally close to the PR (1, 2, 2, 1) equalization waveform, the equalization circuit 30 corresponds the value of the discrimination point of the equalization signal to each transition without greatly changing the frequency characteristics. It is possible to equalize so as to be distributed around the seven reference values ± 1.0, ± 0.67, ± 0.33, and 0.0.

  FIG. 2 illustrates a histogram of equalized signal sample values. In FIG. 2, three types of histograms having different resolutions defined by the ratio of the amplitude of the pattern composed of a continuous 3T mark and 3T space are superimposed on the signal amplitude. Referring to FIG. 2, it can be seen that when the resolution is 65% close to the ideal value, the histogram has peaks at approximately seven locations of ± 1.0, ± 0.67, ± 0.33, and 0.0. However, in the histogram of the equalized signal obtained by equalizing a waveform with a resolution of 70% or 60%, the position at which the peak appears deviates from the above seven reference values.

  In FIG. 2, for comparison, the signal amplitude and the offset are adjusted so that the three locations ± 0.67 and 0.0 match. Referring to FIG. 2, in the waveform having a small resolution (60%), the peak corresponding to ± 0.33 is shifted closer to 0.0, and the peak corresponding to ± 1.0 is 0. It can be seen that there is a shift away from zero. On the other hand, in the waveform with high resolution (70%), the peak is shifted in the opposite direction to the waveform with low resolution.

  Returning to FIG. 1, the Viterbi detector (maximum likelihood detector) 40 determines and outputs a data series from the equalized signal waveform-equalized by the equalization circuit 30. The Viterbi detector 40 includes a branch metric calculation circuit 41, a path metric calculation circuit 42, a path memory 43, and a reference value selection circuit 44. The branch metric calculation circuit 41 calculates a branch metric. The path metric calculation circuit 42 calculates a path metric. The path memory 43 sequentially receives a signal indicating which branch has been selected from the path metric calculation circuit 42, and holds selection information for a certain period of time necessary to determine the determined path. The path memory 43 outputs, as reproduction data, a data string (determination data) corresponding to the determined path, that is, a data string that provides the maximum likelihood for the equalized signal.

  FIG. 3 shows a trellis diagram used for determination by the Viterbi detector 40. The difference from the trellis diagram shown in FIG. 11 is that at least a part of the reference values (reference values) corresponding to the branches that transition from one state to the next state can be selected within a predetermined range. . For example, the reference value corresponding to the branch that transitions from the state S0 to S0 takes a value in the range from -1.1 to -0.9. Further, the branch transitioning from the state S2 to S1, the branch transitioning from the state S3 to S4, and the branch transitioning from the state S5 to S5 are also in the range of −0.43 to −0.23 and 0.23 to 0. It takes a value in the range of 43 and in the range of 0.9 to 1.1.

  The reference value selection circuit 44 outputs, for each sample point, a reference value corresponding to each branch that can be selected in the predetermined range based on the input equalization signal for selectable reference values. The selectable reference value may be set for a branch whose distribution varies greatly according to the characteristics of the reproduction signal. In FIG. 3, the reference values corresponding to the four branches whose distribution changes greatly according to the change in resolution are set to take a certain range.

となる。同様に、状態Ｓ２からＳ１に遷移する枝の参照値Ｒ_２１［ｔ］、状態Ｓ３からＳ４に遷移する枝の参照値Ｒ_３４［ｔ］、状態Ｓ５からＳ５に遷移する枝の参照値Ｒ_５５［ｔ］は、それぞれ、下記のように決められる。

The reference value selection circuit 44 selects, as a reference value, a value that minimizes the difference from the input equalization signal in each range. For example, in the branch (−1.1 to −0.9) transitioning from the state S0 to S0, if the equalization signal X [t] to be input is given, the reference value R ₀₀ [t] is

It becomes. Similarly, the reference value R ₂₁ [t] of the branch transitioning from state S2 to S1, the reference value R ₃₄ [t] of the branch transitioning from state S3 to S4, and the reference value R _{55 of the} branch transitioning from state S5 to S5 [T] is determined as follows.

The branch metric calculation circuit 41 calculates a branch metric for the branch for which the reference value is output from the reference value selection circuit 44 based on the reference value. On the other hand, the branch metric calculation circuit 41 calculates a branch metric for a branch having a fixed reference value in FIG. 3 based on the fixed reference value (standard value) and the input equalized signal as usual. The branch metrics B _mn [t] corresponding to the branches that transition from the state Sm to Sn are respectively expressed by the following equations.
B ₀₀ [t] = (X [t] −R ₀₀ [t]) ²
B ₀₁ [t] = (X [t] +0.67) ²
B ₁₃ [t] = X [t] ²
B ₂₀ [t] = (X [t] +0.67) ²
B ₂₁ [t] = (X [t] −R ₂₁ [t]) ²
B ₃₄ [t] = (X [t] −R ₃₄ [t]) ²
B ₃₅ [t] = (X [t] −0.67) ²
B ₄₂ [t] = X [t] ²
B ₅₄ [t] = (X [t] −0.67) ²
B ₅₅ [t] = (X [t] −R ₅₅ [t]) ²

Here, for branches having a predetermined range where the reference value is not a fixed value, as can be seen from Equations 3 to 6, when the sample value X [t] of the equalized signal is within the predetermined range, etc. The sample value X [t] of the digitized signal becomes the reference value itself. Since the branch metric is given by the square of the reference value and the value of the equalized signal, the value of the branch metric is 0 when the equalized signal is in a predetermined range. For example, the reference value of the branch that transitions from the state S3 to S4 is a value in the range of 0.23 to 0.43. When the sample value X [t] of the equalized signal is a value from 0.23 to 0.43, the reference value is equal to X [t], so the branch metric B ₃₄ is 0. In this way, in the branch where the reference value has a predetermined range, when the sample value X [t] of the equalized signal is a value within the range of the reference value, the equalized signal has no deviation from the reference value. Will be treated as

Based on the branch metric calculated by the branch metric calculation circuit 41, the path metric calculation circuit 42 updates the path metric P _n corresponding to each state from the states S0 to S5 for each identification point. Each path metric is expressed by the following equation.
P ₀ [t] = min [P ₂ [t−1] + B ₂₀ [t], P ₀ [t−1] + B ₀₀ [t]]
P ₁ [t] = min [P ₂ [t−1] + B ₂₁ [t], P ₀ [t−1] + B ₀₁ [t]]
P ₂ [t] = P ₄ [t−1] + B ₄₂ [t]
P ₃ [t] = P ₁ [t−1] + B ₁₃ [t]
P ₄ [t] = min [P ₅ [t−1] + B ₅₄ [t], P ₃ [t−1] + B ₃₄ [t]]
P ₅ [t] = min [P ₅ [t−1] + B ₅₅ [t], P ₃ [t−1] + B ₃₅ [t]]

  The path metric calculation circuit 42 sequentially selects a path that minimizes the path metric from the plurality of paths that reach each state, and holds a path metric corresponding to the path. The path metric calculation circuit 42 sequentially outputs information related to route selection to the path memory 43. The path memory 43 outputs determination data based on information passed from the path metric calculation circuit 42 for each identification point.

For example, as shown in FIG. 3, it is assumed that the path indicated by the thick arrow is selected when an equalization signal up to X [t−1] is given. In FIG. 3, a route indicated by a dotted arrow is a route that has been selected. The surviving path corresponding to the state S3 is a path of S0 → S1 → S3, and P ₃ [t−1] is information indicating how similar the reference value corresponding to this path and the equalized signal sequence are. Represents. The same applies to other states. For example, for the state S5, the route S1 → S3 → S5 is selected as the surviving path that gives the minimum path metric P ₅ [t−1].

When the equalized signal X [t] at time t is given, the path metric P ₄ [t] corresponding to the state S4 is represented by path metrics P ₃ [t−1], P ₅ [t−1], and Updated based on branch metrics B ₃₄ [t], B ₅₄ [t]. In the method of calculating the branch metric with the reference value fixed, the route of S0 → S1 → S3 → S4 should be selected originally, and it corresponds to the route of S1 → S3 → S5 → S4 due to the influence of the difference in resolution. The path metric to be performed may be smaller and the path may be selected incorrectly.

On the other hand, in the present embodiment, the reference value of the branch affected by the resolution shift is not a fixed value but a value selected from a predetermined range according to the equalization signal. For example, in the branch corresponding to the transition from the state S3 to S4, the reference value is not the fixed value 0.33 (FIG. 11) but takes a value from 0.23 to 0.43 depending on the equalization signal. For this reason, even if a shift occurs in the distribution of the equalized signal, it is possible to prevent the branch metric B _{34 from} becoming unduly large. The reference value selection circuit 44 selects, as a reference value, a value that minimizes the difference from the input equalization signal within a range that can be selected as the reference value, so that the Viterbi detector 40 responds to the equalization signal. Thus, the path is selected based on the reference value that maximizes the likelihood among the values that can be selected as the reference value. By doing so, selection errors in path selection can be reduced, and data determination errors can be reduced.

  Next, a second embodiment of the present invention will be described. FIG. 4 shows a data reproducing apparatus according to the second embodiment of the present invention. The data reproducing apparatus according to the present embodiment includes a coefficient control circuit 50, an equalization target generation circuit 60, and a provisional determination circuit 70 in addition to the configuration of the data reproducing apparatus according to the first embodiment shown in FIG. The operations of the A / D converter 10 and the synchronous clock extraction circuit 20 are the same as those in the first embodiment. The operation of the Viterbi detector 40 is the same as that of the first embodiment. Similar to the first embodiment, the reference value selection circuit 44 selects a reference value corresponding to a specific branch from a predetermined range according to the equalization signal.

  The coefficient control circuit 50 controls the equalization parameter in the equalization circuit 30. The equalizer circuit 30 and the coefficient control circuit 50 constitute an adaptive equalizer. The equalization signal output from the equalization circuit 30 is input to the Viterbi detector 40 and the provisional determination circuit 70. The temporary determination circuit 70 performs data determination by a slicer based on the equalization signal. The determination by the slicer increases the probability that a detection error will occur as compared with the determination using the Viterbi detector 40. However, the determination result can be obtained with a small amount of delay compared to the Viterbi detector 40.

  Hereinafter, the provisional determination circuit 70 will be described assuming that slice levels are provided at two locations of ± 0.2 and ternary determination is performed to estimate a data series. FIG. 5 shows a state transition diagram for making a temporary determination based on the result of the ternary determination. Of the slice levels provided at two locations, “1” is indicated when it is above 0.2, “−1” is indicated when it is below −0.2, and “0” is indicated at the middle. The provisional determination circuit 70 determines whether the equalization signal is 1, 0, or −1, and sequentially updates information on the state according to the state transition shown in FIG. 5 according to the determination result. The provisional determination circuit 70 outputs data related to the internal state update to the equalization target generation circuit 60.

  The equalization target generation circuit 60 gives an equalization target value to the coefficient control circuit 50 based on the internal state update information. The equalization target value is determined corresponding to the branch representing the transition of the internal state. The equalization target value is defined by an upper limit and a lower limit of values that can be taken as equalization target values so that the equalization target can have a range for at least some branches. The equalization target generation circuit 60 passes the upper and lower limits of values that can be taken as equalization targets to the coefficient control circuit 50 for the branches for which the equalization target is a value selected from a predetermined range. The equalization target generation circuit 60 passes the single value to the coefficient control circuit 50 as an upper limit and a lower limit of the equalization target for the branch where the equalization target has a single value.

  FIG. 6 shows the equalization target value and the state transition in association with each other. For example, the branch that transitions from the state S2 to S1 has a predetermined width (−0.6 to 0.0) without the equalization target being set to a single value. The equalization target generation circuit 60 outputs the upper limit 0.0 and the lower limit −0.6 to the coefficient control circuit 50 as equalization target values for the branch that transitions from the state S2 to S1. On the other hand, for the branch that transitions from state S1 to state S3, the equalization target is a single value (0.0). The equalization target generation circuit 60 outputs the upper limit 0.0 and the lower limit 0.0 to the coefficient control circuit 50 as equalization target values for the branches that transition from the state S1 to S3.

  FIG. 7 shows an adaptive equalizer including an equalization circuit 30 and a coefficient control circuit 50. The equalization circuit 30 is a transversal filter having a delay circuit 31 that delays one sampling period, a multiplier 32, and an adder 33. The coefficient control circuit 50 includes a delay circuit 31, an equalization error selection circuit 51, a correlator 52, and an integrator 53. The coefficient control circuit 50 generates an equalization error based on the equalization target value input from the equalization target generation circuit 60 and the equalization signal, and performs multiplication in the equalization circuit 30 so that the equalization error is reduced. The coefficient of the device 32 is controlled. The initial value of the coefficient of each multiplier 32 is determined so that the equalized signal has a waveform close to PR (1, 2, 2, 1) when the reproduction signal has a standard waveform.

The equalization error selection circuit 51 receives the upper limit Dmax [t] and the lower limit Dmin [t] of the equalization target from the equalization target generation circuit 60. The equalization error selection circuit 51 calculates the equalization signal E [t] delayed by one sampling clock by the delay circuit 31 and the equalization target upper limit Dmax [t] and lower limit Dmin [t] according to the following equation. The error ε [t] is generated.

  The equalization error selection circuit 51 outputs an equalization error 0 when the equalization signal E [t] is within the range between the upper limit and the lower limit of the equalization target value. When the equalization signal E [t] is larger than the upper limit of the equalization target value, the equalization error selection circuit 51 determines the difference between the equalization signal E [t] and the upper limit of the equalization target value as the equalization error. Output as. Further, when the equalization signal E [t] is smaller than the lower limit of the equalization target value, the equalization error selection circuit 51 determines the difference between the equalization signal E [t] and the lower limit of the equalization target value, etc. Output as error. When the equalization target is a single value, that is, when the upper limit and the lower limit of the equalization target value are equal, the equalization error selection circuit 51 calculates the equalization signal E [t] and the equalization target value. The difference is output as an equalization error.

  Each correlator 52 calculates the correlation between the reproduced signal after sampling delayed by the delay circuit 31 and the equalization error. Each correlator 52 outputs a negative value when there is a positive correlation between the reproduction signal and the equalization error, and outputs a positive value when there is a negative correlation. Each integrator 53 integrates the output of each correlator 52. Each integrator 53 increases or decreases the coefficient in the multiplier 32 of the equalization circuit 30 by the integrated value.

  When the value of the equalization target value is a single value and Dmax [t] and Dmin [t] coincide with each other, the coefficient control circuit 50 performs the equalization signal in the same manner as a normal adaptive equalizer. To be close to the equalization target value. On the other hand, when the equalization target is wide and the equalization signal is between the upper limit and the lower limit of the equalization target value, the equalization error ε [t] becomes 0. Do not change. Therefore, the adaptive equalizer can avoid emphasizing the noise by forcibly correcting the shift without forcibly correcting the shift even when a shift occurs in the resolution of the reproduction signal, for example.

  In the present embodiment, the equalization target has a width at least partially, and when the equalization signal is within the range of the equalization target width, the equalization error is regarded as 0, and each equalization circuit 30 The coefficient of the multiplier 32 is controlled. By giving a wide range to the equalization target, even when a reproduction signal having a resolution of 70% or 60% is input, a coefficient for obtaining an equalization signal having a histogram as shown in FIG. Can be obtained. Further, even when a gradual change appears in the resolution of the reproduction signal, an appropriate equalized signal can be obtained. As a result, the determination error in the Viterbi detector 40 can be further reduced as compared with the first embodiment.

  In the second embodiment, the example in which the temporary determination circuit 70 is used and the temporary determination circuit 70 performs data determination to generate the equalization target value has been described. However, when the equalization target value is generated, the temporary determination circuit 70 is not necessarily required, and the equalization target value can be generated without using the temporary determination circuit 70. FIG. 8 shows another example of the data reproducing apparatus. The data reproducing apparatus having the configuration shown in FIG. 8 needs to generate an equalization target value using the determination data output from the Viterbi detector 40 and to correct a delay amount associated with a delay in the equalization target generation. Except for this point, the same operation as the data reproducing apparatus shown in FIG. 4 is performed.

  Instead of data relating to the internal state from the temporary determination circuit 70, the equalization target generation circuit 60 is provided with three bits of determination data via the delay circuit 31. When the Viterbi detector 40 determines that the shortest mark length is 2T, only six types (000, 001, 011, 111, 110, 100) appear as continuous 3-bit data. The equalization target generation circuit 60 treats these six types as S0, S1, S3, S5, S4, and S2, respectively, and, based on the state transition diagram of FIG. 6, similarly to the operation in the second embodiment. Generate a value. The delay until the equalization target value is generated is the delay of the equalization signal input to the equalization error selection circuit 51 in accordance with the input delay of the equalization target value in the adaptive equalizer shown in FIG. Correction can be made by increasing the amount and increasing the delay amount of the reproduced signal after sampling input to each of the correlators 52.

  Although the present invention has been described based on the preferred embodiments, the data reproducing apparatus and the reproducing method of the present invention are not limited to the above embodiments, and various modifications and changes can be made to the configuration of the above embodiments. Changes are also included in the scope of the present invention.

1 is a block diagram showing a data reproduction apparatus according to a first embodiment of the present invention. The graph which shows the histogram of an equalization signal sample value. The trellis diagram which shows operation | movement of a Viterbi detector. The block diagram which shows the data reproduction apparatus of 2nd Embodiment of this invention. The state transition diagram which shows the data temporary determination in a temporary determination circuit. The figure which shows a state transition and an equalization target value. The block diagram which shows the structure of an adaptive equalizer. The block diagram which shows the data reproduction apparatus of another example of 2nd Embodiment of this invention. 1 is a block diagram showing a general data reproducing apparatus. A state transition diagram explaining operation of a general data reproducing device. The trellis diagram explaining operation | movement of a general data reproducing | regenerating apparatus.

Explanation of symbols

10: A / D converter 20: synchronous clock extraction circuit 30: equalization circuit 31: delay circuit 32: multiplier 33: adder 40: Viterbi detector 41: branch metric calculation circuit 42: path metric calculation circuit 43: path Memory 44: Reference value selection circuit 50: Coefficient control circuit 51: Equalization error selection circuit 52: Correlator 53: Integrator 60: Equalization target generation circuit 70: Temporary determination circuit

Claims (11)

Equalization means for performing equalization processing on an input signal having a predetermined characteristic and generating an equalized signal;
A maximum likelihood detector that outputs, as reproduction data, a data string that provides the maximum likelihood for the equalized signal based on the equalized signal and a reference value;
At least a part of the reference value is selectable within a predetermined range, and the reference value for selecting the reference value from the predetermined range is selected for the selectable reference value according to the equalization signal. A data reproducing apparatus comprising a selection circuit.   The data reproduction device according to claim 1, wherein the reference value selection circuit selects, as the reference value, a value that minimizes a difference from the equalized signal among values selectable in the predetermined range.   The data reproduction device according to claim 1, wherein the reference value selection circuit selects a value of the equalization signal as the reference value when the equalization signal is a value within the predetermined range.   The reference value selection circuit selects the upper limit of the predetermined range as the reference value when the equalization signal is larger than the upper limit of the predetermined range, and the equalization signal is lower than the lower limit of the predetermined range. The data reproducing apparatus according to claim 3, wherein when it is smaller, the lower limit of the predetermined range is selected as the reference value. The equalization means performs an equalization process on the input signal, an equalization target generation circuit that generates an equalization target value based on a result of data discrimination of the equalization signal, and the equalization target An equalization parameter control circuit for controlling an equalization parameter in the equalization process based on a value and the equalization signal;
At least a part of the equalization target value can be selected from a predetermined range, and the equalization parameter control circuit uses the equalization target value selectable from the predetermined range as the equalization signal. 5. The data according to claim 1, wherein an equalization target is selected from the range of the equalization target value and the equalization parameter is controlled based on the selected equalization target. Playback device.   6. The data reproducing apparatus according to claim 5, wherein the equalization parameter control circuit selects, as an equalization target, a value that minimizes a difference from the equalization signal from the range of the equalization target value.   The apparatus further includes a provisional determination circuit that performs provisional determination of a data string based on the equalization signal, and the equalization target generation circuit generates the equalization target value based on data provisionally determined by the provisional determination circuit. The data reproducing device according to claim 5 or 6.   The data reproduction apparatus according to claim 5, wherein the equalization target generation circuit generates the equalization target value based on reproduction data output from the maximum likelihood detector. Performing an equalization process on an input signal having a predetermined characteristic to generate an equalized signal;
Outputting, as reproduction data, a data string that provides the maximum likelihood for the equalized signal based on the equalized signal and a reference value;
Selecting at least a part of the reference value within a predetermined range, and selecting the reference value from the predetermined range for the selectable reference value according to the equalization signal; A data reproduction method comprising: Generating the equalized signal comprises:
Generating an equalization target value in the equalization process based on a result of data discrimination of the equalization signal;
At least a part of the equalization target value can be selected from a predetermined range, and the equalization target value selectable from the predetermined range is determined according to the equalization signal. The method for reproducing data according to claim 9, further comprising: selecting an equalization target from the range and controlling an equalization parameter in the equalization process based on the selected equalization target.   11. The data reproduction method according to claim 10, wherein in the step of controlling the equalization parameter, a value that minimizes a difference from the equalization signal is selected from the range of the equalization target value as an equalization target. .

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