JP4009965B2 - Viterbi decoding method - Google Patents

Description

  The present invention relates to a Viterbi decoding method, and more particularly to a Viterbi decoding method for decoding recorded data from a digital recording medium such as an optical disk or a magnetic disk.

  In a reproducing apparatus for a digital recording medium such as an optical disk or a magnetic disk, since the asymmetry of the reproduction signal occurs due to the length and depth of the recording pit, the detection circuit detects the digital signal by slicing the reproduction signal at a predetermined threshold value. Conventionally, a device (auto slicer) that controls the slice position based on the asymmetric component of the reproduction signal has been used. Conventionally, in order for the Viterbi decoder to cope with such asymmetry of the reproduction signal, the asymmetry amount of the pit information is detected, corrected pit information is generated based on the asymmetry amount, and this corrected pit information is Viterbi decoded. An "optical information reproducing apparatus" (Japanese Patent Laid-Open No. 6-150549) is known which is demodulated by a detector.

JP-A-6-150549

  However, according to the invention described in Japanese Patent Application Laid-Open No. 6-150549, it is difficult to follow the characteristic change in the recording area only by correction in the area where the known pits are recorded. Difficulties in media application are expected.

  For example, an isolated waveform having a value of approximately 1, 1, 1, 1 with respect to an isolated waveform having a width of 1T (T is a bit period: the same applies hereinafter), a so-called transmission characteristic is a partial response (hereinafter abbreviated as PR). When waveform equalization is performed so as to be (1, 1, 1, 1), for example, when the level (peak value) of the reproduced waveform is approximately −2, −1, 0, 1, 2, symmetry FIG. 10 shows a result obtained by sampling a good reproduction signal with a bit period T, that is, measuring a peak value histogram at an input position to the Viterbi decoder.

  However, non-linear distortion that makes it impossible to equalize the PR (1, 1, 1, 1) waveform is generated depending on the excess or deficiency of power during recording or changes in the characteristics of the medium. As a result, FIG. In some cases, only a reproduced waveform with very poor symmetry as shown in the figure can be obtained. In the example of FIG. 11, the waveform equalizer operates to converge the waveform to the levels of −2, −1, 0, 1 and 2, and as a result, the variance of the samples to be converged to the level of 2 is large. Therefore, there is a problem that a conventional Viterbi decoder cannot perform a satisfactory decoding operation for an input wave having such a large nonlinear distortion.

  The present invention has been made in view of the above points, and when reproducing recorded data recorded on a recording medium using the Viterbi algorithm, the recording power, the irregularity of the recording mark shape due to the medium characteristics, It is an object of the present invention to provide a Viterbi decoding method capable of maintaining good reproduction performance even when nonlinear distortion of a reproduction waveform caused by reproduction characteristics occurs.

In order to achieve the above object, the present invention provides a Viterbi decoding method having the following configuration.
(1) a first step of generating a selection signal by calculating a branch metric using five target values for input data;
A second step of outputting the decoded data sequence obtained by Viterbi decoding the input data based on the selection signal,
The decoded data series output from the path memory is input to four delay elements connected in four stages, and is sequentially delayed by one bit period from the four delay elements to generate four output delay signals. 3 steps,
A fourth step of generating a composite signal obtained by adding the four output delay signals generated in the third step;
When the input data at a time point a predetermined bit period before the input data is estimated and the combined signal obtained in the fourth step is 0, the first target value of the five target values Is the first estimated data, and when it is 1, the second target value of the five target values is the second estimated data, and when it is 2, the third target value of the five target values is the third The target value is the third estimated data. When the target value is 3, the fourth target value of the five target values is the fourth estimated data. When the target value is 4, the fourth target value of the five target values is A fifth step of outputting a target value of 5 as fifth estimated data;
A sixth step of outputting the input data as delayed input data delayed to the same time as the first to fifth estimated data;
Output five first data obtained by correcting a target value using a difference between the estimated data of any one of the first to fifth target values and the delayed input data as a target value error. 7 steps,
Of the five first data, five second data are generated as corrected target values corresponding to the five first data so that the target values are symmetric with respect to the median target value. And an eighth step to
When the target value error obtained in the seventh step is less than or equal to a predetermined threshold, the five first data are output for calculating the branch metric, and the target value error is less than the predetermined threshold. A Viterbi decoding method comprising: a ninth step of outputting the five second data for the calculation of the branch metric when exceeding.

  According to the present invention, the branch metric calculation is performed based on the plurality of first target values that are close to the plurality of average values having the highest appearance frequency (having peaks in the histogram). However, accurate Viterbi decoding can be performed with a smaller error rate than in the past.

  In addition, according to the present invention, branch metric calculation based on a plurality of initial target values is performed at the time of calculation start and at the time of non-convergence of error calculation. Can do.

  Further, according to the present invention, when the equalized waveform (input data) input to the Viterbi decoder is greatly distorted, each target value is centered on the target value of the median value among the plurality of first target values. Since the branch metric calculation that minimizes the influence of the distortion of the input data can be performed based on the corrected target value corresponding to each of the plurality of first target values so that the value of Even for input data, accurate Viterbi decoding can be performed without causing asymmetry in branch metric error calculation.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a Viterbi decoder relevant to the present invention. As shown in the figure, in this embodiment, a branch metric arithmetic circuit 11 to which input data y _(k) is supplied via an input terminal 10, a path memory 12 for outputting a decoded data sequence, and a path memory 12 A delay circuit 13 having a delay time determined by the length of the data, a data estimation circuit 14 that outputs estimated data Y _(ki) , and a target value calculation circuit 15 that supplies a target value to the branch metric calculation circuit 11 Has been. This embodiment is characterized in that a delay circuit 13, a data estimation circuit 14, and a target value calculation circuit 15 are provided in a Viterbi decoding circuit including a conventional branch metric calculation circuit 11 and a path memory 12.

  In this embodiment, in a reproducing apparatus for a recording medium on which a digital signal in which the shortest recording inversion interval is limited to 3T is recorded, transmission is performed so that the transmission characteristic is substantially PR (1, 1, 1, 1). A case where the present invention is applied to road equalization will be described as an example. Examples of the recording medium in which the shortest recording inversion interval is limited to 3T include a compact disc (CD) and a DVD (Digital Versatile Disc). In the present embodiment, the case where the shortest recording inversion interval is set to 3T will be described. However, the present invention is applicable to other recording modulation and transmission path equalization methods.

  FIG. 2A shows a response waveform having a value of approximately 1, 1, 1, 1 with respect to an isolated wave having a width of 1T, ie, waveform equalization so as to have a so-called PR (1, 1, 1, 1) characteristic. The recording waveform in the case of recording is shown, and FIG. In this embodiment, as shown in FIG. 2 (b), the waveform is equalized so that the level (peak value) of the reproduced waveform is approximately -2, -1, 0, 1, 2.

  FIG. 3 shows a state transition diagram corresponding to FIG. In the figure, S0, S1, S2, S3, S4, and S5 indicate the state of input data (similar to decoded data), and the symbol attached to the arrow between states is the input bit (input) On the right side, the output peak value is shown. FIG. 4 shows a decoding trellis of PR (1, 1, 1, 1) corresponding to the state transition diagram of FIG. The symbols attached to the arrows between the states indicate the 1-bit value of the input data on the left and the output peak value on the right as in FIG.

The Viterbi decoder shown in FIG. 1 is a circuit that performs Viterbi decoding using PR (1, 1, 1, 1), and the branch metric calculation circuit 11 therein is represented by the state transition diagram of FIG. A waveform obtained by sampling a reproduced waveform subjected to waveform equalization at a bit period interval is received as input data y _(k) via a terminal 10, and a five-value target value TU is output from a target value calculation circuit 15 described later. , MU, ZE, ML, TL are received, branch metric calculation is performed based on these, and two selection signals 0 and 1 are output. The present embodiment is characterized in that the target value, which has been a fixed value in the past, varies based on the target value error signal.

FIG. 5 shows a circuit diagram of an example of the branch metric calculation circuit 11. In the figure, target values TU, MU, ZE, ML, and TL are the five-value peak values “2”, “1”, “0”, “−1”, “-1” shown in the decoding trellis of FIG. -2 "corresponding to the average value. The subtracter 21 ₁ performs subtraction of subtracting the target value TL from the input data y _(k), the subtractor 21 ₂ and 21 ₃ performs a subtraction to subtract the target value ML from the input data y _(k), the subtractor 21 ₄ and 21 ₅ performs a subtraction to subtract the target value ZE from the input data y _(k), the subtractor 21 ₆ and 21 ₇ performs a subtraction to subtract the target value MU from the input data y _(k), the subtracter 21 ₈ input data Subtraction is performed by subtracting the target value TU from y _(k) .

A difference value (error signal) between the input data y _(k) taken out from each of the subtracters 21 _{1 to} 21 ₈ and the corresponding target value is set to 2 by the corresponding square circuits 22 _{1 to} 22 _8. After being multiplied, the signals are supplied to adders 23 ₁ to 23 ₈ , and metrics L _{0 (k−1)} and L _{1 (k− )} at time k−1 in the states S0, S1, S2, S3, S4, and S5. ₁₎ , L _{2 (k-1)} , L _{3 (k-1)} , L _{4 (k-1)} , and L _{5 (k-1)} are added. That is, the adders 23 ₁ and 23 ₃ add the output signals of the squaring circuits 22 ₁ and 22 ₃ and the metric L _{0 (k−1),} and the adder 23 ₂ outputs the output signals of the squaring circuit 22 ₂ and the metric L _{1 (k-1)} is added, and the adders 23 ₄ , 23 ₅ , and 23 ₇ respectively output the output signals of the square circuits 22 ₄ , 22 ₅ , and 22 ₇ and the metrics L _{2 (k−1)} and L _{3 (k -1)} and L _{4 (k-1),} and the adders 23 ₆ and 23 ₈ add the output signals of the square circuits 22 ₆ and 22 ₈ and the metric L _{5 (k-1)} .

The comparison circuit 24 compares the levels of the output signals of the adders 23 ₁ and 23 _{2. When} the output signal of the adder 23 ₁ is smaller than the output signal of the adder 23 ₂ , the selection circuit 25 adds the adder 23 _1. Is output as the metric L _{0 (k)} at time k in the state S0, and in the opposite case, the output signal of the adder 23 ₂ is output as the metric L _{0 (k)} from the selection circuit 25. . Time k represents an arbitrary time after one bit period T from time k-1.

On the other hand, the comparator circuit 27 compares the two output signals of the adders 23 ₇ and 23 _8, the adder 23 ₇ adder 23 ₇ from the selection circuit 26 when towards the output signal is less than the output signal of the adder 23 ₈ the output signal, the selected output as metric L _{5 (k)} at time k in the state S5, in the case of the reverse to output the output signal of the adder 23 ₈ from the selection circuit 26 metric L ₅ as _(k) .

Further, adders 23 ₃ , 23 ₄ , 23 ₅ and 23 ₆ are connected to metrics L _{3 (k)} , L _{1 (k)} and L _{4 (k)} at time k in states S3, S1, S4 and S2, respectively. And L2 _(k) are extracted. Further, the selection signals 0 and 1 are extracted from the comparison circuits 24 and 27, respectively. These selection signals are signals indicating which signal is selected in the selection circuits 25 and 26.

As a result, the metrics L _{0 (k)} , L _{1 (k)} , L _{2 (k)} , L at time k in the states S 0, S 1, S 2, S 3, S 4, and S 5 output from the branch metric calculation circuit 11. L _{3 (k)} , L _{4 (k)} , and L _{5 (k)} are each expressed by the following equations.
L0 _(k) = min [[L0 _(k-1) + (y _(k) -(-2)) ² }, [L1 _(k-1) + (y _(k) -(-1) ) ² ]]
L1 _(k) = L2 _(k-1) + (y _(k) -(0)) ²
L2 _(k) = L5 _(k-1) + (y _(k) -(1)) ²
L3 _(k) = L0 _(k-1) + (y _(k) -(-1)) ²
L4 _(k) = L3 _(k-1) + (y _(k) -(0)) ²
L5 _(k) = min [[L5 _(k-1) + (y _(k) -(2)) ² }, [L4 _(k-1) + (y _(k) -(1)) ² ]]
However, min [a, b] is an operator that outputs the smaller of a and b.

The selection signals 0 and 1 extracted from the branch metric calculation circuit 11 having the above-described configuration are supplied to the path memory 12 as shown in FIG. 1, where a Viterbi-decoded decoded data sequence is generated. For example, as shown in the block diagram of FIG. 6, the path memory 12 includes n selectors 31 _{1 to} 31 _n that perform an operation of selecting one of two input signals by a selection signal 0, and two by a selection signal 1. N selectors 32 _{1 to} 32 _n that perform an operation of selecting one of the input signals, and delay elements 33 _{1 to} 33 ₆ , 34 _{1 to} 34 ₆ , and 35 _{1 to} 35 ₆ each having a delay time of a bit period T And the majority decision circuit 36.

6, 0 input to the selector 31 ₁ , ₁ input to the delay elements 33 ₂ and 33 ₃ , 0 input to the delay elements 33 ₄ and 33 _5, and input to the selector 32 ₁ , respectively. The 1-bit values of 0 and 1 are finally extracted from the majority circuit 36 as one decoded data series by the decoding operation in the path memory 12. Here, each 1-bit value corresponds to the value of the decoding trellis shown in FIG.

In this path memory 12, the selector 31 ₁ outputs L _{0 (k−1)} + (y _(k) − (− 2)) ² as L _{0 (k) in the} metric calculation. The bit value 0 is selected by the selection signal 0, and the bit value 1 is selected by the selection signal 0 when L1 _(k-1) + (y _(k) -(-1)) ² is output. . On the other hand, in the selector 32 ₁ , when L _{5 (k−1)} + (y _(k) − (− 2)) ² is output as L _{5 (k) by the} metric calculation, the selection signal 1 is used. When bit value 1 is selected and L _{4 (k−1)} + (y _(k) − (− 1)) ² is output, bit value 0 is selected. Similarly, the other selectors perform a selection operation based on the selection signal and perform Viterbi decoding based on the decoding trellis shown in FIG.

The number of selectors 31 _{1 to} 31 _n , 32 _{1 to} 32 _n , delay elements 33 _{1 to} 33 ₆ , 34 _{1 to} 34 ₆ , 35 _{1 to} 35 _6, etc. is determined by the decoding performance. Is selected to be about 32.

The decoded data series extracted from the path memory 12 in this way is output from the output terminal 16 of FIG. 1 and supplied to the data estimation circuit 14. The data estimation circuit 14 outputs the estimated data Y _(ki) before time i from k to the target value calculation circuit 15 according to the length of the path memory 12.

FIG. 7 shows a block diagram of an example of the data estimation circuit 14. As shown in the figure, in PR (1, 1, 1, 1), the data estimation circuit 14 includes four-stage cascaded delay elements 41, 42, 43 and 44 driven by a clock having a bit period T. , An adder 45 that adds the delayed signals from the delay elements 41 to 44 to form one combined signal, and an estimated data converter that receives the combined signal from the adder 45 as input and outputs estimated data Y _(ki) 46.

The operation of the data estimation circuit 14 will be described. The decoded data sequence output as a bit string (binary string) is sequentially delayed by the bit period T by the delay elements 41 to 44, and each of the delay elements 41 to 44 is delayed. The output delay signal is added and synthesized by the adder 45 to be a synthesized signal, which is then supplied to the estimated data converter 46. The estimated data converter 46 converts the output value of the adder 45 and outputs one of the target values TU, MU, ZE, ML, and TL in FIG. 5 as estimated data Y _(ki) .

Data conversion by the estimated data converter 46 is performed according to the following rules. That is, when all the output signals of the delay elements 41 to 44 are “0” (0000), the value of the output combined signal of the adder 45 is “0”. At this time, the estimated data converter 46 is set to the target value. TL is output as estimated data Y _(ki) . Further, among the output signals of the delay elements 41 to 44, when the output signal of the delay element 41 or 44 is “1” and the remaining three output signals are “0” (1000 or 0001), addition is performed. the value of the output composite signal bowl 45 is "1", the estimated data converter 46 at this time outputs a target value ML as estimation data Y _(ki).

Among the output signals of the delay elements 41 to 44, the output signals of the delay elements 41 and 42 or the output signals of the delay elements 43 and 44 are “1”, and the remaining two output signals are “0”. By the time (1100 or 0011), the value of the output composite signal of the adder 45 is "2", the estimated data converter 46 at this time outputs a target value ZE as estimation data Y _(ki). Further, among the output signals of the delay elements 41 to 44, when the output signal of the delay element 41 or 44 is “0” and the remaining three output signals are “1” (1110 or 0111), addition is performed. The value of the output combined signal of the unit 45 is “3”. At this time, the estimated data converter 46 outputs the target value MU as the estimated data Y _(ki) , and all the output signals of the delay elements 41 to 44 are “1”. (1111), the value of the output combined signal of the adder 45 is “4”. At this time, the estimated data converter 46 outputs the target value TU as estimated data Y _(ki) . The above is summarized as shown in Table 1.

That is, the data estimation circuit 14 estimates that the data before the time i from the time point k is the target value TL (corresponding to the conventional target value -2) when four 0s are continued as the decoded data series. Similarly, when 1 is one such as 0001 and 1000, the target value ML (corresponding to the conventional target value -1), and when two 1s continue such as 1100 and 0011, the target value ZE (the conventional target value). Is equivalent to a value of 0) and output as estimated data Y _(ki) . Since the output of the Viterbi decoder has a low bit error, the estimation data can be obtained very accurately.

The estimated data Y _(ki) output from the data estimation circuit 14 is supplied to the target value calculation circuit 15 as shown in FIG. Further, in this target value calculation circuit 15, the input data y _(k) to the branch metric calculation circuit 11 is estimated by the delay circuit 13 determined by the length of the path memory 12 and output from the data estimation circuit 14. Delayed input data y _(ki) delayed until the same time as data Y _{(i-1 )} is input.

The target value calculation circuit 15 updates the target value based on these input data Y _(ki) and y _(ki) , and outputs it to the branch metric calculation circuit 11. FIG. 8 shows a circuit diagram of an example of the target value calculation circuit 15. As shown in the figure, the target value calculation circuit 15, a subtracter 51 for performing error calculation, a multiplier 52 for multiplying the correction coefficient, the selector 53 and 54 selectively operated by the estimation data Y _(ki), an adder 55 _to 554 _5, a delay element 56 ₁ to 56 ₅ which constitute the adder 55 _to 554 ₅ and mutually independent feedback loop.

The operation of the target value calculation circuit 15 will be described. The delay input data y _(ki) extracted from the delay circuit 13 is supplied to the subtractor 51, where it is selected by the selector 54 based on the estimated data Y _(ki) . After being subtracted from the delay element output signal of any one of the delayed delay elements 56 _{1 to} 56 ₅ to obtain the target value error signal, the multiplier 52 multiplies the correction coefficient G by the multiplier 52 and supplies the signal to the selector 53. Then, it is selectively input to any one of the adders 55 _{1 to} 55 ₅ according to the estimated data Y _(ki) .

For example, if the target value TL is estimated as the estimated data Y _(ki), since selecting a target value TL of 1 bit period T before the selector 54 is taken out from the delay element 56 _{5 (k-1),} subtraction A target value error signal represented by [y _(ki) −TL _(k−1) ] is taken out from the multiplier 51, multiplied by a correction coefficient G by a multiplier 52, and [G (y _(ki) −TL ₍ after being a signal represented by _k-1))], and the selected input to the adder 55 ₅ by selector 53, is added to the retrieved from the delay element 56 ₅ target value TL _(k-1) . Accordingly, the following equation TL from the adder _{55 5 (k) = TL (} k-1) + G (y (ki) -TL (k-1))
The target value TL _(k) after correction expressed by the following is extracted and output to the branch metric calculation circuit 11.

The same applies to the case where other target value as the estimated data Y _(ki) is estimated, along with when the target value TU is estimated selector 53 outputs the input signal to the adder 55 _1, the selector 54 selects the output signal of the delay element 56 _1, along with when the target value MU is estimated selector 53 outputs the input signal to the adder 55 _2, the selector 54 selects the output signal of the delay element 56 ₂ , along with when the target value ZE is estimated selector 53 outputs the input signal to the adder 55 _3, the selector 54 selects the output signal of the delay element 56 _3, when the target value ML is estimated selector 53 outputs the input signal to the adder 55 _4, the selector 54 selects the output signal of the delay element 56 _4.

Incidentally, the target value calculation circuit 15, an initial target value is input, it is held in the delay element 56 ₁ to 56 _5, calculation start time and a large during non-convergence of the error operation caused by such no-signal state, initial In order to use the target value, for example, an initial target value selection signal is input from a system controller (not shown), a no-signal detection circuit, or the like, and the initial target value is used as the target value.

  The five updated target values extracted from the target value calculation circuit 15 and supplied to the branch metric calculation circuit 11 in this way are data input to the Viterbi decoder and have the highest appearance frequency (in the histogram). It is close to 5 average values (with peaks) and good Viterbi decoding is possible. That is, according to the present embodiment, it is possible to expect a decoding performance improvement effect for a certain amount of nonlinear distortion by correcting the target value.

  Next, another embodiment of the present invention will be described. In the above embodiment, the decoding performance improvement effect can be expected for a certain amount of nonlinear distortion. However, for a greatly distorted waveform, the branch metric error calculation has an asymmetry when the distortion is large, and correction is performed. There are cases where it cannot be exhausted. Therefore, in this embodiment, the circuit portion of the target value calculation circuit 15 of FIG. 1 is configured as shown in the block diagram of FIG. Is configured to perform target value control so as to operate normally.

  In FIG. 9, the updated five target values taken out from the target value calculation circuit 15 are supplied to the target value correction circuit 61 and corrected, while being directly supplied to the selector 62. The selector 62 selects a correction target value from the target value correction circuit 61 or a target value from the target value calculation circuit 15 in accordance with a selection signal from the comparator 63. The output target value of the selector 62 is output to the branch metric calculation circuit 11 shown in FIGS.

The target value correction circuit 61 is configured so that the values of the target values are symmetrical about the target value ZE of the median value among the five target values TU, MU, ZE, ML, and TL from the target value calculation circuit 15. A circuit for generating corrected target values TU ′, MU ′, ZE ′, ML ′, TL ′ corresponding to each of these five target values, specifically, the updated five target values TU, MU, ZE, Using ML and TL, for example, corrected target values TU ′, MU ′, ZE ′, ML ′, and TL ′ are generated and output by the following formula.
TU '=-TL' = (TU-TL) / 2
ML ′ = − ML ′ = (MU-ML) / 2
ZE '= ZE

  That is, the corrected target values TU ′ and TL ′ are the average of the target values TU and TL, and the corrected target values MU ′ and ML ′ are the average of the target values MU and ML. Needless to say, the target value correction circuit 61 can also generate a target correction value based on a more complicated mathematical expression.

The comparator 63 compares the target value error taken out from the subtractor 51 shown in FIG. 8 in the target value calculation circuit 15 with a threshold value set in advance from the outside, and when the target value error is equal to or smaller than the threshold value. The selector 62 selects the target value from the target value calculation circuit 15, and selects the correction target value from the target value correction circuit 61 when the target value error exceeds the threshold value. Since the target value error corresponds to the waveform distortion of the input data y _(k) of the Viterbi decoder, the target value supplied to the branch metric calculation circuit 11 is set when the waveform distortion is large enough to exceed a set value. By changing the target value to the corrected target value from the target value correcting circuit 61, the target value is made symmetric, and the branch metric calculation circuit 11 is operated normally against a large distortion.

  The present invention is not limited to the above embodiment. For example, the target value error may be a value multiplied by a coefficient, or a signal after an integration process or the like may be used. is there. The target value selected by the selector 62 may be an initial target value.

It is a block diagram of a Viterbi decoder related to the present invention. It is explanatory drawing of PR (1, 1, 1, 1). It is a state transition diagram of PR (1, 1, 1, 1). FIG. 4 is a decoding trellis diagram corresponding to FIG. 3. FIG. 2 is a circuit diagram of an example of a branch metric arithmetic circuit in FIG. 1. It is a block diagram of an example of the path memory in FIG. It is a block diagram of an example of the data estimation circuit in FIG. FIG. 2 is a circuit diagram of an example of a target value calculation circuit in FIG. 1. It is a block diagram which shows the other example of the Viterbi decoder relevant to this invention. It is a histogram of a symmetrical reproduction wave. It is an asymmetrical reproduction wave histogram.

Explanation of symbols

10 input data input terminal 11 branch metric computation circuit 12 path memory 13 delay circuit 14 the data estimation circuit 15 a target value calculating circuit 16 decodes the data sequence output terminal _{31 1 ~31 n, 32 1 ~32} n, 53,54,62 selector 41～44,56 _{1-56 5} delay elements 45, 55 _to 554 ₅ adder 46 estimation data converter 51 subtractor 52 multiplier 61 target value correction circuit 63 comparator

Claims (1)

A first step of calculating a branch metric using five target values for input data to generate a selection signal;
A second step of outputting the decoded data sequence obtained by Viterbi decoding the input data based on the selection signal,
The decoded data series output from the path memory is input to four delay elements connected in four stages, and is sequentially delayed by one bit period from the four delay elements to generate four output delay signals. 3 steps,
A fourth step of generating a composite signal obtained by adding the four output delay signals generated in the third step;
When the input data at a time point a predetermined bit period before the input data is estimated and the combined signal obtained in the fourth step is 0, the first target value of the five target values Is the first estimated data, and when it is 1, the second target value of the five target values is the second estimated data, and when it is 2, the third target value of the five target values is the third The target value is the third estimated data. When the target value is 3, the fourth target value of the five target values is the fourth estimated data. When the target value is 4, the fourth target value of the five target values is A fifth step of outputting a target value of 5 as fifth estimated data;
A sixth step of outputting the input data as delayed input data delayed to the same time as the first to fifth estimated data;
Output five first data obtained by correcting a target value using a difference between the estimated data of any one of the first to fifth target values and the delayed input data as a target value error. 7 steps,
Among the five first data, five second data are set as correction target values corresponding to the five first data so that the values of the target values are symmetric about the median target value. An eighth step of generating,
When the target value error obtained in the seventh step is less than or equal to a predetermined threshold, the five first data are output for calculating the branch metric, and the target value error is less than the predetermined threshold. A Viterbi decoding method comprising: a ninth step of outputting the five second data to perform the branch metric calculation when exceeding.

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