JP2006318547A - Prml decoding device and prml decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of exhibiting performance equal to bit detection when the target response of a long constraint length is used by using PRML (Partial Response Maximum Likelihood) detection using the target response of a short constraint length. <P>SOLUTION: The PRML bit detection is carried out based on a short constraint length by using a target response easier than a target response defined for target bit detection performance. Meanwhile, a differential metric is calculated by using the target response defined for target bit detection performance. Then, when the obtained differential metric is larger than its Euclidean distance indicating that a bit value is erroneous, a bit value detected in the PRML bit detection is corrected. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a PRML (Partial Response Maximum Likelihood) decoding apparatus and a PRML decoding method for, for example, a reproduction signal obtained by reproducing information recorded on a recording medium.

Japanese Patent Laid-Open No. 10-21651 JP 2003-141823 A JP 2003-151220 A JP 2003-178537 A

In recent years, a method called partial response maximum likelihood (PRML) detection has been adopted as a playback method for optical disks. This method is a method for detecting a partial response sequence that minimizes the Euclidean distance of a reproduction signal, and is a technique that combines a process of partial response and a process of maximum likelihood detection.
The partial response sequence is obtained by performing weighted addition defined by the target response to the bit sequence. In the optical disk system, PR (1, 2, 2, 1) is often used, and this returns a value obtained by adding a weight of 1, 2, 2, 1 to the bit sequence as a partial response value.
The partial response is a process of returning an output longer than 1 bit with respect to a 1-bit input, and the reproduced signal is sequentially converted into 1, 2, 2, A process obtained as a signal obtained by multiplying by 1 is expressed as PR (1, 2, 2, 1).
In the maximum likelihood detection, a distance called Euclidean distance is defined between two signals, and the distance between an actual signal and an expected signal from an assumed bit sequence is examined. This is a method for detecting a bit sequence that becomes closest. Here, the Euclidean distance is a distance defined as a distance obtained by adding the square of the amplitude difference between two signals at the same time over the entire time. Further, Viterbi detection, which will be described later, is used to search for a bit sequence that minimizes this distance.
In the partial response maximum likelihood detection combining these, the signal obtained from the bit information of the recording medium is adjusted by a filter called an equalizer so that it becomes a partial response process, and the resulting reproduced signal is assumed to be a bit sequence. The Euclidean distance with the partial response is checked, and a bit sequence having the closest distance is detected.

In order to search for a bit sequence in which the Euclidean distance is actually minimized, the above-described algorithm based on Viterbi detection is effective.
Viterbi detection uses a Viterbi detector consisting of a plurality of states configured in units of continuous bits of a predetermined length and branches represented by transitions between them, and all possible bit sequences are used. A desired bit sequence is efficiently detected from the inside.
In an actual circuit, for each state, a register that stores a partial response sequence and a Euclidean distance (path metric) of the signal up to that state called a path metric register, and a state called a path memory register. There are two registers, a register that stores the flow (path memory) of the bit sequence until the end, and for each branch, the partial response sequence at that bit called the branch metric unit and the Euclidean distance of the signal are calculated. Arithmetic units are provided.
In this Viterbi detector, various bit sequences can be associated in a one-to-one relationship by one of the paths passing through the state. In addition, the Euclidean distance between the partial response sequence passing through these paths and the actual signal is obtained by sequentially adding the above-mentioned branch metrics in the branches, that is, the transitions between the states constituting the above paths. Can be obtained.
Further, in order to select a path that minimizes the above Euclidean distance, paths having smaller path metrics are sequentially selected while comparing the magnitudes of path metrics of two or less branches that are reached in each state. This can be achieved. By transferring this selection information to the path memory register, information representing the path reaching each state in a bit sequence is stored. The value of the path memory register is converged to a bit series that finally minimizes the Euclidean distance while being sequentially updated, and the result is output. In this way, it is possible to efficiently search for a bit sequence that generates a partial response sequence having the closest Euclidean distance to the reproduction signal.

In such bit detection using PRML, it has been proposed to use SAM jitter described below as an index of the bit detection capability.
In bit detection by PRML, the Euclidean distance between the partial response sequence obtained from the correct bit sequence and the reproduced signal, that is, the path metric for the correct bit sequence is the Euclidean between the partial response sequence obtained from the erroneous bit sequence and the reproduced signal. Correct bit detection is performed when the distance, i.e., the path metric for an erroneous bit sequence, is smaller, and vice versa.
Therefore, the bit detection capability of PRML is determined by the difference between the former path metric and the latter path metric, that is, how far the differential metric is from 0. In other words, it can be estimated that the smaller the differential metric, the higher the possibility of error occurrence.
Among the bit sequences with errors, the most important sequence that occupies most of the errors is a bit sequence that gives another partial response sequence that has the shortest Euclidean distance from the partial response sequence obtained from the correct sequence. . Such a sequence is, for example, a case where there is an error of only 1 bit in PRML with a target response of PR (1, 2, 2, 1).
Therefore, in the bit detection by PRML, the magnitude of the difference between the partial response sequence obtained from the correct bit sequence and the Euclidean distance of the reproduced signal, the difference between the partial response sequence of the bit sequence having only one bit error and the Euclidean distance of the reproduced signal is It is considered that the ability of bit detection by PRML is determined.

Equation for difference in Euclidean distance between the two partial response sequences (a partial response sequence obtained from a correct bit sequence and a partial response sequence obtained from a bit sequence having a single bit error) defined by the reproduced signal Will be described.
First, the path metric for the correct bit sequence, that is, the Euclidean distance Mc between the partial response sequence obtained from the correct bit sequence and the reproduced signal is obtained by the following equation.
Mc = Σn _i ²
Here, _ni is noise in the sample of the reproduction signal, and is white noise according to a Gaussian distribution with an average of 0 and a standard deviation n. Further, Σ means addition for all channel clocks i.
The derivation of this equation is based on the assumption that PRML is obtained as a signal obtained by adding noise to a partial response sequence obtained from a correct bit sequence.

Next, a path metric for a bit sequence having a single bit error, that is, a Euclidean distance Me between a partial response sequence obtained from the bit sequence having a single bit error and a reproduced signal is given by the following equation.
Me = Σ (c _i −n _i ) ²
However, c _i is a coefficient of the target response, and if PR (1, 2, 2, 1), it becomes 1, 2, 2, 1, 0.
Therefore, the difference, that is, the differential metric dM is given by the following equation.
dM = Me−Mc = Σ | c _i | ² −2Σn _i · c _i
Here, Σ | c _i | ² corresponds to the Euclidean distance of the partial response sequence obtained from two bit sequences different by 1 bit. As mentioned earlier, an error occurs when this difference is negative. In addition, the probability that this difference is negative, the higher the standard deviation n of the noise n _i is the greater.
Therefore, this noise distribution n is an index that directly contributes to the bit error rate. However, n is not a detectable amount.
So, instead of n, using the differential metric dM and the known quantity Σ | c _i | ² as the detectable quantity,
j = √V (dM) / (2 · Σ | c _i | ² )
Can be used as an index that directly contributes to the bit error rate.
However, V (dM) represents the variance of the differential metric dM. Further, Σ is all addition for the channel clock i.
The jitter j defined as above is called SAM jitter.
If dM is substituted into the definition formula of j and transformed, the following formula is obtained.
j = √ (V (n _i ) · 2 · Σ | c _i | ² ) / (2 · Σ | c _i | ² )
= N / √ (2 · Σ | c _i | ² )
Here, √Σ | c _i | ² corresponds to the signal energy when a random bit sequence is equalized by the partial response channel. Therefore, it can be seen that the SAM jitter j is inversely proportional to the SN ratio.

As described above, when performing bit detection using PRML, it is understood that it is desirable to use an index that incorporates fluctuations in the amplitude axis direction as an index corresponding to the bit error rate. Specifically, the index obtained by dividing the standard deviation of the differential metric, which is the difference between the path metric of the correct bit sequence and the bit metric of the bit sequence having a single bit error, by the signal power, that is, the SAM jitter is effective. I know that there is.
Strictly speaking, the SAM jitter cannot be defined unless the correct bit sequence is known. However, as shown in Patent Documents 1, 2, 3, and 4, the SAM jitter is finally detected by Viterbi decoding. A technique using SAM jitter assuming that the bit sequence is a correct bit sequence is known.

The PRML detection method is widely used and exhibits effects over many fields such as communication information, magnetic tape, and hard disk. However, in any field, with the recent increase in density, PRML detection with a long constraint length is required. For example, in an optical disk system, the target response changes from PR (1, 2, 1) with a constraint length of 3 to PR (1, 2, 2, 1) with a constraint length of 4 which is currently mainstream, Proposals for adaptively correcting PR (1, 2, 2, 2, 1) with a constraint length of 5 and PR (0, 1, 2, 2, 1, 0) with a constraint length of 6 have been proposed.
The reason why such a target response with a long constraint length is required is derived from the increase in the intersymbol interference length accompanying the increase in density. As the density increases, the bit length with respect to the resolution of the reproducing head, the pickup, and the like decreases relatively. Therefore, PRML detection with a long constraint length is indispensable for increasing the density.

On the other hand, when dealing with a target response having a long constraint length, the circuit scale of the PRML decoding apparatus increases, and the increase is estimated to be about twice as long as the constraint length increases by one.
Therefore, for example, when the current PR (1, 2, 2, 1) is changed to PR (1, 2, 2, 2, 1) or the like, the circuit scale is about twice as large. Such an increase in circuit scale is not a desirable direction from the viewpoint of reducing power consumption, and there is a problem that the more complicated the circuit scale, the more difficult the design becomes and the reduction in processing speed.

  Therefore, an object of the present invention is to realize a technique that exhibits the same performance as that of bit detection when a long constraint length target response is used by using PRML detection using a short constraint length target response.

  The PRML decoding apparatus according to the present invention includes a bit detection unit that detects a bit by performing a partial response equalization process and a Viterbi detection process on an input signal, and a bit pattern according to a predetermined rule in the bit sequence detected by the bit detection unit. In contrast, a differential metric calculation unit that calculates a differential metric different from the differential metric used for bit detection by the bit detection unit, a differential metric obtained by the differential metric calculation unit, Bit correction means for correcting the bit sequence detected by the bit detection means based on the comparison result with the Euclidean distance corresponding to the differential metric.

The bit pattern according to the predetermined rule is a bit pattern according to a predetermined run-length rule, which satisfies the run-length rule even if a predetermined one bit is changed.
When the bit detection means performs Viterbi detection processing for a signal that complies with the d1 rule as the run-length rule, the bit pattern according to the predetermined rule is a bit pattern of 5 bits or more, and a plurality of the above-described bit patterns. As the bit pattern, a bit pattern including 11000, a bit pattern including 11100, a bit pattern including 00001, and a bit pattern including 00111 are set.
The differential metric calculated by the differential metric calculating means is a bit metric different from the path metric corresponding to the bit series detected by the bit detecting means by only one bit from the bit series detected by the bit detecting means. Is a differential metric obtained by an operation different from the differential metric used for bit detection by the bit detection means.
In addition, the bit correction unit may be configured to output the bit when the differential metric value obtained by the differential metric calculation unit exceeds a Euclidean distance between two partial response sequences formed by two bit sequences different by one bit. A predetermined bit value of the bit pattern in the detected bit sequence detected by the detecting means is inverted.

The bit pattern according to the predetermined rule is a bit pattern according to a predetermined run length rule, including one or more consecutive shortest run length runs, and shifting the shortest run length run by 1 bit. Is also a bit pattern satisfying the run length rule.
When the bit detection means performs a Viterbi detection process for a signal that complies with the d1 rule as the run length rule, the bit pattern according to the predetermined rule is a bit pattern of 7 bits or more, and a plurality of the above-described bit patterns. As the bit pattern, a bit pattern including 001000, a bit pattern including 0001100, a bit pattern including 1110011, and a bit pattern including 1100111 are set.
The differential metric calculated by the differential metric calculating means includes a path metric corresponding to the bit sequence detected by the bit detecting means and a run of the shortest run length included in the bit sequence detected by the bit detecting means. Is a differential metric obtained by an operation different from the differential metric used for bit detection by the bit detection means.
Further, the bit correcting means may include two partial response sequences formed by two bit sequences in which the differential metric value obtained by the differential metric calculating device is shifted by 1 bit from the shortest run length run. When the Euclidean distance is exceeded, a predetermined bit value of the bit pattern in the detected bit sequence detected by the bit detecting means is inverted.

In addition, the bit correcting unit may be configured to detect a bit pattern in the detected bit sequence detected by the bit detecting unit when the differential metric value obtained by the differential metric calculating unit exceeds a minimum Euclidean distance determined by a target response. The predetermined bit value is inverted.
Further, the differential metric different from the differential metric used for bit detection by the bit detection means is longer than the constraint length necessary for calculating the differential metric used for bit detection by the bit detection means. It is a differential metric that requires a constraint length.
The differential metric used for bit detection by the bit detection means is a differential metric calculated from a reference level obtained from the target response PR (1, 2, 2, 1) having a constraint length of 4, The differential metric calculated by the differential metric calculation means is a differential metric calculated using a reference level obtained from a target response PR (1, 2, 2, 2, 1) having a constraint length of 5.
In this case, the differential metric calculated by the differential metric calculation means is a reference level obtained by applying a predetermined correction to the reference level obtained from the target response PR (1, 2, 2, 2, 1) having a constraint length of 5. Is a differential metric calculated using the above, and the predetermined correction of the reference level is, for each reference level, selecting a signal that corresponds to the reference level from among actually detected signals. The reference level is adaptively corrected using the low frequency component.

  The PRML decoding method of the present invention includes a bit detection step of performing bit response detection and Viterbi detection processing on an input signal to detect bits, and a bit pattern according to a predetermined rule in the bit sequence detected in the bit detection step. In contrast, a differential metric calculation step for calculating a differential metric different from the differential metric used for bit detection in the bit detection step, a differential metric obtained in the differential metric calculation step, and A bit correction step of correcting the bit sequence detected in the bit detection step based on a comparison result with the Euclidean distance corresponding to the differential metric.

  That is, in the present invention, PRML bit detection with a short constraint length is performed using a target response that is simpler than the target response assumed for the target bit detection performance, in particular, a target response with a short constraint length. . On the other hand, the differential metric is calculated using the target response assumed according to the target bit detection performance. If the obtained differential metric is larger than the Euclidean distance and indicates that the bit value is incorrect, the bit value detected by the PRML bit detection is corrected.

According to the present invention, in PRML detection in which a target response with a long constraint length is required, a target response that is simpler than the assumed target response, in particular, a target response with a shorter constraint length, is used. PRML bit detection by length is performed. On the other hand, the differential metric is calculated using the target response assumed according to the target bit detection performance. The obtained differential metric is larger than the Euclidean distance and the bit value is incorrect. , The bit value detected by PRML bit detection is corrected. As a result, there is an effect that highly accurate bit detection can be performed without significantly increasing the circuit scale of the PRML decoding device.
Further, for example, as a PRML decoding device corresponding to high density recording media, it is possible to simultaneously realize low power consumption while realizing high-accuracy bit detection without incurring an increase in circuit scale. Since it does not become complicated, design difficulty associated with higher density does not occur, and processing speed does not decrease. Therefore, the present invention is suitable for a system that intends to realize a high information recording density and a high transfer rate.

Embodiments of the present invention will be described below.
FIG. 1 is a block diagram showing an outline of a playback apparatus including a PRML decoding apparatus according to an embodiment.
As shown in FIG. 1, the reproduction apparatus of this example includes an optical pickup 1 that reproduces bit information from a recording medium such as an optical disc 90, and a preamplifier 2 that converts a signal read by the optical pickup 1 into a reproduction signal (RF signal). A / D converter 3 that performs A / D conversion of the reproduction signal, an equalizer 4 that adjusts the waveform of the reproduction signal for PLL processing, a PLL circuit 5 that reproduces a clock from the reproduction signal, and PRML that detects bit information from the reproduction signal Decoding device 6; demodulator 8 such as RLL (1-7) pp demodulator that demodulates bit information; RS decoder 9 that corrects error of demodulated information; process error-corrected information and reproduce application data CPU block 10 and the like.

The optical disk 90 is assumed to be a ROM type disk, for example. Of course, there may be a write-once type disc or a rewritable type disc.
A reproduction signal (RF) reproduced from the optical disc 90 through the optical pickup 1 and the preamplifier 2 is numerically sampled by the A / D converter 3 (RF (Sampled)). This sampling is performed at the same timing as the clock synchronized with the channel bits reproduced by the PLL circuit 5.
The sampling information of the sampled reproduction signal is adjusted in waveform by the equalizer 4 and then input to the PRML decoding device 6 to determine bit information.
Here, the PRML decoding device 6 is configured to satisfy the d1 rule (minimum run length d = 1 and the shortest mark length is 2T) in accordance with the modulation method restriction at the time of recording, and the PRML target response is PR (1 , 2, 2, 1).
Note that the PRML decoding device 6 of this example can detect SAM jitter as a signal quality evaluation index for measuring the accuracy of bit detection.

  The bit information obtained by the PRML decoding device 6 is demodulated by the demodulator 8 according to the modulation method at the time of recording. Further, the RS decoder 9 decodes the Reed-Solomon code of the ECC block to correct the error, and the CPU block 10 Confirms that no error is detected in the error detection code in the EDC block, thereby restoring the original application data.

FIG. 2 shows the configuration of the PRML decoding device 6 shown in FIG.
The PRML decoding device 6 equalizes a waveform equalizer (equalizer) 20 that equalizes a channel response to a target response, a maximum likelihood detector 21 that performs Viterbi detection from the output of the equalizer 20, and another target response. An equalizer 26, a differential metric calculator (DMC) 27 that calculates a differential metric dM at the time of path comparison, a bit corrector 29, and a SAM jitter calculator 30 are configured.

The equalizer 20 equalizes the input signal (RF) to the target response PR (1, 2, 2, 1). The input signal RF that is PR-equalized by the equalizer 20 is supplied to the maximum likelihood detector 21.
The maximum likelihood detector 21 detects a bit sequence according to the d1 rule under the target response PR (1, 2, 2, 1), and sequentially outputs the detected bit values as a bit sequence.
When there is a d1 rule (minimum run length d = 1 and the shortest mark length is 2T) as the minimum run length rule, for example, the maximum likelihood detector 21 is composed of 6 states composed of 3 bits and 4 bits. 10 branches are prepared, and these branches are configured to connect between the states according to the D1 constraint.

  The equalizer 26 equalizes the input signal (RF) to the target response PR (1, 2, 2, 2, 1). The input signal RF that is PR-equalized by the equalizer 26 is supplied to a differential metric calculator 27.

The differential metric calculator 27 is supplied with the input signal PR-equalized to the target response PR (1, 2, 2, 2, 1) by the equalizer 26 and is detected by the maximum likelihood detector 21. A bit string (bit sequence) is supplied.
Then, the differential metric calculator 27 calculates a differential metric dM as the following value from the input signal.
dM = 1 · (q _n-0 −p _n-0 ) + 2 · (q _n−1 −p _n−1 ) + 2 · (q _n−2 −p _n−2 ) + 2 · (q _n−3 −p _n-3 ) + 1 · (q _n-4 -p _n-4 )
Where q _n is the output of the equalizer 26, _pn is the partial response output of the target response PR (1, 2, 2, 2, 1) obtained from the detection bit sequence by the maximum likelihood detector 21, and n is the time To express. Except for the positive and negative values, this value is equal to a value obtained by subtracting the Euclidean distance in a sequence different by 1 bit in PR (1, 2, 2, 2, 1) from a differential metric with a bit sequence different by 1 bit.

The bit corrector 29 performs bit detection again using the differential metric dM obtained by the differential metric calculator 27. That is, the detection bit detected by the maximum likelihood detector 21 is corrected and a corrected bit sequence is output.
The bit corrector 29 classifies the differential metric dM based on the 5-bit detection bit sequence input from the maximum likelihood detector 21 and redetects the bit value. By where 5 bits patterns are set to 11000,11100,00011,00111, if The size of the differential metric dM is larger than the Euclidean distance ^{d = (1 2 +2 2 +2} 2 +2 2 +1 2) = 14, The middle bit of the 5 bits of the detection bit sequence is corrected.

  The SAM jitter calculator 30 calculates the standard deviation for the differential metric dM supplied from the differential metric calculator 27 with the target response PR (1, 2, 2, 2, 1), thereby calculating the SAM jitter. Calculate Then, the value of SAM jitter is output as an evaluation value.

  In the configuration example of FIG. 2, the equalizer 20 and the maximum likelihood detector 21 correspond to the bit detection means of the present invention. The differential metric calculator 27 corresponds to the differential metric calculation means in the claims of the present invention. Further, the bit corrector 29 corresponds to the bit correcting means in the claims of the present invention.

Hereinafter, each part of FIG. 2 will be described in detail.
FIG. 3 shows an example of the equalizer 20 and the equalizer 26 shown in FIG. The equalizers 20 and 26 are constituted by flip-flops 31A to 31F, multipliers 32A to 32G, and an adder 33, and form a waveform equalization filter.
The input reproduction signal (reproduction signal RF (Sampled) supplied from the equalizer 4 to the PRML decoding device 6 in FIG. 1) branches through the flip-flops 31A to 31F into seven signals delayed by one clock at a time with the channel clock. Is done.
Next, the seven branched signals are amplified at different magnifications (coefficients k0 to k6) by multipliers 32A to 32G, respectively.
Finally, the signals amplified by the multipliers 32A to 32G are added by the adder 33, and the output is output as an equalized signal.

Here, the coefficients k0 to k6 of the multipliers 32A to 32G are coefficients that minimize the equalization error with respect to the target response of the equalized signal. It is desirable that this coefficient is automatically set by, for example, an LMS algorithm. When the LMS algorithm is used, each coefficient is obtained by the following calculation.
k0 = k0 + ε · r _n−3 · (p _n −q _n ),
k1 = k1 + ε · r _n−2 · (p _n −q _n ),
k2 = k2 + ε · r _n−1 · (p _n −q _n ),
k3 = k3 + ε · r _n−0 · (p _n −q _n ),
k4 = k4 + ε · r _{n + 1} · (p _n −q _n ),
k5 = k5 + ε · r _{n + 2} · (p _n −q _n ),
k6 = k6 + ε · r _{n + 3} · (p _n −q _n ),
However, ε is a feedback constant of about 0.001. r _n, p _n, q _n, the input signals of the time n, the partial response signal, which is the equalized signal.

The example of FIG. 3 is a case of a 7-tap equalizer using signals separated from 7 clocks. The number of taps does not necessarily have to be seven, and it can be changed according to the purpose by increasing it further if it eliminates intersymbol interference more accurately or by reducing it if the scale is reduced. Just do it.
In any case, the equalizer 20 may be any equalizer as long as partial response equalization can be realized with a target response of PR (1, 2, 2, 1).
The equalizer 26 may be any equalizer as long as partial response equalization can be realized with a target response of PR (1, 2, 2, 2, 1).

FIG. 4 shows an example of the maximum likelihood detector 21. The maximum likelihood detector 21 compares a branch by taking a branch metric and a branch metric calculation unit (BMC) 22 that calculates a branch metric for each branch. The path metric update unit (ACS) 23 performs path selection and path metric update, and the path memory update unit (PMEM) 24 updates the path memory according to the selected path information.
In the branch metric calculation unit 22, the partial response levels -3, -2, -2, -1 corresponding to the bit sequences 0000, 0001, 1000, 1001, 0011, 1100, 0110, 0111, 1110, 1111 , 0, 0, 1, 2, 2, 3 and the Euclidean distance between the input signals.
The path metric update unit 23 selects, for the bit string 0000, 0001, 1000, 1001, 0011, 1100, 0110, 0111, 1110, 1111, a path with a small path metric from the paths to reach this bit string, The branch metric is added and updated as the next path metric.
The path memory update unit 24 shifts the path memory of the path up to the bit string to the bit string 0000, 0001, 1000, 1001, 0011, 1100, 0110, 0111, 1110, 1111 and shifts the least significant bit. In addition, it is updated as the next path memory. Further, for example, the path memory that has reached the bit string 0000 is selected, and the most significant bit is output as the detection bit of the maximum likelihood detector 21.

FIG. 5 shows a configuration of the branch metric calculation block 22 in the maximum likelihood detector 21 having PR (1, 2, 2, 1) as a target response.
The branch metric calculation unit 22 includes reference value registers 41A to 41J, subtracters 42A to 42J, multipliers 43A to 43J, and branch metric registers 44A to 44J.
The branch metric calculation unit 22 receives the equalized signal qn obtained through the equalizer 20 described above.
The reference value register 41A stores a reference level _r0000 corresponding to the bit string 0000.
Reference value register 41B stores a reference level r ₀₀₀₁ corresponding to the bit string 0001.
Reference value register 41C stores the reference level r ₁₀₀₀ corresponding to the bit string 1000.
The reference value register 41D stores a reference level r ₁₀₀₁ corresponding to the bit string 1001.
The reference value register 41E stores a reference level r ₀₀₁₁ corresponding to the bit string 0011.
The reference value register 41F stores a reference level r ₁₁₀₀ corresponding to the bit string 1100.
The reference value register 41G stores a reference level r ₀₁₁₀ corresponding to the bit string 0110.
The reference value register 41H stores a reference level r ₀₁₁₁ corresponding to the bit string 0111.
The reference value register 41I stores a reference level r ₁₁₁₀ corresponding to the bit string 1110.
The reference value register 41J stores a reference level r ₁₁₁₁ corresponding to the bit string 1111.

Here, the target response is PR (1, 2, 2, 1), and the reference level r _ijkl for the bit string _ijkl is:
r ₀₀₀₀ = -3,
r ₀₀₀₁ = −2,
r ₁₀₀₀ = −2,
r ₁₀₀₁ = -1,
r ₀₀₁₁ = 0,
r ₁₁₀₀ = 0,
r ₀₁₁₀ = 1,
r ₀₁₁₁ = 2
r ₁₁₁₀ = 2
r ₁₁₁₁ = 3,
It becomes.

The branch metric register 44A stores a branch metric m ₀₀₀₀ between the signal qn and the reference level r ₀₀₀₀ .
The branch metric register 44B stores a branch metric m ₀₀₀₁ between the signal qn and the reference level r ₀₀₀₁ .
The branch metric register 44C stores a branch metric m ₁₀₀₀ between the signal qn and the reference level r ₁₀₀₀ .
The branch metric register 44D stores a branch metric m ₁₀₀₁ between the signal qn and the reference level r ₁₀₀₁ .
The branch metric register 44E stores a branch metric m ₀₀₁₁ between the signal qn and the reference level r ₀₀₁₁ .
The branch metric register 44F stores a branch metric m ₁₁₀₀ between the signal qn and the reference level r ₁₁₀₀ .
The branch metric register 44G stores a branch metric m ₀₁₁₀ between the signal qn and the reference level r ₀₁₁₀ .
The branch metric register 44H stores a branch metric m ₀₁₁₁ between the signal qn and the reference level r ₀₁₁₁ .
The branch metric register 44I stores a branch metric m ₁₁₁₀ between the signal qn and the reference level r ₁₁₁₀ .
The branch metric register 44J stores a branch metric m ₁₁₁₁ between the signal qn and the reference level r ₁₁₁₁ .

From the reference value register 41A to the branch metric register 44A,
From the reference value register 41B to the branch metric register 44B,
From the reference value register 41C to the branch metric register 44C,
From the reference value register 41D to the branch metric register 44D,
From the reference value register 41E to the branch metric register 44E,
From the reference value register 41F to the branch metric register 44F,
From the reference value register 41G to the branch metric register 44G,
From the reference value register 41H to the branch metric register 44H,
From the reference value register 41I to the branch metric register 44I,
From the reference value register 41J to the branch metric register 44J,
In each process, one subtractor 42 (42A to 42J) and one multiplier 43 (43A to 43J) are prepared.

Each subtracter (42A to 42J) receives an input signal qn and a reference level signal obtained from the corresponding register (41A to 41J), and outputs the difference.
Each multiplier (43A to 43J) outputs a value obtained by squaring the difference output from the corresponding subtracter (42A to 42J). The values output from the respective multipliers (43A to 43J) become the branch metrics m _{0000 to} m ₁₁₁₁ stored in the branch metric registers (44A to 44J).
In this case, the branch metric m _ijkl is
m _ijkl = (q _n −r _ijkl ) ²
It is. Here, q _n is an input signal at time n.

However, the branch metric is sufficient if the relative value is known, and therefore, there is no q _n ² term. Therefore, as shown in branch metric register 44A~44J in FIG. 5, the branch metric m _ijkl is
m _ijkl = −r _ijkl (2q _n −r _ijkl )
And it is sufficient. In this way, the capacity of the multiplier 43 can be reduced.
Instead of the multiplier 43, an absolute value calculator may be provided.

The branch metrics m _{0000 to} m ₁₁₁₁ obtained as described above and stored in the branch metric registers 44A to 44J are updated for each channel bit clock and output to the path metric update unit 23 in the next stage. .

FIG. 6 shows the path metric update unit 23 in the maximum likelihood detector 21 having PR (1, 2, 2, 1) as a target response.
The path metric update unit 23 shown in FIG. 6 includes path metric registers 51A to 51J and 52A to 52J, and flip-flops 53A to 53J.

The path metric register 51A stores the path metric pm ₀₀₀₀ of the surviving path in the branch b ₀₀₀₀ .
The calculation of the path metric of the path that reached the bit string 0000 is
pm ₀₀₀₀ = min (pm ₀₀₀₀ , pm ₁₀₀₀ ) + m ₀₀₀₀
It is represented by min (A, B) is an operation for selecting a smaller one of A and B.
That is, in the path metric register 52A, a smaller value of pm ₀₀₀₀ + m ₀₀₀₀ and pm ₁₀₀₀ + m ₀₀₀₀ is selected as the path metric pm ₀₀₀₀ of the path leading to the branch b ₀₀₀₀ .
The metrics m ₀₀₀₀ and m ₁₀₀₀ for calculating the path metric value are input from the branch metric calculation unit 22 of FIG. In FIG. 6, the branch metrics {m _ijkl } indicate the branch metrics m _{0000 to} m ₁₁₁₁ supplied from the branch metric registers 44A to 44J in FIG. The same applies to metrics m _ijkl in path metric registers 52B to 52J described later.
The value of the path metric register 52A latched by the flip-flop 53A is stored as the value of the path metric register 51A.

The path metric register 51B stores the path metric pm ₀₀₀₁ of the surviving path in the branch b ₀₀₀₁ .
The calculation of the path metric of the path reaching bit string 0001 is
pm ₀₀₀₁ = min (pm ₀₀₀₀ , pm ₁₀₀₀ ) + m ₀₀₀₁
It is represented by That is, in the path metric register 52B, a smaller value is selected from pm ₀₀₀₀ + m ₀₀₀₁ and pm ₁₀₀₀ + m ₀₀₀₁ as the path metric pm ₀₀₀₁ of the path leading to the branch b ₀₀₀₁ .
The value of the path metric register 52B latched by the flip-flop 53B is stored as the value of the path metric register 51B.

The path metric register 51C stores the path metric pm ₁₀₀₀ of the surviving path in the branch b ₁₀₀₀ .
The calculation of the path metric of the path reaching the bit string 1000 is
pm ₁₀₀₀ = pm ₁₁₀₀ + m ₁₀₀₀
It is represented by The path metric register 52C stores the path metric pm ₁₀₀₀ = pm ₁₁₀₀ + m ₁₀₀₀ of the path leading to the branch b ₁₀₀₀ .
The value of the path metric register 52C latched by the flip-flop 53C is stored as the value of the path metric register 51C.

The path metric register 51D stores the path metric pm ₁₀₀₁ of the surviving path in the branch b ₁₀₀₁ .
The calculation of the path metric of the path reaching the bit string 1001 is
pm ₁₀₀₁ = pm ₁₁₀₀ + m ₁₀₀₁
It is represented by The path metric register 52D stores the path metric pm ₁₀₀₁ = pm ₁₁₀₀ + m ₁₀₀₁ of the path leading to the branch b ₁₀₀₁ . The value of the path metric register 52D latched by the flip-flop 53D is stored as the value of the path metric register 51D.

The path metric register 51E stores the path metric pm ₀₀₁₁ of the surviving path in the branch b ₀₀₁₁ .
The calculation of the path metric of the path that reached the bit string 0011 is
pm ₀₀₁₁ = min (pm ₀₀₀₁ , pm ₁₀₀₁ ) + m ₀₀₁₁
It is represented by In the path metric register 52E, a smaller value is selected from pm ₀₀₀₁ + m ₀₀₁₁ and pm ₁₀₀₁ + m ₀₀₁₁ as the path metric pm ₀₀₁₁ of the path reaching the branch b ₀₀₁₁ . The value of the path metric register 52E latched by the flip-flop 53E is stored as the value of the path metric register 51E.

The path metric register 51F stores the path metric pm ₁₁₀₀ of the surviving path in the branch b ₁₁₀₀ .
The calculation of the path metric of the path reaching the bit string 1100 is as follows:
pm ₁₁₀₀ = min (pm ₀₁₁₀ , pm ₁₁₁₀ ) + m ₁₁₀₀
It is represented by In the path metric register 52F, a smaller value is selected from pm ₀₁₁₀ + m ₁₁₀₀ and pm ₁₁₁₀ + m ₁₁₀₀ as the path metric pm ₁₁₀₀ of the path to the branch b ₁₁₀₀ . The value of the path metric register 52F latched by the flip-flop 53F is stored as the value of the path metric register 51F.

The path metric register 51G stores the path metric pm ₀₁₁₀ of the surviving path in the branch b ₀₁₁₀ .
The calculation of the path metric of the path that reached the bit string 0110 is
pm ₀₁₁₀ = pm ₀₀₁₁ + m ₀₀₁₁
It is represented by The path metric register 52G stores the path metric pm ₀₁₁₀ = pm ₀₀₁₁ + m ₀₁₁₀ of the path leading to the branch b ₀₁₁₀ . The value of the path metric register 52G latched by the flip-flop 53G is stored as the value of the path metric register 51G.

The path metric register 51H stores the path metric pm ₀₁₁₁ of the surviving path in the branch b ₀₁₁₁ .
The calculation of the path metric of the path that reached the bit string 0111 is
pm ₀₁₁₁ = pm ₀₀₁₁ + m ₀₁₁₁
It is represented by The path metric register 52H stores the path metric pm ₀₁₁₁ = pm ₀₀₁₁ + m ₀₁₁₁ of the path to the branch b ₀₁₁₁ . The value of the path metric register 52H latched by the flip-flop 53H is stored as the value of the path metric register 51H.

The path metric register 51I stores the path metric pm ₁₁₁₀ of the surviving path in the branch b ₁₁₁₀ .
The calculation of the path metric of the path reaching the bit string 1110 is as follows:
pm ₁₁₁₀ = min (pm ₀₁₁₁ , pm ₁₁₁₁ ) + m ₁₁₁₀
It is represented by In the path metric register 52I, a smaller value is selected from pm ₀₁₁₁ + m ₁₁₁₀ and pm ₁₁₁₁ + m ₁₁₁₀ as the path metric pm ₁₁₁₀ of the path to the branch b ₁₁₁₀ . The value of the path metric register 52I latched by the flip-flop 53I is stored as the value of the path metric register 51I.

The path metric register 51J stores the path metric pm ₁₁₁₁ of the surviving path in the branch b ₁₁₁₁ .
The calculation of the path metric of the path that has reached the bit string 1111 is as follows:
pm ₁₁₁₁ = min (pm ₀₁₁₁ , pm ₁₁₁₁ ) + m ₁₁₁₁
It is represented by In the path metric register 52J, a smaller value is selected from pm ₀₁₁₁ + m ₁₁₁₁ and pm ₁₁₁₁ + m ₁₁₁₁ as the path metric pm ₁₁₁₁ of the path to the branch b ₁₁₁₁ . The value of the path metric register 52J latched by the flip-flop 53J is stored as the value of the path metric register 51J.

As described above, the path metric up to that branch in each branch is updated.
On the other hand, the path selection information in each branch, that is, the information on which path was selected at the time of path metric comparison / selection is shown as {S _ijkl } in FIG. 5. This path selection information {S _ijkl } is output to the path memory update unit 24 described below.

FIG. 7 shows the path memory update unit 24 in the maximum likelihood detector 21 having PR (1, 2, 2, 1) as a target response.
The path memory update unit 24 in FIG. 7 includes path memory registers 61A to 61J, 62A to 62J, and flip-flops 63A to 63J.
In FIG. 7, the path selection information supplied from the path metric update unit 23 is shown as {S _ijkl }.

The path memory register 61A, a path memory M ₀₀₀₀ of the survival path in branch b ₀₀₀₀ are stored.
The update of the path memory of the path that reached the bit string 0000 is
_{M 0000 = 2 · select (M} 0000, M 1000) +0
It is represented by Note that select (A, B) is an operation for selecting A and B.
That is, the path memory register 62A selects a path memory having a path metric that decreases the path metric among the path memories M ₀₀₀₀ and M ₁₀₀₀ of the two paths leading to the branch b ₀₀₀₀ , and doubles the selected memory value to 0. Add and store. This path selection information is based on the comparison result at branch b ₀₀₀₀ in the path metric update unit 23 of FIG. The value of the path memory register 62A latched by the flip-flop 63A is stored as the value of the path memory register 61A.
In the figure, select (S ₀₀₀₀ , M ₀₀₀₀ , M ₁₀₀₀ ) is shown. This is an operation for selecting either M ₀₀₀₀ or M ₁₀₀₀ based on the path selection information S ₀₀₀₀ at the time of path metric update. It shows the meaning. The other path memory registers 62B, 62E, 62F, 62I, and 62J have the same meaning.

The path memory register 61B, a path memory M ₀₀₀₁ of the survival path in branch b ₀₀₀₁ are stored.
The update of the path memory of the path that reached the bit string 0001 is
M ₀₀₀₁ = 2 · sel (M ₀₀₀₀ , M ₁₀₀₀ ) +1
It is represented by For this reason, the path memory register 62B selects a path memory having a path metric that decreases among the path memories M ₀₀₀₀ and M ₁₀₀₀ of the two paths leading to the branch b ₀₀₀₁ , and doubles the selected memory value to 1 Is added and memorized. This path comparison information is based on the comparison result in the branch b ₀₀₀₁ in the path metric update unit 23. The value of the path memory register 62B latched by the flip-flop 63B is stored as the value of the path memory register 61B.

The path memory register 61C, a path memory M ₁₀₀₀ of the survival path in branch b ₁₀₀₀ are stored.
The update of the path memory of the path that reached the bit string 1000 is
M ₁₀₀₀ = 2 · M ₁₁₀₀ +0
It is represented by Therefore, in the path memory register 62C, the path memory M ₁₁₀₀ of the path leading to the branch b ₁₀₀₀ is doubled, and 0 is added and stored. The value of the path memory register 62C latched by the flip-flop 63C is stored as the value of the path memory register 61C.

The path memory register 61D stores the path memory M ₁₀₀₁ of the surviving path in the branch b ₁₀₀₁ .
The update of the path memory of the path reaching the bit string 1001 is
M ₁₀₀₁ = 2 ・ M ₁₁₀₀ +1
It is represented by In the path memory register 62D, the path memory M ₁₁₀₀ of the path leading to the branch b ₁₀₀₁ is doubled, and 1 is added and stored. The value of the path memory register 62D latched by the flip-flop 63D is stored as the value of the path memory register 61D.

The path memory register 61E, the path memory M ₀₀₁₁ of the survival path in branch b ₀₀₁₁ are stored.
The update of the path memory of the path reaching the bit string 0011 is as follows:
M ₀₀₁₁ = 2 · sel (M ₀₀₀₁ , M ₁₀₀₁ ) +1
It is represented by In the path memory register 62E, a path memory having a path metric that reduces the path metric is selected from the path memories M ₀₀₀₁ and M ₁₀₀₁ of the two paths leading to the branch b ₀₀₁₁ , and the selected memory value is doubled to 1 Add and store. This path selection information is based on the comparison result in the branch b ₀₀₁₁ in the path metric update unit 23 of FIG. The value of the path memory register 62E latched by the flip-flop 63E is stored as the value of the path memory register 61E.

The path memory register 61F stores the path memory M ₁₁₀₀ of the surviving path in the branch b ₁₁₀₀ .
The update of the path memory of the path reaching the bit string 1100 is as follows:
M ₁₁₀₀ = 2 · sel (M ₀₁₁₀ , M ₁₁₁₀ ) +0
It is represented by In the path memory register 62F, a path memory with a path metric that decreases the path metric is selected from the path memories M ₀₁₁₀ and M ₁₁₁₀ of the two paths leading to the branch b ₁₁₀₀ , and the selected memory value is doubled to 0. Is added and memorized. This path selection information is based on the comparison result in the branch b ₁₁₀₀ in the path metric update unit 23. The value of the path memory register 62F latched by the flip-flop 63F is stored as the value of the path memory register 61F.

The path memory register 61G stores the path memory M ₀₁₁₀ of the surviving path in the branch b ₀₁₁₀ .
The update of the path memory of the path that reached the bit string 0110 is
M ₀₁₁₀ = 2 · M ₀₀₁₁ +0
It is represented by In the path memory register 62G, the path memory M ₀₀₁₁ of the path leading to the branch b ₀₁₁₀ is doubled and 0 is added and stored. The value of the path memory register 62G latched by the flip-flop 63G is stored as the value of the path memory register 61G.

The path memory register 61H stores the path memory M ₀₁₁₁ of the surviving path in the branch b ₀₁₁₁ .
The update of the path memory of the path that reached the bit string 0111 is
M ₀₁₁₁ = 2 · M ₀₀₁₁ +1
It is represented by In the path memory register 62H, the path memory M ₀₀₁₁ of the path leading to the branch b ₀₁₁₁ is doubled and 1 is added and stored. The value of the path memory register 62H latched by the flip-flop 63H is stored as the value of the path memory register 61H.

The path memory register 61I stores a path memory M ₁₁₁₀ of the surviving path in the branch b ₁₁₁₀ .
The update of the path memory of the path reaching the bit string 1110 is as follows:
M ₁₁₁₀ = 2 · sel (M ₀₁₁₁ , M ₁₁₁₁ ) +0
It is represented by In the path memory register 62I, a path memory having a path metric having a smaller path metric is selected from the path memories M ₀₁₁₁ and M ₁₁₁₁ of the two paths leading to the branch b ₁₁₁₀ , and the selected memory value is doubled to 0. Add and store. This path selection information is based on the comparison result in the branch b ₁₁₁₀ in the path metric update unit 23. The value of the path memory register 62I latched by the flip-flop 63I is stored as the value of the path memory register 61I.

The path memory register 61J, the path metric M ₁₁₁₁ of the survival path in branch b ₁₁₁₁ are stored.
The update of the path memory of the path that reached the bit string 1111 is
M ₁₁₁₁ = 2 · sel (M ₀₁₁₁ , M ₁₁₁₁ ) +1
It is represented by In the path memory register 62J, a path memory having a path metric that decreases the path metric is selected from the path memories M ₀₁₁₁ and M ₁₁₁₁ of the two paths leading to the branch b ₁₁₁₁ , and the selected memory value is doubled to be 1. Add and memorize. This path selection information is based on the comparison result in the branch b ₁₁₁₁ in the path metric update unit 23. The value of the path memory register 62J latched by the flip-flop 63J is stored as the value of the path memory register 61J.

The bit sequence stored in the above path memory update unit 24 eventually converges to a plausible bit sequence while repeating the above-described path selection. The time taken to converge is said to be about five times the constraint length. Therefore, if the path memory is composed of a 30-bit shift register, the upper bits of the path memory are converged. Therefore, the maximum likelihood detector 21 selects the most significant bit (MSB) of the path memory of the branch b ₁₁₁₁ and outputs this as a bit detection result.

FIG. 8 is an example of the differential metric calculator 27 of FIG. The differential metric calculator 27 calculates a differential metric different from the differential metric used for the bit detection process in the maximum likelihood detector 21.
As described in FIG. 2, the differential metric calculator 27 detects the equalized signal of the target response PR (1, 2, 2, 2, 1) from the equalizer 26 and the maximum likelihood detector 21. A bit sequence is provided.
As shown in FIG. 8, the differential metric calculator 27 includes a PR level generator 80, a subtracter 81, flip-flops 82A to 82D, multipliers 83A to 83E, and an adder 84.
Note that the number of flip-flops and the number of multipliers are changed as necessary.

The PR level generator 80 generates the PR level of the target response PR (1, 2, 2, 2, 1) from the bit sequence from the maximum likelihood detector 21. That is, a PR level is generated by multiplying a 5-bit bit string by 1, 2, 2, 2, 1 and adding the result.
The subtracter 81 is supplied with the equalized signal q from the equalizer 26 and the PR sequence signal p from the PR level generator 80.
The output value subjected to the subtraction of qp by the subtracter 81 is supplied to the multipliers 83A to 83E by shifting by one clock timing by the shift register by the flip-flops 82A to 82D, and the outputs of the multipliers 83A to 83E are further supplied. The result is added by the adder 84 to obtain a differential metric dM.

In this case, the coefficients of the multipliers 83A to 83E are sequentially 1, 2, 2, 2, 1. In the differential metric calculator 27, a filter (a filter composed of flip-flops 82A to 82D, multipliers 83A to 83E, and an adder 84) has a partial response obtained from the output q _{n of the} equalizer 26 and the detected bit sequence. since the difference between the output p _n are sequentially inputted, as a result, the differential metric dM _n at time n,
dM _n = 1 · (q _n-0 −p _n-0 ) + 2 · (q _n−1 −p _n−1 ) + 2 · (q _n−2 −p _n−2 ) + 2 · (q _n−3 − p _n-3 ) + 1 · (q _n-4 −p _n-4 )
Will get. This value is a value obtained by removing the Euclidean distance as described above. Further, the sign is corrected in the processing by the bit corrector 29 later.
The differential metric calculated by the differential metric calculator 27 differs from the path metric corresponding to the bit sequence detected by the maximum likelihood detector 21 and the bit sequence detected by the maximum likelihood detector 21 by 1 bit. This corresponds to the difference between the path metric corresponding to the bit sequence.

  The differential metric calculated by the differential metric calculator 27 uses a reference level obtained by performing a predetermined correction on the reference level obtained from the target response PR (1, 2, 2, 2, 1) having a constraint length of 5. Or a differential metric calculated by In this case, the predetermined correction of the reference level means that for each reference level, a signal that corresponds to the reference level is selected from the actually detected signals, and the reference level is adapted using the low frequency component. To correct it.

The differential metric dM calculated by the differential metric calculator 27 is supplied to the bit corrector 29 and the SAM jitter calculator 30.
FIG. 9 is an example of the bit corrector 29. The bit corrector 29 includes a classifier 91, a comparison calculator 92, a selector 93, and a register 94. The bit corrector 29 classifies the differential metric dM obtained by the differential metric calculator 27 using the 5-bit value obtained by the maximum likelihood detector 21 and compares it with the Euclidean distance. And the value of the middle bit of the 5 bits is corrected.

  The register 94 holds 5 bits of a bit sequence as bits sequentially detected and output from the maximum likelihood detector 21. That is, for each channel bit, the bit value output from the maximum likelihood detector 21 is stored as bit b4, the value of bit b4 is bit b3, the value of bit b3 is bit b32, and the value of bit b2 is The values of bit b1 and bit b1 take the form of a shift register that is transferred to bit b0, respectively. The bit value sequentially output from the bit b0 is a modified bit sequence. The third bit b2 is corrected by the value supplied from the selector 93.

The classifier 91 classifies the differential metric dM calculated by the differential metric calculator 27 into four operation tables. The classification is performed based on the 5-bit pattern held in the register 94.
Here, the differential metric dM is classified by four 5-bit patterns of 11000, 11100, 00001, and 11111.
It should be noted that the bit patterns 11000, 11100, 00001, and 00111 are the d1 rule even when the maximum likelihood detector 21 performs a Viterbi detection process on a signal that complies with the d1 rule as a run length rule, even if a predetermined 1 bit is changed. It is a bit pattern that satisfies
The comparison calculator 92 includes four calculation tables 92-0, 92-1, 92-2, and 92-3 corresponding to the four bit patterns, respectively.
The selector 93 selects one of the four calculation tables 92-0, 92-1, 92-2, and 92-3 based on the 5-bit pattern held in the register 94, and calculates the selected calculation table. The result is supplied to bit b2 of register 94.

The bit corrector 29 operates as follows.
When the 5-bit pattern held in the register 94 is 11000, the differential metric dM supplied from the differential metric calculator 27 is classified into the operation table 92-0 by the classifier 91. And in the calculation table 92-0,
out = (+ dM <c)? 0: 1
The value “0” or “1” as a result of comparing the value of the differential metric dM and the Euclidean distance by the above operation is added to the middle bit of 5 bits, that is, the value of the bit b2 of the register 94.
However, c is a Euclidean sequence of a partial response sequence different by 1 bit when the target response is PR (1, ^2, 2, ^2, 1), and its value is c = (1 ² +2 ² +2 ² +2 ² +1 ² ) = 14. A? B: C indicates an operation for outputting B if the logic A is correct and outputting C if the logic A is incorrect.
In this case, if + dM <c, out = 0, and 0 is added to the middle bit (b2 of the register 94) of 11000. In other words, it is not corrected. On the other hand, if + dM <c, out = 1, 1 is added to the middle bit of 5 bits of 11000 (b2 of the register 94), and the 5 bits are corrected to 11100.

When the 5-bit pattern held in the register 94 is 11100, the differential metric dM supplied from the differential metric calculator 27 is classified into the operation table 92-1 by the classifier 91. And in the calculation table 92-1,
out = (− dM <c)? 0: 1
The result of comparison between the differential metric value and the Euclidean distance by the above operation is added to the value of the bit b2 in the middle of 5 bits.

When the 5-bit pattern held in the register 94 is 00001, the differential metric dM supplied from the differential metric calculator 27 is classified into the operation table 92-2 by the classifier 91. And in the calculation table 92-2,
out = (+ dM <c)? 0: 1
The result of comparing the value of the differential metric dM and the Euclidean distance by the above calculation is added to the value of the middle bit b2 of 5 bits.

When the 5-bit pattern held in the register 94 is 00111, the differential metric dM supplied from the differential metric calculator 27 is classified into the operation table 92-3 by the classifier 91. And in the calculation table 92-3,
out = (− dM <c)? 0: 1
The result of comparing the value of the differential metric dM and the Euclidean distance by the above calculation is added to the value of the middle bit b2 of 5 bits.

The bit corrector 29 repeats the above processing for each channel bit to correct the bit value.
In other words, the bit corrector 29 detects the detected bit sequence detected by the maximum likelihood detector 21 when the differential metric value exceeds the Euclidean distance between two partial response sequences formed by two bit sequences different by one bit. The bit value b2 of the 5-bit bit pattern is inverted.
However, when the 5 bits of the register 94 are not 11000, 11100, 00001, or 11111, the arithmetic processing for the differential metric dM is not performed, that is, the bit b2 is not corrected.

The differential metric dM calculated by the differential metric calculator 27 as described above is also supplied to the SAM jitter calculator 30.
FIG. 10 is an example of the SAM jitter calculator 30. The SAM jitter calculator 30 includes a square circuit 95, a pattern detection counter 96, a square value addition circuit 97, a square root circuit 98, and a division circuit 99.
The differential metrics dM sequentially supplied from the differential metric calculator 27 are squared by the square circuit 95 and added by the square value addition circuit 97 to calculate an average value. Then, the standard deviation value of the differential metric dM is calculated by performing the square root calculation by the square root circuit 98. Further, the SAM jitter corrected by dividing the standard deviation value by the Euclidean distance (14 in this case) by the dividing circuit 99 is obtained.
The pattern detection counter 96 is supplied with 5 bits of the register 94, that is, a 5-bit pattern on the bit sequence from the maximum likelihood detector 21, and the pattern detection counter 96 receives the input 5-bit pattern. 11000, 11100, 00001 or 00111 is detected. Only in any case, the square value addition circuit 97 adds the square value of the differential metric dM.
With the above processing, the SAM jitter is calculated using the differential metric dM.

According to the PRML decoding device 6 as described above, in PRML detection in which a target response having a long constraint length, for example, PR (1, 2, 2, 2, 1) is required, the PRML decoding process itself has a constraint length. A short target response, eg PR (1, 2, 2, 1) is used, but by performing bit correction based on the value of the differential metric dM calculated by PR (1, 2, 2, 2, 1), High-precision bit detection can be performed without increasing the circuit scale of the PRML decoding device.
As a result, even when the bit length with respect to the resolution of the reproducing head and the pickup is relatively reduced as the recording medium such as the disk 90 increases in density, the differential metric dM is calculated with a target response having a longer constraint length. Then, it is possible to detect the bit with high accuracy by adopting a technique of correcting the PRML detection bit.
Furthermore, the fact that there is almost no increase in the circuit scale of the PRML decoding device 6 when coping with high density realizes low power consumption while realizing highly accurate bit detection. Furthermore, since the circuit scale is not complicated, design difficulty associated with higher density does not occur, and processing speed is not reduced.
For these reasons, the recording / reproducing system and the data transmission system can cope with high density and high transfer rate.

By the way, in the above example, when Viterbi detection processing is performed on a signal that complies with the d1 rule as a run length rule, four bit patterns 11000, 11100, 00001, and 00111 satisfy the d1 rule even if a predetermined one bit is changed. Although an example using a 5-bit pattern is used, the bit corrector 29 may perform classification using a bit pattern of 6 bits or more. However, in this case, at least a bit pattern including 11000, a bit pattern including 11100, a bit pattern including 00001, and a bit pattern including 00111 are set as bit patterns. For example, as an example of using a 6-bit bit pattern, 6 bits obtained by adding 0 or 1 as the least significant bit to the above 5 bits, that is, 8 types of 110000, 110001, 111000, 111001, 00110, 000111, 001110, and 001111. It is conceivable to classify the value of the differential metric dM with a 6-bit pattern.
Furthermore, it is conceivable to use a bit pattern of 7 bits or more obtained by adding 2 bits or more to each of the 5 bits.

In addition, when performing Viterbi detection processing for a signal conforming to the d1 rule, a bit pattern that includes one or more consecutive shortest run length runs and satisfies the d1 rule even if the shortest run length run is shifted by 1 bit, There is also an example using a bit pattern of 7 bits or more. In this case, a bit pattern including 001000, a bit pattern including 0001100, a bit pattern including 1110011, and a bit pattern including 1100111 are set as the plurality of bit patterns.
In this case, the differential metric calculator 27 calculates the path metric corresponding to the bit sequence detected by the maximum likelihood detector 21 and the shortest run length run included in the bit sequence detected by the maximum likelihood detector 21 as 1. The difference between the path metric corresponding to the bit sequence shifted by bits is obtained in the target response PR (1, 2, 2, 2, 1).

  The bit corrector 29 includes a classifier 91A, a comparison calculator 92A, a selector 93A, and a register 94A as shown in FIG. In this case, the bit corrector 29 classifies the differential metric dM obtained by the differential metric calculator 27 using the 7-bit value obtained by the maximum likelihood detector 21 and calculates the difference from the Euclidean distance. The comparison is performed and the value of two of the seven bits is corrected.

The register 94A holds 7 bits (b0 to b6) of the bit sequence as bits sequentially detected and output from the maximum likelihood detector 21. In this case, bit b2 and bit b4 are corrected by the value supplied from selector 93A.
The classifier 91A classifies the differential metric dM calculated by the differential metric calculator 27 into four operation tables. The classification is performed based on the 7-bit pattern held in the register 94A. Here, the differential metric dM is classified by four 7-bit patterns of 001000, 0001100, 1110011, and 1100111.
The comparison calculator 92A includes four calculation tables 92-0, 92-1, 92-2, and 92-3 corresponding to the four bit patterns, respectively.
The selector 93A selects one of the four calculation tables 92-0, 92-1, 92-2, and 92-3 based on the 7-bit pattern held in the register 94A, and calculates the selected calculation table. The result is supplied to bits b2 and b4 of register 94A.

The bit corrector 29 classifies the differential metric dM into four calculation tables 92-0, 92-1, 92-2, and 92-3 according to the 7-bit pattern, and the calculation tables 92-0 and 92-3. −1, 92-2, and 92-3 perform the same calculation as in FIG. When the calculation result, that is, when the output of the selector 93A is “0”, the values of the bits b2 and b4 are not inverted, and when the output of the selector 93A is “1”, the bits b2 and b4 are inverted. .
For example, when the 7-bit pattern held in the register 94A is 001000, the differential metric dM supplied from the differential metric calculator 27 is classified into the operation table 92-0 by the classifier 91. And in the calculation table 92-0,
out = (+ dM <c)? 0: 1
The result of comparison between the differential metric dM and the Euclidean distance c is obtained by the above calculation. At this time, when the operation result is “0”, “0” is added to the values of the bits b2 and b4 of the register 94A, so the values of the bits b2 and b4 are not changed. That is, the 7 bits of the register 94A remain unchanged at 001000. On the other hand, when the operation result is “1”, “1” is added to the values of the bits b2 and b4 of the register 94A, and the values of the bits b2 and b4 are inverted. That is, the 7 bits of the register 94A are corrected from 001000 to 0001100. That is, when the value of the differential metric exceeds the Euclidean distance between two bit sequences obtained by shifting the shortest run-length run by 1 bit, the shortest run-length run is 1 It will correct the bit-shifted error.
In each case where the 7-bit pattern held in the register 94A is 0001100, 1110011, and 1100111, the same processing is performed according to the calculation result in the comparison calculator 92A.
However, when the 7 bits of the register 94A are neither 001000, 0001100, 1110011, or 1100111, the arithmetic processing for the differential metric dM is not performed, that is, the bits b2 and b4 are not corrected.
Although a 7-bit pattern is used here, a (7 + n) -bit bit pattern in which n bits are added to each of 001000, 0001100, 1110011, and 1100111 may be used.

In the embodiment, the target response in the equalizer 20 and the maximum likelihood detector 21 is PR (1, 2, 2, 1), and the target response in the equalizer 26 and the differential metric calculator 27 is PR (1, 2, , 2, 2, 1), but various other examples are possible.
For example, the target response in the equalizer 26 and the differential metric calculator 27 is changed to PR (0, 1, 2, 2, 1, 0) with a constraint length of 6 instead of PR (1, 2, 2, 2, 1). Also good.
The target response at the equalizer 20 and the maximum likelihood detector 21 is PR (1, 2, 1), and the target response at the equalizer 26 and the differential metric calculator 27 is PR (1, 2, 2, 1) or ( Examples such as 1, 2, 2, 2, 1) are also conceivable.

It is a block diagram of the reproducing | regenerating apparatus of embodiment of this invention. It is a block diagram of the PRML decoding apparatus of an embodiment. It is a block diagram of the equalizer in the PRML decoding apparatus of embodiment. It is a block diagram of the maximum likelihood detector in the PRML decoding apparatus of an embodiment. It is a block diagram of the branch metric calculation unit in the PRML decoding device of the embodiment. It is a block diagram of the path metric update unit in the PRML decoding apparatus of the embodiment. It is a block diagram of the path memory update unit in the PRML decoding device of the embodiment. It is a block diagram of a differential metric calculator in the PRML decoding apparatus of the embodiment. It is a block diagram of the bit modifier in the PRML decoding apparatus of an embodiment. It is a block diagram of the SAM jitter calculator in the PRML decoding apparatus of embodiment. It is a block diagram of the other bit modifier in the PRML decoding apparatus of embodiment.

Explanation of symbols

1 optical pickup, 2 preamplifier, 3 A / D converter, 4 equalizer, 5 PLL circuit, 6 PRML decoder, 8 demodulator, 9 RS decoder, 10 CPU block, 20 equalizer, 21 maximum likelihood detector, 22 branch metric Calculation unit, 23 path metric update unit, 24 path memory update unit, 26 equalizer, 27 differential metric calculator, 29 bit corrector, 30 SAM jitter calculator, 91, 91A classifier, 92, 92A comparison operator, 93 , 93A selector, 94, 94A register

Claims (14)

Bit detection means for performing bit response detection and Viterbi detection processing on the input signal to detect bits;
Differential metric calculation means for calculating a differential metric different from the differential metric used for bit detection by the bit detection means for a bit pattern according to a predetermined rule in the bit sequence detected by the bit detection means; ,
Bit correction means for correcting the bit sequence detected by the bit detection means based on a comparison result between the differential metric obtained by the differential metric calculation means and the Euclidean distance corresponding to the differential metric;
A PRML decoding device comprising:   The bit pattern according to the predetermined rule is a bit pattern according to a predetermined run-length rule, and is a bit pattern that satisfies the run-length rule even if a predetermined one bit is changed. The PRML decoding device described. When the bit detection means performs a Viterbi detection process for a signal that complies with the d1 rule as the run length rule,
The bit pattern according to the predetermined rule includes a bit pattern of 5 bits or more, and includes a plurality of bit patterns including a bit pattern including 11000, a bit pattern including 11100, a bit pattern including 00001, and 11111. The PRML decoding apparatus according to claim 2, wherein a bit pattern is set. The differential metric calculated by the differential metric calculation means is
A difference between a path metric corresponding to the bit sequence detected by the bit detection unit and a path metric corresponding to a bit sequence different from the bit sequence detected by the bit detection unit by 1 bit,
3. The PRML decoding device according to claim 2, wherein the PRML decoding device is a differential metric obtained by an operation different from the differential metric used for bit detection by the bit detection means. The bit correcting means is
Detection detected by the bit detection means when the differential metric value obtained by the differential metric calculation means exceeds the Euclidean distance between two partial response sequences formed by two bit sequences different by one bit. 3. The PRML decoding apparatus according to claim 2, wherein a predetermined bit value of a bit pattern in the bit sequence is inverted.   The bit pattern according to the predetermined rule is a bit pattern according to a predetermined run length rule, including one or more consecutive shortest run length runs, and even if the shortest run length run is shifted by 1 bit. The PRML decoding apparatus according to claim 1, wherein the PRML decoding apparatus has a bit pattern that satisfies a run length rule. When the bit detection means performs a Viterbi detection process for a signal that complies with the d1 rule as the run length rule,
The bit pattern according to the predetermined rule is a bit pattern of 7 bits or more, and includes a plurality of bit patterns including a bit pattern including 001000, a bit pattern including 0001100, a bit pattern including 1110011, and 1100111. The PRML decoding apparatus according to claim 6, wherein a bit pattern is set. The differential metric calculated by the differential metric calculation means is
A path metric corresponding to the bit sequence detected by the bit detection unit, and a path metric corresponding to a bit sequence obtained by shifting the shortest run-length run included in the bit sequence detected by the bit detection unit by one bit; The difference between
7. The PRML decoding apparatus according to claim 6, wherein the PRML decoding device is a differential metric obtained by an operation different from the differential metric used for bit detection by the bit detection means. The bit correcting means is
When the differential metric value obtained by the differential metric calculation means exceeds the Euclidean distance between two partial response sequences formed by two bit sequences in which the shortest run-length run is shifted by 1 bit. 7. The PRML decoding apparatus according to claim 6, wherein a predetermined bit value of a bit pattern in the detected bit sequence detected by the bit detecting means is inverted. The bit correcting means is
When the differential metric value obtained by the differential metric calculation means exceeds the minimum Euclidean distance determined by the target response, the predetermined bit value of the bit pattern in the detection bit sequence detected by the bit detection means is inverted. The PRML decoding device according to claim 1, wherein:   The differential metric different from the differential metric used for bit detection by the bit detection means is a constraint longer than the constraint length necessary for calculating the differential metric used for bit detection by the bit detection means. The PRML decoding apparatus according to claim 1, wherein the PRML decoding apparatus is a differential metric that requires a length. The differential metric used for bit detection by the bit detection means is a differential metric calculated from a reference level obtained from a target response PR (1, 2, 2, 1) having a constraint length of 4,
The differential metric calculated by the differential metric calculation means is a differential metric calculated using a reference level obtained from a target response PR (1, 2, 2, 2, 1) having a constraint length of 5. The PRML decoding device according to claim 1. The differential metric calculated by the differential metric calculation means uses a reference level obtained by performing a predetermined correction on the reference level obtained from the target response PR (1, 2, 2, 2, 1) having a constraint length of 5. Is a calculated differential metric,
The predetermined correction of the reference level means that for each reference level, an actually detected signal corresponding to the reference level is selected, and the reference level is adaptively used using the low frequency component. The PRML decoding device according to claim 12, which is to be modified. A bit detection step for detecting a bit by performing a partial response equalization process and a Viterbi detection process on the input signal;
A differential metric calculation step for calculating a differential metric different from the differential metric used for bit detection in the bit detection step with respect to a bit pattern according to a predetermined rule in the bit sequence detected in the bit detection step; ,
A bit correction step of correcting the bit sequence detected in the bit detection step based on a comparison result between the differential metric obtained in the differential metric calculation step and the Euclidean distance corresponding to the differential metric;
A PRML decoding method comprising:

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