JPH0697769A - Automatic equalizer for digital signal recording/ reproducing device - Google Patents

Abstract

PURPOSE:To automatically equalize a non-linear distortion caused at the time of recording with high density by a small circuit scale by using a Viterbi equalizer, and a decision feedback type equalizer, for equalization of a pre-cursor component of a signal, and equalization of a post-cursor, respectively. CONSTITUTION:Three symbols b0-b2 in an impulse response execute Viterbi equalization, and one symbol b3 uses a dicision feedback type equalizer. A metric arithmetic part 1 sets deviation power of a receiving signal distorted due to an inter-code interference of an estimated signal sequence having possibility of reception as a branch metric, and executes Viterbi decoding in accordance with a prescribed trellis transition. A path memory part 2 stores path information for showing which path is selected by the arithmetic part 1, and by its path information, an address signal of the estimated signal is generated. A correction address signal generating part 3 generates and outputs a signal for determining an estimated signal for correcting to an estimated signal having possibility of reception by using a result of decision from the memory part 2. A correcting device part 5 corrests it to a signal having possibility of reception to an estimated signal storage part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizer for digital signal recording / reproducing apparatus.

[0002]

2. Description of the Related Art In a magnetic recording system, in order to digitally record a high-definition broadcast, it is necessary to perform high density recording on a magnetic recording tape. It is affected by interference.

Further, in the case of the magnetic recording method, since an nonlinear signal is recorded, an equalizer capable of removing nonlinear distortion is required. Conventionally, there are two types of automatic equalizers for removing such intersymbol interference and non-linear distortion: a decision feedback equalizer and a Viterbi equalizer.

[0004]

When this conventional automatic equalizer is applied to a high definition digital VTR, the decision feedback equalizer can remove the postcursor component of the impulse response, but the precursor component. Has a problem in that it cannot be equalized due to its circuit configuration. Also, if Viterbi equalization is applied, both the post and precursor components can be equalized, but due to the large amount of computation, it is especially suitable for high-definition digital VTRs. Has the problem that it cannot be used.

[0005]

The automatic equalizer according to the first aspect of the present invention includes a digital type received signal including intersymbol interference distortion and 2 ⁿ (n is a non-negative integer) corresponding thereto. The branch metric is the squared value of the error of the received signal for each of the 2 ⁿ possible estimated signal sequences, which is received, and is selected as the branch metric of 2 ⁿ possible states. A metric calculator for calculating a summed path metric of the added branch metric and outputting the minimum value of the path metric reaching each state as a path memory signal; 2 from the metric calculator
An estimate for storing the output of ^n-1 path memory signals as path survival information, outputting the most probable judgment value for the received signal from the state transition of the survival information, and reading out 2 ⁿ estimated signals. A path memory unit that outputs an address signal; an input signal for rewriting the judgment value output of the path memory unit into an estimated signal that may be received in the estimated signal storage unit, and an estimated signal that may be received A corrected address signal generation unit that generates and outputs a signal that determines an estimated signal to be corrected; and outputs 2 ⁿ estimated signals to the path metric calculation unit when the estimated address signal is selected in the path memory unit, When the modified address signal output from the address signal generator is selected, it is output to the corrector for the estimated signal memory in which the estimated signal to be corrected is stored. And an estimated signal storage unit for storing the output result of the corrector as an input; a correction in which all estimated signals output from the estimated signal storage unit are connected to an estimated signal storage unit in which estimated signals are stored A correction unit for correcting the estimated signal into an estimated signal that may be received and outputting the estimated signal to the estimated signal storage unit.

The automatic equalizer according to the second aspect of the present invention includes a digital-type received signal including intersymbol interference distortion and a corresponding 2
^{When n n} (n is a non-negative integer) estimated signals are received, the square value of the error of the received signal with respect to 2 ⁿ estimated signal sequences that may be received is used as a branch metric, and 2 ⁿ A metric calculator for calculating a summed path metric of a branch metric of a state to be obtained and a branch metric selected immediately before, and outputting the minimum value of the path metric reaching each state as a path memory signal; 2 ^{n -1} path memory signal outputs are stored as path survivor information, the most probable judgment value for the received signal is output from the state transition of the survivor information, and 2 ⁿ estimated signals are read out. A path memory unit that outputs an estimated address signal of the estimated signal output of the path memory unit, and an estimated signal that may be received in an estimated signal storage unit. A corrected address signal generation unit that generates and outputs a signal that determines an estimated signal to be corrected as an input signal for rewriting the estimated signal that may be received; and the estimated address signal is selected in the path memory unit. At this time, 2 ⁿ estimated signals are output to the path metric calculator, and when the corrected address signal output from the address signal generator is selected, the estimated signal to be corrected is output to the selector, and the corrector An estimated signal storage unit that stores the corrected signal as a corrected signal that may be received by the ;; an estimated signal sequence that is input from the estimated signal sequence from the estimated signal storage unit in the estimated signal storage unit A selector for modifying or selecting the estimated signal in the signal memory; selecting the selected output of the selector as an input, and selecting the modified signal again in one of the estimated signal storage sections And a corrector for writing.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. In this embodiment, three symbols b _{0 to} b ₂ in the impulse response shown in FIG. 2 are used for Viterbi equalization, and one symbol b ₃ is a decision feedback equalizer. A branch metric 6 is the power of the error of the received signal that is distorted by intersymbol interference with respect to the estimated signal sequence that may be received, and a metric calculator 1 that performs Viterbi decoding according to the trellis transition diagram shown in FIG. Output from the path memory unit 2, which stores the surviving path information indicating which path is selected by the operation, and which generates the address signal of the estimation signal based on the surviving path information given from the metric operation unit 1. A corrected address signal generation unit 3 for generating a corrected address signal for correcting the estimated signal in the estimated signal storage unit 4 using the determined determination result, and stores the estimated signal. The estimation signal storage unit 4 and the corrector unit 5 that corrects a signal that may be received are configured.

Next, the details of each part will be described with reference to the drawings.

FIG. 4 is a block diagram showing a first configuration example of the metric calculator 1. As the estimated signal, four symbols (b ₀ , b ₁ , b ₂ , b ₃ ) of the impulse response signal sequence shown in FIG. 2 are used, and three of them (b ₀ , b ₁ , b ₂ ) is equalized,
Since one symbol (b ₃ ) is equalized by the decision feedback circuit, only 2 ³ = 8 branch metrics are required for Viterbi equalization. A trellis transition diagram for equalizing this signal sequence is shown in FIG. Assuming that the received signal a _n has intersymbol interference distortion, branch metrics c ₀ to c ₇ are given by the following equation (1).
~ (8) is required.

C ₀ = a _n ² (1) c ₁ = (a _n −b ₀ ) ² (2) c ₂ = (a _n −b ₁ ) ² (3) c 3 = (a _n −b ₀ −b ^{_{1) 2 (4) c4 =}} (a n -b 2) 2 (5) c5 = (a n -b 2 -b 0) 2 (6) c6 = (a n -b 2 -b 1) 2 (7 ) c7 = addition _{(a n -b 2 -b 1 -b} 0) 2 (8), d 3 from the time path metric d ₀ is obtained by the following equation (9) to (12).

D _{n, 0} = min [d _{n -1, 0} + c ₀ , d _{n -1, 2} + c ₄ ] (9) d _{n, 1} = min [d _{n -1, 0} + c ₁ , d _{n- 1, 2} + c ₅ ] (10) dn _{, 2} = min [dn- _{1, 1} + c ₂ , dn- _{1, 3} + c ₆ ] (11) dn _{, 3} = min [dn- _{1, 1} + C ₃ , dn _{− 1, 3} + c ₇ ] (12) That is, which path metric data is smaller is compared by the comparison selector 8, and when the left term of the above equation is small, “0” is set.
When the right term is small, "1" is used as surviving path information, and small path metric data is stored in the register 9. One of the stored four path metric data is used as a reference signal, the reference signal is subtracted from the remaining path metric by the subtractor 10, and the subtraction result is given by the branch metric and the adder 7 that are input next. By adding, the next path metric is determined. The same operation is performed each time an input signal is input.

FIG. 5 is a block diagram showing a first configuration example of the path memory unit 2. The survival information obtained by the metric calculation unit 1 is stored, and a judgment value corresponding to the path is output at the point where the data converge. FIG. 7 is a trellis transition diagram for explaining the operation. The abscissa indicates T with time, the ordinate indicates S _{0 to} S ₃ , and the states are c ₀ to c
₇ is the branch metric, and the reciprocal of the probability of each state at each time is the path metric d. For example, T = 5
In this case, each state may be taken, and the survival state information (e ₀ = e ₁ = e ₂ = e ₃ = 1) is shown by the input of the path storage circuit 12 in FIG. At T = 4, the states S ₀ and S ₃ may take the states shown in FIG. 7, and the states S ₁ and S ₂ are impossible. That is, c ₀ = 0 and e
_{When 5 0} = 0 or c ₁ = 0 and e _{5 1} = 0, e _{4 0} =
It becomes 1 and otherwise, e ₄₀ = 0. Similarly, c ₆ =
1 and e _{5 2} = 1 or c ₇ = 1 and e _{5 3} = 1 e
_{4 3} = 1 and otherwise e _{4 3} = 0. Therefore T
Since the data is merged into S ₃ at the time of = 2, the data up to T = 2 can be determined as "0101". The modifying unit 13 rewrites and updates the received data signal stored in the estimated signal storage unit 14. In updating this document, as shown in FIG.
Bit-shifted data is input to the decoder 17, and the estimated signal memory 14 containing the data to be modified is selected. The corrector 13 connected to the data corrects and processes the data, and inputs the data to the estimated signal memory 4 again.

FIG. 12 is a block diagram showing a second configuration example of the metric calculator 1. The estimated signal is as shown in FIG.
4 symbols (b of the impulse response signal sequence shown in FIG.
₀ , b ₁ , b ₂ , b ₃ ) and three symbols (b ₀ , b ₁ , b ₂ ) among them are equalized by Viterbi equalization, and one symbol b ₃ is equalized by a decision feedback circuit. Therefore, only 2 ³ = 8 branch metrics are required for Viterbi equalization. A trellis transition diagram for equalizing this signal sequence is shown in FIG. Assuming that the received signal a _n has the intersymbol interference distortion, the branch metrics c ₀ to c ₇ can be obtained by the equations (1) to (8).

At this time, the path metrics d ₀ to d
₃ is obtained from the following equations (13) to (16).

D _{n, 0} = min [dn _{− 1, 0} + c ₀ , dn _{− 1, 4} + c ₄ ] (13) dn _{, 1} = min [dn _{− 1, 1} + c ₁ , d _{n- 1, 5 + c 5] (} 14) d n, 2 = min [d n - 1, 2 + c 2, d n - 1, 6 + c 6] (15) d n, 3 = min [d n - 1, 3 _{+ c 3, d n - 1} , 7 + c 7] (16) compares the comparison selector eight or data of which path metric is smaller, when the left term of the equation is small "0",
When the right term is small, "1" is used as the surviving path metric data selection signal, and the small path metric data is further compared by the comparison selector 8. The following formulas (17) and (18)
Shown in.

E _{n, 0} = min [d _{n, 2} , d _{n, 3} ] (17) e _{n, 1} = min [d _{n, 2} , d _{n, 3} ] (18) That is, which path metric The data is small or compared by the comparator 8. When the left term of the above equation is small, "0" is used as the survival path metric data selection signal, and when the right term is small, the small path metric data is further selected. The comparison selector 8 performs comparison. It is shown in the following equation (19).

F _{n, 0} = min [e _{n, 0} , e _{n, 1} ] (19) That is, which path metric data is smaller is compared by the comparison selector 8, and when the left term of the above equation is small, "0",
When the right term is small, "1" is used as the survival path metric data selection signal, and the final path metric data selected by the equation (19) is subtracted from the path metric data selected by the equations (13) to (16). Subtracting is performed at 10, and the subtraction result is added to the branch metric to be input next by the adder 7 to determine the next path metric. The same operation is performed each time the following is input.
FIG. 13 is a block diagram showing a second configuration example of the path memory unit 2. The survivor information obtained by the metric calculator 1 is stored, and at the point where the data converges, the judgment value corresponding to that point is output. FIG. 14 is a trellis transition diagram for explaining the operation. It is assumed that T on the horizontal axis indicates a change with time, S _{0 to} S _{3 on} the vertical axis are states, and c _{0 to} c ₇ are branch metrics. When the data in the path memory of T = 1 to T = 3 has the values shown in FIG. 10, the surviving path metric data selection signal output from the metric operation next is S1 of “1”, S1 Is "0", S2
Assuming that "1" is selected and S3 is selected as "1", the survival state information as viewed from T = 4 is as follows.

S _{3, 0} (1) → S _{3, 1} (1) → S _{2, 2} (1) → S _{0, 3} (1) S _{1, 0} (0) → S _{2, 1} (0) → S _{0, 2} (1) → S _{1, 3} (0) S _{3, 0} (1) → S _{3, 1} (1) → S _{3, 2} (1) → S _{3, 3} (1) S _{3, 0} (1) → S _{3, 1} (1) → S _{3, 2} (1) → S _{3, 3} (1) Assuming that the data converges when T = 4, the path metric data output from the metric calculator 1 is The data in the path memory at the time of T = 4 becomes the judgment value result by inputting the selection signal of the path that becomes the minimum. Estimated signal memory 14
The correction unit 13 rewrites and updates the data stored in 1) by the received signal. This rewriting update is as shown in FIG.
The judgment output data is input to the decoder 17 as a 2-bit shift by the flip-flop 16 and the estimated signal storage calculator 14 containing the data to be corrected is selected. The data that has been shifted by 2 bits in the flip-flop 16 is further 2
An address signal that determines which of the data stored in the estimated signal storage unit 14 is rewritten by bit shifting is generated, and the correction unit 13 shown in FIG. It is again input to the estimated signal storage unit 14.

FIGS. 9 and 10 are block diagrams of the second embodiment of the present invention. The difference from the first embodiment is that the survivor path state information and survivor path information in the metric calculator are obtained. In addition, a point where the smallest path metric is selected by performing a plurality of stages of comparison and selection, a point where the selection signal serves as a selection signal for determining the judgment value result of the path memory section, and instead of the modifier section 5 To selector 15
And the modifier 13 is used. In this embodiment,
Using the judgment value obtained from the path memory unit 2, the modified address signal generation unit 3 generates a modified address signal for rewriting the estimated signal for equalizing the precursor component,
The specified signal corresponding to the input signal of the modified address signal is output from each estimated signal storage unit 14 as an estimated signal, and the data stored in the estimated signal storage unit 14 is rewritten and updated by the correction unit 13 according to the received signal. . This rewrite update is shown in Figure 1.
0, as shown in FIG. 11, the judgment value data is shifted by 2 bits in the flip-flop 16 and input to the decoder 17 to generate the rewriting read selection signal of the estimated signal memory 14. Next, this selection signal is input to the selector 15, which selects one of the eight estimated signal storage units 14 and outputs it to the correction unit 13. The corrector 13 receives the output of the selector 15 as an input, corrects the data, and inputs it to the estimated signal storage 14 again.

[0021]

As described above, when the automatic equalizer of the present invention is applied to a high-definition digital VTR, it is possible to equalize the post of the impulse response and the precursor component, and equalize the postcursor component. A decision feedback equalizer can be applied to reduce the circuit scale, and Viterbi equalization can be applied to the precursor component to obtain the nonlinearity of the reproduced signal read from the high-density recorded magnetic tape. It is possible to remove the distortion.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a signal sequence diagram of an impulse response according to the embodiment of this invention.

FIG. 3 is a trellis transition diagram of the embodiment of the present invention.

FIG. 4 is a block diagram showing a first configuration example of a metric calculation unit 1 in FIG.

5 is a block diagram showing a first configuration example of a path memory unit 2 in FIG.

6 is a circuit diagram of a path storage circuit 12 in FIG.

FIG. 7 is a trellis transition diagram according to the embodiment of the present invention.

8 is a block diagram of an estimated signal storage unit 4 and a corrector unit 5 in FIG.

FIG. 9 is a block diagram of an embodiment of the present invention.

FIG. 10 is a block diagram of an embodiment of the present invention.

11 is a block diagram of the corrector 13 of FIGS. 8 to 10. FIG.

12 is a block diagram showing a second configuration example of the metric calculation unit 1 in FIG.

13 is a block diagram showing a second configuration example of the path memory unit 2 in FIG.

FIG. 14 is a trellis transition diagram of the embodiment of the present invention.

[Explanation of symbols]

 1 metric calculation unit 2 bus memory unit 3 corrected address signal generation unit 4 estimated signal storage unit 5 correction unit 6 subtraction squarer 7 adder 8 comparison selector 9 register 10 subtractor 11 D flip-flop 12 path storage circuit 13 correction 14 Estimated signal storage 15 Selector 16 Flip-flop 17 Decoder

Claims (2)

[Claims] 1. Received 2 ⁿ (n is a non-negative integer) estimated signal corresponding to a digital type received signal including intersymbol interference distortion, and 2 ⁿ possible received signals, respectively. A branch metric is the squared value of the error of the received signal with respect to a certain estimated signal sequence, and an addition value path metric of the branch metric of 2 ⁿ possible states and the branch metric selected immediately before is calculated, and each state is reached. A metric calculator that outputs the minimum value of the path metric as a path memory signal;
An estimate for storing the output of ^n-1 path memory signals as path survival information, outputting the most probable judgment value for the received signal from the state transition of the survival information, and reading out 2 ⁿ estimated signals. A path memory unit that outputs an address signal; an input signal for rewriting the judgment value output of the path memory unit into an estimated signal that may be received in the estimated signal storage unit, and an estimated signal that may be received A corrected address signal generation unit that generates and outputs a signal that determines an estimated signal to be corrected; and outputs 2 ⁿ estimated signals to the path metric calculation unit when the estimated address signal is selected in the path memory unit, When the modified address signal output from the address signal generator is selected, it is output to the corrector for the estimated signal memory in which the estimated signal to be corrected is stored. And an estimated signal storage unit for storing the output result of the corrector as an input; a correction in which all estimated signals output by the stored estimated signal storage unit are connected to an estimated signal storage unit in which the estimated signals are stored. A digital signal recording / reproducing apparatus, comprising: a correction unit for correcting the estimated signal into an estimated signal that is likely to be received as an input to the receiver and outputting the estimated signal to the estimated signal storage unit. Automatic equalizer for. 2. Received 2 ⁿ (n is a non-negative integer) estimated signals corresponding to a digital-type received signal including intersymbol interference distortion, and 2 ⁿ possible received signals, respectively. A branch metric is the squared value of the error of the received signal with respect to a certain estimated signal sequence, and an addition value path metric of the branch metric of 2 ⁿ possible states and the branch metric selected immediately before is calculated, and each state is reached. A metric calculator that outputs the minimum value of the path metric as a path memory signal;
An estimate for storing the output of ^n-1 path memory signals as path survival information, outputting the most probable judgment value for the received signal from the state transition of the survival information, and reading out 2 ⁿ estimated signals. A path memory unit that outputs an address signal; an input signal for rewriting the judgment value output of the path memory unit into an estimated signal that may be received in the estimated signal storage unit, and an estimated signal that may be received A corrected address signal generation unit that generates and outputs a signal that determines an estimated signal to be corrected; and outputs 2 ⁿ estimated signals to the path metric calculation unit when the estimated address signal is selected in the path memory unit, When the modified address signal output from the address signal generator is selected, the estimated signal to be modified can be output to the selector and received by the modifier. An estimated signal storage unit that stores the corrected signal into a certain corrected signal; an estimated signal sequence that is input from an estimated signal sequence from the estimated signal storage unit in the estimated signal storage unit, and an estimated signal of which estimated signal storage unit A selector for correcting or selecting the correction signal; and a selector for inputting the selection output of the selector and again writing one of the estimated signal storage units by selecting one of the estimated signal storage units. An automatic equalizer for digital signal storage / reproduction devices.