JP2668451B2 - Maximum likelihood decoding control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A maximum likelihood decoding control method for maximum likelihood decoding of an input signal subjected to a waveform interference is intended to improve the decoding error rate without increasing the circuit scale. A maximum-likelihood decoding unit having a circuit, a path memory, a path selector, and a hypothetical path memory inputs a sample value of an input signal subjected to waveform interference to perform maximum-likelihood decoding in the maximum-likelihood decoding control method. The amount of interference due to future signals is estimated by using the sample values of several bits corresponding to the temporal data sequence before the memory, and a hypothetical sample value including the amount of interference is obtained. And a sample value of the input signal is input to the ACS circuit to perform maximum likelihood decoding.

[Industrial applications]

The present invention relates to a maximum likelihood decoding control system that performs maximum likelihood decoding of an input signal that has received waveform interference.

2. Description of the Related Art In magnetic disk devices and the like, the recording density has been increased in accordance with the demand for larger capacity. Therefore, the reproduced signal is greatly affected by the waveform interference, and the waveform equalization processing becomes difficult (the equalization in such a case greatly increases the high-frequency noise). In the case of decoding by level identification, the error rate becomes large. The reproduced signal suffering from such waveform interference or the received signal suffering from waveform interference in the data transmission system is reconstructed by using a Viterbi decoder or the like which selects and decodes the most probable signal from the assumed data sequence. It has been proposed to improve the decoding error rate by performing likelihood decoding.

[Conventional technology]

A demodulation system of a conventional magnetic recording apparatus has, for example, the configuration shown in FIG. 9, 61 is a magnetic head for reproducing recorded data from a recording medium such as a magnetic disk, 62 is an amplifier, 63 is an equalizer, 64 is a pulse circuit, 65 is a phase locked loop (PLL), 66 is an equalizer, 67 is an AD converter (A / D),
68 is a Viterbi decoder.

The reproduced signal from the magnetic head 61 is amplified by an amplifier 62, is equalized and amplified by equalizers 63 and 66 including filters and the like, and is subjected to noise removal and the like.A pulse is formed by peak detection in a pulsing circuit 64, A clock signal phase-locked to the reproduction signal is obtained from the phase synchronization circuit 65, this clock signal becomes a sampling clock signal of the AD converter 67, and the reproduction signal equalized by the equalizer 66 is added to the AD converter 67. The digital signal is sampled and converted into a digital signal by a sampling clock signal having a bit period from the phase synchronization circuit 65, and the sampled value of the reproduced signal converted into the digital signal is converted into a Viterbi decoder 68.
And maximum likelihood decoding is performed.

The Viterbi decoder is known as a maximum likelihood decoder of a convolutional code, for example, as shown in FIG.
The ACS circuits 72-1 to 72-4, the path memory 73, the normalization circuit 74, and the path selector 75 are provided, and the branch metric value is calculated by the distributor 71 to calculate the ACS circuits 72-1 to 72-72.
-4. The ACS circuits 72-1 to 72-4 are provided with 2 ^k-1 assuming that the constraint length of the convolutional code is k.
FIG. 10 shows a case where the constraint length k = 3 because four ACS circuits are provided.

The ACS circuits 72-1 to 72-4 are respectively adders (A).
And a comparator (C) and a selector (S). The branch metric value and the previous path metric value are added by the adder (A) and compared by the comparator (C).
The smaller path metric value is selected by the selector (S) as the path metric value of the surviving path, and the path selection signal at that time is added to the path memory 73. The path memory 73 is 4 to 5 times the constraint length k. It has the number of stages of path memory cells and is stored as a survivor path, and the output of the final stage is added to the path selector 75, and a decoded output is obtained by majority processing and the like. When the number of digits overflows in the calculation of the path metric value, the normalization circuit 74 normalizes the path metric value.

When such a Viterbi decoder is used to decode a signal subjected to waveform interference, the ACS circuit calculates the sum of the squared output of the error between the assumed sample value and the actual sample value and the previous path metric value. A new path metric value, compare each path metric value, select the smaller one of the new path metric values of the addition output, set it as the next path metric value, and add the selected information to the path memory 73. is there.

FIG. 11 shows a trellis diagram with a constraint length of 3, where solid arrows indicate transitions when input data is “0”, dotted arrows indicate transitions when input data is “1”, and circles indicate internal states. For example, the path P0, P
The hypothetical sample values at 1 are calculated as shown in (a) and (b) of FIG.
Can be set to y _p0 and y _p1 indicated by black circles in the waveform. This value is obtained by the 3-bit hypothetical path (a _-1 , a ₀ , a ₁ ) shown as the present in (a) of FIG. 12, and depends on the bit period of the isolated waveform in (c) of FIG. Assuming that the sample value is g _i , the constraint length is k, and m = (k−1) / 2, Is determined by: Therefore, y _p0 and y _p1 become m = 1 when the constraint length k = 3, so that i = −1 to i =
Values up to +1 are values obtained by the equation (1).

When interference from past data is also taken into consideration, the value of the path memory (b ₂ , b ₃ ,...) Can be determined by:

FIG. 13 is a block diagram of a main part of a conventional example in which interference from past data is considered based on the above-mentioned equation (2).
A circuit 81, a path memory 82, a path selactor 83, and a hypothetical path memory 84 are provided, and a sample value of a signal to be decoded such as a reproduction signal in a magnetic disk device or the like is added to the ACS circuit 81. In the path memory 82 and the assumed path memory 84, since the magnetic recording / reproducing signal has positive and negative polarities, “1”,
It has a shift register configuration capable of storing “0” and “−1”, and the assumed path memory 84 stores a plurality of different assumed data strings.

Based on this hypothetical data string and the contents of the path memory 82, the hypothetical sample value considering interference from past data is obtained, and in the ACS circuit 81, this hypothetical sample value and the sample value of the reproduced signal and the like are obtained. Is obtained, the square output of the difference between the two is calculated, the previously calculated metric value is added, the smaller output is compared, and the smaller one is selected. Value is path memory
Entered in 82.

Therefore, the value in the path memory 82 is not the most likely value as a decoded value, but is a value that is likely at that point in time, leading to a hypothesis. The path selector 83 detects the minimum value of the path metric value at that time,
A path leading to that state is selected, and the last data is used as a decoded output. The arrow connecting between the path memory 82 and the assumed path memory 84 is expressed by the following equation (2).
This shows that multiplication and addition are performed to obtain a hypothetical sample value at the present time.

[Problems to be solved by the invention]

As described above, an accurate hypothetical sample value can be estimated by also considering interference from past data. However, when the path one bit ahead (one bit before the current time) is considered, for example, a hypothetical sample when the paths following the path P0 in the trellis diagram of FIG. The values are y _p00 and y _p10 indicated by black circles in the waveforms of (d) and (e) in FIG. 12, and if the future data of one bit is “1”, it is assumed that the interference amount is not considered. The error of the sample value increases. Therefore, it is necessary to increase the constraint length k, that is, increase the number of bits of the hypothetical path to accurately estimate the interference amount. However, the circuit size of the decoder is
Proportional to 2 ^k, increasing the constraint length k becomes large circuit scale becomes difficult to realize.

Further, in the decoding method considering the interference due to the past data as in the conventional example shown in FIG. 13, since the interference due to the future data with respect to the present data is not taken into consideration as described above, It is necessary to perform special equalization such that interference is zero. This special equalization is a major obstacle to practical use for a magnetic disk device or the like in which the amount of interference differs for each track of magnetic recording.

An object of the present invention is to improve the decoding error rate without increasing the circuit scale.

[Means for solving the problem]

The maximum likelihood decoding control method of the present invention estimates a waveform interference due to future data to form a hypothetical sample value, and will be described with reference to FIG.

ACS circuit 1, path memory 2, path selector 3,
The maximum likelihood decoding unit 5 having the assumed path memory 4 inputs the sample value of the input signal subjected to the waveform interference and performs the maximum likelihood decoding. The interference amount due to a future signal is estimated by using the sample values for several bits, and the hypothetical sample value including this interference amount is obtained, and the hypothetical sample value and the sample value of the input signal are sent to the ACS circuit 1. The maximum likelihood decoding is performed by inputting.

Further, the amount of interference due to future signals is estimated from the sample values of the input signal for several bits corresponding to the temporally preceding data sequence of the assumed path memory 4 and the assumed data sequence of the assumed path memory 4. Using the amount of interference, the assumed data string of the assumed path memory 4 and the contents of the path memory 2, ACS
The hypothetical sample value to be added to the circuit 1 is obtained.

The amount of interference due to future signals is estimated based on the sample values of the input signal for several bits before the assumed data sequence in the assumed path memory 4 and the assumed data sequence in the assumed path memory 4, and The amount of interference due to past signals is obtained from sample values of input signals for several bits corresponding to the temporally subsequent data sequence of the hypothetical data sequence No. 4 and the amount of interference due to future signals, the hypothetical data sequence of the hypothetical path memory 4, Is used to determine a hypothetical sample value based on the interference amount of the signal.

Further, an interference amount due to a future signal is estimated based on a sample value of an input signal of several bits corresponding to a time preceding the assumed data sequence of the assumed path memory 4 and the assumed data sequence of the assumed path memory 4, and A first interference amount due to a past signal based on a sample value of an input signal of several bits corresponding to a time later than the assumed data sequence of the assumed path memory 4;
A second interference amount due to a past signal is obtained from the contents of the path memory 2, and the second interference amount is selected when the output of the last stage of the path memory 2 is converged, and the first interference amount is selected when the output is not converged. Is selected, and a hypothetical sample value is obtained from the selected interference amount, the hypothetical data sequence in the hypothetical path memory 4, and the interference amount due to future signals.

[Action]

In claim 1, when a hypothetical sample value is calculated based on the hypothetical data string of the hypothetical path memory 4 and added to the ACS circuit 1, the sample value of the input signal corresponding to the temporally preceding said hypothetical data string is calculated. Using one bit or a plurality of bits, an interference amount due to a future signal is estimated by multiplication and addition processing. That is, an accurate hypothetical sample value is calculated in consideration of waveform interference between adjacent bits and between a plurality of bits apart. Therefore, by performing maximum likelihood decoding based on the difference between the assumed sample value and the sample value of the input signal, the decoding error rate can be reduced without increasing the length of the assumed data sequence (length of the constraint length). Can be improved.

3. A hypothetical path memory according to claim 2, wherein a sample value of the input signal is input to a shift register or the like, and a sample value of several bits corresponding to a temporally earlier than the hypothetical data string of the hypothetical path memory is used. The amount of interference due to future signals is estimated using the hypothetical data sequence No. 4. A hypothetical sample value is calculated using the estimated interference amount, the hypothetical data sequence in the hypothetical path memory 4, and the contents of the path memory 2. That is, the hypothetical sample value is determined in consideration of the interference amount due to the future signal and the interference amount due to the past signal.

The interference amount due to a past signal is calculated by using a sampled value of an input signal which is temporally later than the hypothetical data string of the hypothetical path memory 4, and the content of the path memory 2 is incorrect. If there is, the amount of interference is determined based on the content including the error, and therefore the error propagates. However, when the sample value of the input signal is used, it is possible to avoid the spread of the error.

In Claim 4, the amount of interference due to past signals is obtained as a first amount of interference calculated using sample values of the input signal and a second amount of interference calculated using the contents of the path memory 2. It is determined whether or not the output of the last stage of the path memory 2 has converged. If the output is converged, there is no error.
The second interference amount is selected, and if the convergence is not achieved, there is an error, so the first interference amount is selected. Then, an assumed sample value is obtained from the selected interference amount, the assumed data sequence in the assumed path memory 4, and the amount of interference due to future signals.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a main part of an embodiment of the present invention.
The decoding unit 15 having the ACS circuit 11, the path memory 12, the path selector 13, and the assumed path memory 14, an interference amount predictor 16,
A configuration in which a shift register 17 is added is shown. Input signals such as a reproduction signal in the magnetic recording device and a reception signal in the data transmission system which have received the waveform interference are sampled in a bit cycle, and the sample value (digital value) is input to the shift register 17.

The case where the hypothetical data string of the hypothetical path memory 14 is 3 bits (constraint length k = 3) a _-1 , a ₀ , a ₁ ("0,0,0" to "1, -1,1,") is shown. , Correspondingly, 3 bits of path memory 12
b ₂ , b ₃ , b ₄ (see (a) of FIG. 12) and the shift register
3 bits x ₀ of 17, x _-1, is intended to obtain the assumed sample value with one bit x _-2 in the x _-2, interference amount predictor 16
Is the sample value corresponding to 1 bit before the assumed data string
The case where the interference amount is predicted using x _-2 , the assumed data sequence a _-1 , a ₀ , a ₁ and the content b ₂ of the path memory 12 corresponding to 1 bit after the assumed data sequence is shown.

As described above, when the hypothetical sample value is obtained in consideration of future data, the hypothetical sample value y is It can be expressed as. That is, using the value a _i of the assumed interference amount due to future data path memory 14, the value b _i of the path memory 12, the interference amount corresponding thereto g _i, and the actual sample values thereof and temporally corresponding It is an estimate. or As shown by, the system (i) in which the time at which the hypothetical sample value is obtained is 0 is converted to the system (j) in which the bit immediately before the hypothetical path is 0, and 10 (c = 0) of c _j (j = 0 to 9) is obtained. FIG. 3 shows the waveform interference when various data strings from all “0” to “1” are assumed in the bit range. A Lorentz waveform as shown in FIG. 4 was assumed as an isolated waveform in that case. This Lorentz waveform g (t) is It is represented by

The horizontal axis represents the amplitude x at j = 0, and the vertical axis represents the interference amount y _i at j = 1, 2, and 3, and the relationship between the interference amounts in the case of T ₅₀ = 1, 1.5, 2 is shown in FIG. Shown in For example, the constraint length k =
For 3, m = 1, and the assumptions sample values from will be based on the amount of interference j = 2, when attention is focused on y _2, it is found can be approximated by a straight line. That is, assuming that g ₀ = 1, It can be expressed as. This equation (6) is the assumed path memory
Since the interference amount from the path memory 12 and the path memory 12 to the amplitude x is not taken into consideration, the following expression is obtained when this interference amount is taken into consideration.

When this equation (7) is substituted into the above equation (3), the assumed sample value y becomes Will be obtained.

If the constraint k = 3, then m = 1, and the first expression (8)
The terms are assumed data strings a ₋₁ , a ₀ , a ₁ assuming i = −1,0,1;
It is shown that the multiplication results of the isolated waveform sample values g ₁ , g ₀ , and g ₋₁ are added, and the second term is n = 4, i = 2,3,4, and the path memory 12 Content of b ₂ , b ₃ , b ₄
, And the multiplication results of the isolated waveform sample values g ₄ , g ₃ , and g ₂ are added. The first term in parentheses in the third term is a sample value g ₋₁ , g ₋₂ , g of an isolated waveform.
_-3 and the multiplication result of each of the hypothetical data sequences a _-1 , a ₀ , a ₁ are added, and the second term in the parentheses is i = 2, 3, 4 and the isolated waveform sample value g _-4 , g _-5 , g _-6 and path memory 1
Add the result of multiplication with the contents b ₂ , b ₃ , and b _{4 of 3}
The sum of them is subtracted from x _-2 to obtain the sample value g of the isolated waveform.
_The arrow in FIG. 2 indicates multiplication by two.
The multiplication and addition processing by equation (8) is shown.

FIG. 6 shows a specific configuration for obtaining the hypothetical sample value according to the above equation (8), wherein 21 to 33 are multipliers, 34 to 36 are adders, and 37 is a subtractor. The hypothetical data string a _-1 , a ₀ , a _{1 of the} hypothetical path memory 14 and the sample values g ₁ , g ₀ , g _-1 of the isolated waveform are multiplied by the multipliers 21 to 23 and then added by the adder 34. By the addition, the calculation of the first term of the equation (8) is performed. The contents b ₂ , b ₃ , b _{4 of the} path memory 12 are multiplied by the isolated waveform sample values g ₄ , g ₃ , g ₂ by the multipliers 24 to 26 and added by the adder 34. As a result, the calculation of the second term of the equation (8) is performed. Also, the multiplication results by the multipliers 27 to 32 are added by the adder 35, respectively,
The operation in the parentheses of the third term of the equation (8) is performed, and the subtractor 35
Is subtracted from the sample values x _-2 of the input signal In, by being multiplied by g ₂ by the multiplier 33, (8) a third
The terms are calculated and added by the adder 36 to obtain a hypothetical sample value y to be added to the ACS circuit 11.

The ACS circuit 11 calculates the sum of the sample value x ₀ of the input signal via the shift register 17, the square output of the difference between the above-mentioned assumed sample value y, and the previous metric value to obtain a new metric value. The smaller value is compared as the next metric value, and the last data of the selected hypothetical data sequence is added to the path memory 12, and the decoded output by the majority decision of the output of the last stage of the path memory 12 is output. It will be output from the path selector 13.

FIG. 7 is a block diagram showing a main part of another embodiment of the present invention, in which a sample value of an input signal is used as past data, 41 is an ACS circuit, 42 is a path memory, 43 is a path selector, 44 Is an assumed path memory, 45 is an interference amount calculator, 46
Is an interference amount predictor, 47 and 48 are input to the ACS circuit 41 from the connection stage of the shift registers 47 and 48, and the sample value of x ₋₂ of the shift register 47 is input to the interference amount predictor 46 and the shift register 48. Are input to the interference amount calculator 45. The hypothetical sample value y added to the ACS circuit 41 is obtained based on the above equation (3). The first term is obtained from the value of the hypothetical path memory 44, and the second term is the path memory.
Instead of using the value of 42, it is obtained by the interference amount calculator 45 using the past sample value x _2, and the third term is obtained by the interference amount predictor 46 using the future sample value x _-2. .

The second term of the above equation (3) is And the third term of equation (3) is expressed by equation (6). Assumed path memory of this equation (9) and the above equation (6)
Since the interference amount with respect to the sample value x from the path memory 44 and the path memory 42 is not considered, when this interference amount is considered, (9)
ceremony, Becomes Further, the expression (6) becomes the above-mentioned (7).

Therefore, the hypothetical sample value y is Becomes That is, the hypothetical sample value y is obtained by the configuration shown in FIG. Incidentally, the arrow indicates the same as in the above-mentioned embodiment,
It is shown that multiplication and addition are performed, and the hypothetical sample value calculation unit can be realized by, for example, a multiplier and an adder similar to the configuration shown in FIG.

Since the interference amount is calculated by using the past sample value and the hypothetical sample value is calculated by the above equation (11), the decoding is compared with the case where the interference amount is calculated by using the contents of the path memory 42. Can be avoided.

FIG. 8 is a block diagram of a main part of still another embodiment of the present invention, in which 51 is an ACS circuit, 52 is a path memory, 53 is a path selector, 54 is an assumed path memory, 55 is an interference amount calculator, and 56 is An interference amount predictor, 57 and 58 are shift registers, 59 is an exclusive OR circuit, and 60 is a switching circuit.

In this embodiment, the interference amount due to data in the past is calculated using the first interference amount calculated using the past sample value x ₂ and the values b ₂ , b ₃ and b ₄ of the path memory 52. The interference amount of 2 is switched by the switching circuit 60 that is switched and controlled by the output of the exclusive OR circuit 59, and is used for calculating the assumed sample value y. That is, when the output of the final stage of the path memory 52 is converged, the output of the exclusive OR circuit 59 becomes “0”, so the switching circuit 60 selects the interference amount obtained using the path memory 52, When the output of the last stage of the path memory 52 is not converged, the output of the exclusive OR circuit 59 becomes “1”, so that the switching circuit 60 selects the interference amount obtained using the past sample values. .

Therefore, when a decoding error occurs and the final stage of the path memory 52 does not converge, the interference amount is calculated using the past sample values of the input signal, and the hypothetical sample value is obtained based on the interference amount. The spread of errors can be avoided.

The present invention is not limited to the above-described embodiment, but may be configured so that future and past sample values are used for a plurality of bits with respect to the contents of the assumed path memory.

〔The invention's effect〕

As described above, according to the present invention, the maximum likelihood decoding unit 5 such as the Viterbi decoder having the ACS circuit 1, the path memory 2, the path selector 3, and the hypothetical path memory 4 samples the input signal subjected to the waveform interference. Maximum likelihood decoding is performed by inputting a value, and the assumed sample value in that case is used to estimate the amount of interference due to future signals by using the sample values for several bits that are temporally preceding the assumed data string. Since an accurate hypothetical sample value can be obtained in consideration of interference due to future data, there is an advantage that the error rate of decoding can be improved without increasing the constraint length, that is, the number of bits of the hypothetical data sequence. is there.

Further, by calculating the amount of interference due to the past data using the past sample values and obtaining the assumed sample values, it is possible to prevent the propagation of decoding errors. Further, by calculating the hypothetical sample value including the interference amount due to the past data and the interference amount due to the future data, it is possible to obtain an accurate hypothetical sample value considering the influence of the future and past data. This has the advantage that the decoding error rate can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a block diagram of a main part of an embodiment of the present invention, FIG.
FIG. 5 is an explanatory diagram of an isolated waveform, FIG. 5 is an explanatory diagram of the relationship of the interference amount,
FIG. 6 is a block diagram of a main part of a hypothetical sample value calculation unit, FIG. 7 is a block diagram of a main part of another embodiment of the present invention, and FIG. 8 is a block diagram of a main part of still another embodiment of the present invention. , FIG. 9 is a block diagram of a conventional example, FIG. 10 is a block diagram of a Viterbi decoder, FIG. 11 is a trellis diagram of a constraint length 3, and FIG.
(E) is an explanatory diagram of a signal waveform, and FIG. 13 is a block diagram of a main part of a conventional example. 1 is an ACS circuit, 2 is a path memory, 3 is a path selector, 4
Is a hypothetical path memory.

 ───────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Muto 1015 Ueodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kiichiro Kasai 1015 Kamiodanaka Nakahara-ku Kawasaki-shi, Kanagawa Fujitsu Limited ( 56) References JP-A-3-160668 (JP, A)

Claims (4)

(57) [Claims] An input signal sample subjected to waveform interference by a maximum likelihood decoder (5) having an ACS circuit (1), a path memory (2), a path selector (3), and a hypothetical path memory (4). In the maximum likelihood decoding control method for inputting a value and performing maximum likelihood decoding, using the sample value for several bits corresponding to the temporal data before the hypothetical data string of the hypothetical path memory (4), the future Estimating an interference amount due to a signal, obtaining a hypothetical sample value including the interference amount, inputting the hypothesis sample value and the sample value of the input signal to the ACS circuit (1), and performing maximum likelihood decoding. Maximum likelihood decoding control method. 2. A future value of a sample value of an input signal for several bits corresponding to a temporally preceding data sequence of the hypothetical path memory (4) and a hypothetical data sequence of the hypothetical path memory (4). Estimate the amount of interference due to the signal, the amount of interference,
The hypothetical sample value to be applied to the ACS circuit (1) is obtained using the hypothetical data string of the hypothetical path memory (4) and the contents of the path memory (2). Likelihood decoding control method. 3. A hypothetical path memory (4) having a plurality of bits of an input signal sample value corresponding to a time preceding the hypothetical data string and a hypothetical data string of the hypothetical path memory (4). The amount of interference due to signals is estimated, and the amount of interference due to past signals is obtained from sample values of the input signal for several bits corresponding to the postulated data sequence of the assumed path memory (4) in time. 2. The maximum likelihood decoding control method according to claim 1, wherein the assumed sample value is obtained from an interference amount due to a signal, an assumed data sequence in the assumed path memory (4), and an interference amount due to the past signal. . 4. The future data of the input signal of several bits corresponding to the temporal data sequence of the hypothetical path memory (4) and the hypothetical data sequence of the hypothetical path memory (4). A first interference amount caused by a past signal based on a sample value of the input signal corresponding to several bits corresponding to a time later than the assumed data sequence in the assumed path memory (4); When the second interference amount due to the past signal is obtained from the contents of the path memory (2), the second interference amount is selected when the output of the final stage of the path memory (2) is converged, and when the output is not converged. Selects the first interference amount, and obtains the assumed sample value from the selected interference amount, the assumed data sequence in the assumed path memory (4), and the interference amount due to the future signal. Claim 1 Maximum likelihood decoding control scheme.