JP2002025201A - Recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a recording and reproducing device made suitable for high density and high speed operations by providing a synchronization signal generating circuit which generates highly precise sychronization signals that are hardly affected by noise. SOLUTION: A synchronization signal generating circuit 38 has a phase error detector 30 which detects phase errors in reading signals that are made into digital signals in accordance with FDTS algorithm and a VCO 36 which controls oscillation frequency based on the phase errors detected by the detector 30. The VCO 36 generates synchronization signals. An ADC 33 makes the reading signals into digital signals based on the synchronization signals generated by the circuit 38. The digitized reading signals are converted into binary data by a discriminating circuit 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a partial response maximum likelihood decoding method.
More specifically, the present invention relates to a high-precision phase error detector for synchronizing signal generation (PLL) and a recording / reproducing apparatus using the phase error detector.

[0002]

2. Description of the Related Art Conventionally, various techniques have been devised for a recording apparatus typified by a hard disk apparatus in accordance with an improvement in recording density. In particular, as for the recording / reproducing method, the PRML method applying the technology in the communication field has been generally used, and thereafter, the extended PRML method has been put to practical use in order to further improve the recording density.

The partial response (PR) is a method of reproducing data while compressing a necessary signal band by actively utilizing intersymbol interference (interference between reproduced signals corresponding to bits recorded adjacent to each other). How to do. At this time, it can be further classified into a plurality of types of classes depending on how the intersymbol interference occurs. In the case of magnetic recording, the basic response is a class 4 partial response “PR4”.

[0004] The Viterbi decoding method (ML) is a kind of so-called maximum likelihood sequence estimation method, and effectively utilizes the inter-symbol interference rule of a reproduced waveform and based on signal amplitude information over a plurality of times. Perform data playback. In the Viterbi decoding method (ML), a synchronous clock synchronized with a reproduced waveform obtained by a magnetic head is generated. The reproduced waveform is sampled by the synchronous clock and converted into amplitude information. After that, appropriate waveform equalization is performed, the waveform is converted into a response waveform of a predetermined partial response, and is input to the Viterbi decoding unit. The Viterbi decoding unit uses the past and present sample data and outputs the most probable data series as reproduction data.

A method of reproducing data by combining the above-described partial response method and Viterbi decoding method (maximum likelihood decoding) is called a PRML channel method.

Generally, in a magnetic disk drive, when reading information recorded on a recording medium, magnetization information recorded on the recording medium is read out as an electric signal and digitized by a data reproducing circuit. Output as information. The data reproduction circuit performs an appropriate band limitation on the readout signal, performs analog / digital conversion (sampling) on the readout signal using a synchronization signal generated from the readout signal itself, and obtains amplitude information. Then, a most probable data string is generated based on the amplitude information. The obtained data string is decoded by the decoding circuit and sent to the host device.

The processing corresponding to the above PRML is performed in a data reproducing circuit. The reproduction signal input to the data reproduction circuit is amplified by a variable gain amplifier, band-limited by a band-limiting filter,
It is converted to a digital signal by a digital converter. The sampling clock at this time is generated by the synchronization signal generation circuit.

The synchronizing signal generation circuit generates a sampling clock based on the digital signal whose waveform has been equalized so as to have a response waveform of a target partial response. The synchronization signal generation circuit includes a phase error detector, a loop filter, and a VCO. The phase error detector is
A phase error between the sampling timing of the sampled signal and the originally expected correct sampling timing is obtained. The loop filter 37 performs an appropriate filtering process on the obtained phase error signal. The VCO generates a sampling clock while adjusting its oscillation frequency based on the output signal of the loop filter.

Here, the synchronizing signal generator needs to generate a high-precision sampling clock synchronized with the reproduced signal from the reproduced signal itself. Also, by improving the performance of the phase error detector, the data reproduction performance has been improved,
This makes it possible to prevent mislocking of the synchronization signal. Examples of such a phase error detector include, for example, JP-A-10-125008 and JP-A-7-19240.
There is a technique disclosed in Japanese Unexamined Patent Application Publication No. 6-206.

FIG. 13 shows an example of the configuration of a phase error detector. In the figure, a sign judgment circuit 21 judges the sign of an input signal according to Equation 1 described later. Delay circuits 12, 13
Are delay elements for one time having the same function. The multiplication circuits 14 and 15 have the same function and output a product of two input signals. The adder circuit 16 outputs the sum of the two inputs (in this case, the difference). Here, it is assumed that waveform equalization is performed so that the output waveform of the equalizer 34 becomes a response waveform of PR4. The output of the equalizer 34 at time n is represented by Y
(n), and the output of the sign determination circuit 21 corresponding to this is X (n)
And Y (n) and X (n) are delay circuits 12,
13, a one-time delay occurs, so that the delay circuits 12, 1
The output signals of No. 3 are Y (n-1) and X (n-1). These signals are multiplied by multiplication circuits 14 and 15, and Y (n
-1) .X (n) and values corresponding to Y (n) .X (n-1) are output. Since the difference between these two values is calculated by the adder circuit 16, the operation of the phase comparator can be expressed by the following equation.

[0011]

[Equation 1] Δφ = Y (n−1) · X (n) −Y (n) · X (n−1) (Equation 1) where X (n) = 1 When Y (n)> = THX (n) = 0 When TH> Y (n)> =-THX (n) =-1 When-TH> Y (n) Here, TH is a predetermined threshold value. The target equalization level at the time of noise is {1,0, −
Assuming 1 °, TH is set to about 0.5. As is apparent from Equation 1, X (n) takes any value of {1, 0, -1}. The result of Equation 1 is an input signal of the loop filter 37 as a phase error amount.

The loop filter 37 performs an appropriate filter process designed in advance on the phase error signal,
The control signal of the VCO 36 is output. The VCO 36 slightly changes the oscillation frequency based on the control signal from the loop filter 37, and adjusts the sampling timing.

[0013]

However, in the phase comparison method disclosed in Japanese Patent Application Laid-Open Nos. Hei 10-125008 and Hei 7-192406, noise or deviation of sample timing generated in a recording medium or a magnetic head is required. X (n) is determined by comparing Y (n) including an equalization error caused by a phase shift) with a predetermined threshold value. Therefore, when the noise is large and the phase shift is large, X
There is a problem that the probability of the determination error of (n) increases, the reliability of the phase error signal decreases to a level that cannot be ignored, and appropriate phase control cannot be performed. In recent years, the recording density of recording devices such as magnetic disk devices has been remarkably improved, and the signal-to-noise ratio of reproduced signals tends to decrease. As a result, the frequency of erroneous code determination is much higher than in the past, which may cause insufficient synchronization signal synchronization or mislock.

To solve such a problem, Japanese Patent Application Laid-Open No. 10-29
No. 3973 and JP-A-9-17130,
It is disclosed that an output of a Viterbi detection circuit for data reproduction is used as a reference signal X (n) for phase comparison. This makes it possible to sufficiently reduce the probability of occurrence of a decision error and accurately detect a phase error. However, the data determination using the Viterbi algorithm has a long delay time for data determination, and cannot sufficiently secure a band for phase control. Therefore, there is a problem that the control becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to obtain a highly reliable phase error signal even when the phase error is large and the signal-to-noise ratio is low, and to secure a phase control band in consideration of the above-mentioned problems in the prior art. To be able to do it.

[0016]

To achieve the above object, a recording and reproducing apparatus according to the present invention comprises a data reproducing circuit for reproducing recorded data based on a read signal read from a recording medium; A decoding circuit for decoding the recording data reproduced by the circuit; and an interface for outputting the recording data decoded by the decoding circuit to the outside.

The data reproducing circuit includes an analog-to-digital converter for converting a read signal from an analog signal to a digital signal, an equalizer for equalizing the waveform of the read signal converted to a digital signal, and an output of the equalizer. A determination circuit that performs a code determination based on a signal and outputs binary data,
A synchronization signal generation circuit for generating a synchronization signal for determining a sampling timing in the analog-to-digital conversion circuit.

In a preferred embodiment of the present invention, the synchronizing signal generation circuit has a response time shorter than that of the determination circuit, and outputs the output signal from the equalizer based on a determination algorithm that is more accurate than a code determination based on a threshold. A phase error detection circuit that performs sign determination and detects a phase error based on the determination result, a loop filter connected to the output side of the phase error detection circuit, and an analog-to-digital conversion circuit based on the output of the loop filter. And a variable frequency oscillating circuit for generating a given synchronization signal.

According to another aspect of the present invention, the synchronization signal generation circuit performs a code determination in accordance with the FDTS algorithm using output signals from the equalizer at at least two different times, and performs a code determination based on the result of the code determination. Phase error detecting circuit for detecting a phase error, a loop filter connected to the output side of the phase error detecting circuit, and a variable frequency oscillator circuit for generating a synchronization signal to be applied to an analog-to-digital conversion circuit based on the output of the loop filter And

According to another aspect of the present invention, in an information reproducing apparatus for reproducing a digital signal from a reproduction signal reproduced from a recording medium by using a partial response method, an impulse response length of a partial response is set to N bits, and Means for sampling a reproduction signal from a recording medium in accordance with a clock to be converted and converting the signal into amplitude information;
Means for performing data reproduction by the FDTS algorithm using one piece of amplitude information, and means for obtaining a phase difference signal indicating a shift in sampling timing by using obtained data and amplitude information of a reproduction signal from a recording medium. And an information reproducing apparatus including means for adjusting a sample timing so that the phase difference signal becomes zero.

According to still another aspect of the present invention, in an information reproducing apparatus for reproducing digital data of a reproduction signal reproduced from a recording medium by using a partial response method, reproduction from the recording medium in accordance with a generated clock. Means for sampling a signal to convert it into first amplitude information, means for waveform-equalizing the first amplitude information to obtain second amplitude information, and data reproduction by the FDTS algorithm using the second amplitude information. Means for obtaining a phase difference signal indicating a sampling timing shift using the obtained data and the first amplitude information, and means for adjusting the sample timing so that the phase difference signal becomes zero. A playback device is provided.

[0022]

FIG. 1 is a block diagram showing a schematic configuration of a magnetic disk drive as an example of a recording / reproducing apparatus to which the present invention is applied.

In the figure, a host interface (host I / F) 45 controls data transfer between a magnetic disk device and a host computer such as a personal computer (not shown). The recording encoding circuit 44 includes a host I / F
The user data to be recorded received from the host computer via the computer 45 is modulated according to a predetermined rule and converted into data recordable on the recording medium 41 (this process is called encoding).

The recording / reproducing amplifier 42 receives the encoded data from the recording / encoding circuit 44, and writes the data to the recording medium 41 via the recording head. Also, record /
The reproduction amplifier 42 reads out the magnetization information recorded on the recording medium 41 as an electric signal and outputs the electric signal to the data reproduction circuit 39. The data reproduction circuit 39 performs an appropriate band limitation on the read signal, converts the signal to analog / digital conversion (sampling), converts the signal into amplitude information, and determines the most reliable signal based on the amplitude information. Generate a likely data series.

The obtained data sequence is subjected to demodulation in the decoding circuit 43 in a manner opposite to that of the encoding circuit 44 (this process is called decoding), and the original recording data is restored. In the magnetic disk device, data recording and reproduction are performed according to the above procedure.

FIG. 2 is a block diagram showing a schematic configuration of the data reproducing circuit 39. In the data reproduction circuit 39, the PR
Reproduction of data by the ML method is performed.

The reproduced signal read by the magnetic head is amplified by a variable gain amplifier (VGA) 31 with an appropriate gain. The reproduced signal amplified by the VGA 31 is
After that, it is input to the band limiting filter 32. The band limiting filter 32 is used for analog-to-digital conversion at the subsequent stage.
Appropriate band limitation is performed on the reproduction signal. The analog / digital converter 33 converts the analog reproduced waveform from the band-limiting filter 32 into a digital signal. The sampling clock at this time is generated by the synchronization signal generation circuit 38. The reproduced signal converted into a digital signal is output to an equalizer 34.
In, waveform equalization is performed so as to obtain a response waveform of an intended partial response. The waveform-equalized signal is decoded into binary data by the Viterbi decoding circuit 35 and output.

The output (equalized signal) of the equalizer 34 is also supplied to a synchronizing signal generation circuit 38. The synchronization signal generation circuit 38 generates a sampling clock for determining the sampling timing of the analog-to-digital conversion based on the equalized signal. The synchronization signal generation circuit 38 is large and includes the phase error detector 30, the loop filter 37, and the VCO 36.

The phase error detector 30 calculates the phase error between the sampling timing of the sampled signal and the originally expected correct sampling timing. The loop filter 37 performs an appropriate filtering process on the obtained phase error signal. The VCO 36 generates a sampling clock while adjusting the oscillation frequency based on the output signal of the loop filter 37.

Here, in the synchronizing signal generator 38,
It is necessary to generate a high-precision sampling clock synchronized with the reproduction signal from the reproduction signal itself. Further, by improving the performance of the phase error detector 30, it is possible to improve the data reproduction performance and prevent the synchronization signal from being mislocked.

FIG. 3 is a block diagram showing a schematic configuration of the phase error detector.

Like the conventional phase error detector shown in FIG. 13, the phase error detector 30 includes delay circuits 12, 13 which are delay elements at one time and multiplication circuits 14, 15 for multiplying two input signals. , And an addition circuit 16 that outputs the difference between the two signals output from the multiplication circuits 14 and 15.

The phase error detector 30 further has a sign determination circuit 11, a delay circuit 17, and an arithmetic circuit 18. The sign determination circuit 11 is a FDTS (Fixed Delay Tree Searc
h) Perform sign determination according to the algorithm according to the method.

The F applied to the sign determination circuit 11 will be described below.
The DTS method will be described. FDTS described here
The method is disclosed in detail in, for example, US Pat. No. 5,136,593.

The impulse response from recording to reproduction of the partial response is {a ₀ , a ₁ , a ₂ }, the recording data is X _n (where X _n = {1, 0}), and the ideal channel output is Z _n, the channel output including noise and _{Y n.} At this time, the following relationship is established.

[0036]

Z _k = X _k · a ₀ + X _k−1 · a ₁ + X _k−2 · a ₂ (Equation 2)

[0037]

Y _k = Z _k + N _k (where N _k is a noise component) (Equation 3) Here, since X _n = any value of {1, 0},
For example, there are 2 ^L possible combinations of X _{n in} the range of consecutive L bits. Therefore, it is possible to determine the value of Z _n for each combination of several 2.

[0038] In FDTS method, in the range of L bits predetermined compares the errors of the values of the actually obtained Y _n of Z _n obtained from Equation 2, the true and the smallest Z _n is the difference The data is reproduced as a value.

Specifically, assuming that the search range is L = 3 bits and the target _Xn is {X _k , X _{k + 1} , X _{k + 2} }, there are eight possible combinations of X _n. is there. FIG. 4 shows this in a tree shape. In FIG. 4, a white circle represents a node, and the state changes to the next node by a new input _Xn . The dotted line is a branch corresponding to X _n = 0, and the solid line is a branch corresponding to X _n = 1. Numerical values in the figure are values of X _k / Z _k corresponding to each branch. However,
Here, it is assumed that X _k-1 = 0 and X _k-2 = 0.

For all eight combinations of Z _k, an evaluation function (Equation 4) called a metric for defining an error from the actual input signal Y _k is defined.

[0041]

(Equation 4)

In the example shown in FIG.

[0043]

M (k) = (Y _k −Z _k ) ² + (Y _{k + 1} −Z _{k + 1} ) ² + (y _{k + 2} −Z _{k + 2} ) ² (Equation 5)

[0044]

(Equation 6)

However, since Y _k and Y _{k + 1} are subject to intersymbol interference due to known X _k−1 and X _k−2 , it is necessary to correct this part. That is,

[0046]

Y _k ′ = Y _k − (a ₁ · X _k−1 + a ₂ · X _k−2 ) Y _{k + 1} ′ = Y _{k + 1} − (a _{2 ×} X _k−1 ) (Equation 7) Next, the eight metric values obtained from Equation 6 are compared,
The smallest metric is selected. Branches branches corresponding to the selected metric begins with X _{k =} 1, i.e. when in the lower half of FIG. 4 (section black circle) is determined as X _k = 1, X _k
= 0, ie in the upper half of FIG.
It is determined that X _k = 0, and a series of processes for one sample of data is completed. At the next time k + 1, data determination is similarly performed from the next point following the selected branch.

FIG. 5 is a simplified block diagram showing an example of a code determination circuit for realizing the above-mentioned FDTS algorithm.

The sign judging circuit 11 shown in FIG.
01 to 716, adders 717 to 726, one-time delay circuits 729 to 732, and a selector 728. Information that has been subjected to waveform equalization by the equalizer 34 so that Equations 2 and 3 hold is input to the sign determination circuit 11. An input signal at a certain time is Y _{k + 2} . The signals input to the sign determination circuit 11 are
708 and the input of the delay circuit 729.

The arithmetic circuit code 701 is the square of the input signal,
That is, (Y _{k + 2} ) ² is calculated. The arithmetic circuit 702 calculates the square of the value obtained by subtracting a ₀ from the input signal, that is, (Y _{k + 2} −a ₀ ) ²
Is calculated. The arithmetic circuit 703 calculates the square of the value obtained by subtracting a ₁ from the input signal, that is, (Y _{k + 2} −a ₁ ) ² . The arithmetic circuit 704 calculates the square of a value obtained by subtracting a ₂ from the input signal,
That is, (Y _{k + 2} −a ₂ ) ² is calculated. Arithmetic circuit 705
Is the square of the value obtained by subtracting a ₀ and a ₁ from the input signal, that is,
(Y _{k + 2} −a ₀ −a ₁ ) ² is calculated. The arithmetic circuit 706 calculates the square of the value obtained by subtracting a ₀ and a ₂ from the input signal, that is, (Y _{k + 2}
-A ₀ -a ₂ ) ² is calculated. The arithmetic circuit 707 calculates the square of the value obtained by subtracting a ₁ and a ₂ from the input signal, that is, (Y _{k + 2} −a ₁
-A ₂ ) ² is calculated. The arithmetic circuit 708 calculates the square of the value obtained by subtracting a ₀ , a _1, and a ₂ from the input signal, that is, (Y _{k + 2} −a ₀
−a ₁ −a ₂ ) ² is calculated.

The delay circuit 729 outputs the input signal Y _{k + 1} one time before the time when the signal Y _{k + 2} is input.
This signal is applied to addition circuit 725 and delay circuit 730. The addition circuit 725 corrects the known intersymbol interference shown in Expression 7. The output signal of the addition circuit 725 is provided to arithmetic circuits 709 to 712.

The arithmetic circuit 709 calculates the 2 of the input signal.
The power, that is, (Y _{k + 1} ) ² is calculated. The arithmetic circuit 710 includes:
The square of the value obtained by subtracting a ₀ from the input signal, that is, (Y
_{k + 1−} a ₀ ) ² is calculated. The arithmetic circuit 711 calculates the square of the value obtained by subtracting a ₁ from the input signal, that is, (Y _{k + 1} −a ₁ )
Calculate ² . The arithmetic circuit 712 calculates the square of the value obtained by subtracting a ₀ and a ₁ from the input signal, that is, (Y _{k + 1} −a ₀ −
a ₁ ) ² is calculated.

The delay circuit 731 delays the input signal by one time and outputs it. The output signal of the delay circuit 731 at the time when the signal Y _{k + 2} is input becomes Y _k . The output signal of delay circuit 731 is provided to addition circuit 726.
The addition circuit 726 corrects the known intersymbol interference shown in Expression 7. The output signal of the addition circuit 726 is
3-714.

The arithmetic circuit 713 calculates the 2 of the input signal.
The power, that is, (Y _k ) ² is calculated. The arithmetic circuit 714 is
The square of the value obtained by subtracting a ₀ from the input signal, that is, (Y
_k− a ₀ ) ² is calculated. The values obtained by the arithmetic circuits 701 to 714 are provided to adders 717 to 724. In the adders 717 to 724, the calculation of the metric value shown in Expression 6 is performed. Specifically, the output signals of the arithmetic circuits 701, 709, and 713 are input to the addition circuit 717, and the value of M0 in Equation 6 is output. Adder circuit 7
The output signal of the arithmetic circuits 702, 709, and 713 is input to 18, and the value of M1 in Equation 6 is output. The output signals of the arithmetic circuits 703, 710, and 713 are input to the adder circuit 719, and the value of M2 in Equation 6 is output. The arithmetic circuits 705, 710, 7
Thirteen output signals are input, and the value of M3 in Equation 6 is output. The addition circuits 721 include arithmetic circuits 704 and 7
11, 714 output signals are input and M
A value of 4 is output. The addition circuit 722 includes an arithmetic circuit 7
The output signals 06, 711, and 714 are input, and the value of M5 in Equation 6 is output. The output signals of the arithmetic circuits 707, 712, and 714 are input to the addition circuit 723, and the value of M6 in Equation 6 is output. Adder circuit 72
4 receives the output signals of the arithmetic circuits 708, 712, and 714, and outputs the value of M7 in Equation 6.

The values of M0 to M7 thus obtained are input to the minimum value selection circuit 728. The minimum value selection circuit 728 selects a value that minimizes the metric value.
This selection result, the value of X _k is output is determined.
This output becomes the output of the FDTS and the delay circuit 7 at the same time.
31 is input. The delay circuit 731 is a one-time delay circuit, and its output is X _k−1 . The output signal of the delay circuit 731 is supplied to the delay circuit 732 and the arithmetic circuits 715 and 7.
16 is input.

The delay circuit 732 is a one-time delay circuit, and its output is _Xk-2 . The output signal of the delay circuit 732 is input to the arithmetic circuit 716. Arithmetic circuit 715
Calculates the correction value (a ₂ · X _{k -1} ) of Y _{k + 1} in Equation 7. The arithmetic circuit 716 calculates the correction value (a ₁ · X _{k -1} + a ₂ · X _{k -2} ) of Y _k in Equation 7. Arithmetic circuit 71
5 and 716 are output from adders 725 and 7 respectively.
26.

Referring back to FIG. 3, the output of the sign determination circuit 11 is input to the arithmetic circuit 18. In the present embodiment, it is assumed that a class 4 partial response is used. Therefore, the aforementioned impulse responses {a ₀ , a ₁ ,
Waveform equalization is performed so that a ₂ ｝ = {1, 0, −1}. The operation circuit 18 performs an operation for obtaining the original PR4 output from the recording code. That is, when the output of the code determination circuit 11 at time k is X _k , the arithmetic circuit 18 performs an operation such that the output X _k ′ satisfies Expression 8.

[0057]

X _k ′ = (X _k −X _k−2 ) (Equation 8) The output of the arithmetic circuit 18 is a multiplication circuit 14 and a delay circuit 13
Is input to the arithmetic circuit 15 through

The delay circuit 17 is provided for adjusting the delay time generated in the sign determination circuit 11 and the operation circuit 18. The delay time of the delay circuit 17 is
And the same delay time as the delay time generated in the arithmetic circuit 18 is set. The composite delay time in the sign determination circuit 11 described above is two times. Therefore, the operation circuit 18
Assuming that no delay occurs in the delay circuit 17
Is two times.

The output of the delay circuit 17 is supplied to the multiplication circuit 15
The signal is input to the arithmetic circuit 14 via the delay circuit 12. The operation results of the multiplication circuits 14 and 15 are subtracted by the addition circuit 16 to generate a phase error signal representing the amount of phase error, as described in the section of the related art. The phase error signal thus generated is, as described above,
VCO filtered by the loop filter 37
36. The VCO 36 slightly changes the oscillation frequency based on the filtered phase error signal to adjust the sampling timing.

According to the above-described embodiment, since the FDTS algorithm is applied to the sign determination for detecting the phase error, the phase error with higher accuracy than the sign determination based on comparison with the threshold value, which has been conventionally common. A signal can be generated, and a more accurate synchronization signal can be generated. Further, the decoding time for code determination is two times, and the response time is relatively short, and hardly affects the phase control band.

In this embodiment, the length of the channel response is 3
Bit, that is, the impulse response is {a ₀ , a ₁ , a ₂ }
Although the case of (1) has been described as an example, a code determination circuit applicable to a partial response having an arbitrary impulse response length can be configured. Therefore, as a recording / reproducing device, not only a magnetic disk but also an optical disk device and a magnetic tape device can be widely applied.

Next, a recording / reproducing apparatus having a simplified structure of a code determining unit will be described as a second embodiment.

The partial response used for magnetic recording includes (1-D) in its transfer function due to magnetic characteristics. For example, the transfer function of the partial response of class 4 is (1-D) (1 + D), and the extended class 4 (EPR
The transfer function in the case of 4) is (1−D) (1 + D) ² .
Here, (1-D) when the appropriate precoding process is performed
Considering the output, the possible values are 1, 0, and −1, and the output corresponding to the recording code “1” is alternately output as 1 or −1, and the recording code “1”. 0 "
Is characterized in that the output corresponding to is zero.

(1-D) A state branch diagram corresponding to FIG. 4 is drawn on the basis of the output, and FDTS is performed based on the state branch diagram, so that the search range of FDTS can be shortened and the FDTS has a simple configuration. Is possible. That is, 1,0, -1
It can be considered that (1 + D) is a transfer function in the case of PR4 and (1 + D) ² is a transfer function in the case of EPR4. An embodiment based on this concept will be described.

It is assumed that the transfer function in the first embodiment can be modified as shown in Expression 9.

[0066]

(A ₀ + a ₁ · D + a ₂ · D ² ) = (1−D) · (b ₀ + b ₁ · D) (Equation 9) Here, the symbol “D” represents a one-time delay. It is assumed that “D ² ” is an operator representing a two-time delay. The transfer function based on the (1-D) output is (b ₀ + b ₁ · D). In the present embodiment, a register Sg for holding the sign of the output corresponding to the next recording data “1” at the output of (1-D) is newly provided. Sg is 1, −
It becomes one of the values of 1. At this time, the output of (1-D) that can be obtained at the next time k is {0, Sg}.

Note that in the (1-D) output corresponding to the recording data "1", Sg and -Sg alternately correspond to each other, and the state branch is shown in the same manner as in the first embodiment. Drawing is as shown in FIG. In FIG. 6, white circles represent nodes,
A state transition is made to the next node by a new input _Xn . The dotted line is the branch corresponding to X _n = 0, and the solid line is X _k = 1 or X _k
It is a branch corresponding to _k = -1. Numerical values in the figure are values of X _k / Z _k corresponding to each branch. However,
It is assumed that X _k-1 = 0 and X _k-2 = 0. As in the first embodiment, the value of Z _n corresponding to each branch, obtaining the value of the evaluation function metric. That is,

[0068]

Equation 10] _{M0 (k) = Y k '} 2 + Y k + 1 2 M1 (k) = Y k' 2 + (Y k + 1 -Sg · b 0) 2 M2 (k) = (Y k '- Sg · b ₀ ) ² + (Y _{k + 1} −Sg · b ₁ ) ² M3 (k) = (Y _k ′ −Sg · b ₀ ) ² + (Y _{k + 1} −Sg · b ₁ + Sg · b ₀ ) ² (Equation 10) However, since Y _k receives intersymbol interference due to known X _k−1 , it is necessary to correct this part. That is,

[0069]

Y _k ′ = Y _k − (b ₁ · X _k−1 ) (Equation 11) The metric value obtained by the expression 10 which has the smallest value is selected, and If it is M0 or M1, it is determined that X _k = 0, and if the minimum value is M2 or M3, it is determined that X _k = Sg and Sg = −
The value is updated as Sg. Thus, a series of processing for one sample data is completed, and processing for the next data is similarly performed.

FIG. 7 shows an FDT for realizing such processing.
FIG. 4 is a simplified block diagram illustrating an example of a sign determination circuit based on S.

The sign judging circuit of the present embodiment comprises an arithmetic circuit 8
09 to 815, adders 817 to 820, 826, delay circuits 830, 831, 833, a register 832, and a minimum value selector 828.

Now, assume that the input signal of the sign determination circuit is Y _{k + 1} . This input signal is supplied to arithmetic circuits 809, 810, 81
1, 812 and the delay circuit 830. The arithmetic circuit 809 calculates the square of the input signal, that is, (Y _{k + 1} ) ² . The arithmetic circuit 810 calculates the square of the value obtained by subtracting Sg · b ₀ from the input signal, that is, (Y _{k + 1} −Sg · b ₀ ) ² . The arithmetic circuit 811 calculates the square of the value obtained by subtracting Sg · b ₁ from the input signal, that is, (Y _{k + 1} −Sg · b ₁ ) ² .
The arithmetic circuit 811 calculates the square of the value obtained by adding −Sg · b ₁ + Sg · b ₀ to the input signal, that is, (Y _{k + 1} −Sg · b ₁ + Sg · b ₀ ) ²
Is calculated.

The delay circuit 830 delays the input signal by one time and outputs it. Therefore, the output signal becomes the input signal _Yk one time earlier. The output signal of the delay circuit 830 is input to the addition circuit 826. The addition circuit 826 is
Similarly to the addition circuits 725 and 726 in the first embodiment, the influence of intersymbol interference due to X _k−1 is corrected. The output of the adding circuit 826 is input to the arithmetic circuits 813 and 814. The arithmetic circuit 813 calculates the square of the input signal, that is, (Y _k ) ² . Arithmetic circuit 814, the square of a value obtained by subtracting the Sg · b ₀ from the input signal, i.e. (Y _k -sg
・ Calculate b ₀ ) ² .

The operation circuit 80 is connected to the input of the addition circuit 817.
9 and the output signal of the arithmetic circuit 813 are input, and the sum of them, that is, the value of M0 in Equation 10 is output. The inputs of the addition circuit 818 include the operation circuit 810 and the operation circuit 8
Thirteen output signals are input, and their sum, that is,
The value of M1 at 0 is output. The output signal of the arithmetic circuit 811 and the output signal of the arithmetic circuit 814 are input to the input of the adder circuit 819, and the sum of them, that is, the value of M2 in Expression 10 is output. Output signals of the arithmetic circuits 812 and 814 are input to the input of the adder circuit 820, and the sum of them, that is, the value of M3 in Expression 10 is output.

The outputs of the adders 817 to 820 are input to the minimum value selector 828. Minimum value selection circuit 828
Selects the one with the minimum input metric value from the outputs of the adders 817 to 820 and outputs the corresponding value of X _k . This output is the output of the sign determination circuit as a determination result. The output of minimum value selection circuit 828 is provided to delay circuit 831 and register 832.

The register 832 is a register for holding the code (Sg) of the (1-D) output corresponding to the recording code "1", and stores either "1" or "-1". Take. The value of Sg is expressed as X _k =
When 1 is output, the sign is inverted, and when X _k = 0 is output, the previous value is held as it is. The output of the register 832 is input to the arithmetic circuits 810, 811, 812, 814, and is used as an input signal of the arithmetic in each arithmetic circuit. The output of the register 832 is also supplied to the delay circuit 833, and is output to the outside as the code data of _Xk which is the output of the code determination circuit.

Each of the delay circuits 831 and 833 is a one-time delay circuit. The delay circuit 831 _outputs the _{X k-1} value (1 or 0), the delay circuit _{833, X k-1}
Is output (+1 or -1). Delay circuit 83
The outputs of 1,833 are also input to the arithmetic circuit 815. The arithmetic circuit 815 performs an operation of b ₁ · X _k−1 which is a correction value of the intersymbol interference component. The output of the arithmetic circuit 815 is input to the adding circuit 826.

With the sign determination circuit described in the present embodiment,
A sign determination circuit that is more simplified than the sign determination circuit according to the first embodiment can be realized.

FIG. 8 is a simplified block diagram showing a configuration of a phase error detection circuit using the above-described code determination circuit.

The phase error detector shown in FIG. 8 has basically the same configuration as the phase error detector according to the first embodiment shown in FIG. The phase error detector of the present embodiment is the first
The difference from the embodiment is that the configuration of the sign determination circuit 11 is different as described above, and that the operation in the arithmetic circuit 18 that processes the output of the sign determination circuit 11 is different.

The arithmetic circuit 18 calculates the input signal X _{k at} time k as

[0082]

X _k ′ = (X _k + X _{k -1} ) (Equation 12) A signal X _k ′ is output.

The delay time of the delay circuit 17 is shorter by one time than in the first embodiment. This is the sign determination circuit 1
This is because the decoding delay time at 1 is shortened by simplification of the circuit.

Other points than those described here are the first
Since the phase error detector is not particularly different from the phase error detector according to the embodiment, the description is omitted here.

According to the above-described embodiment, similarly to the first embodiment, a highly accurate phase error signal can be generated. Further, it is possible to simplify the configuration of the code determination device as compared with the first embodiment.

Next, as a third embodiment, a description will be given of a recording / reproducing apparatus in which the accuracy of phase error detection is improved as compared with the recording / reproducing apparatuses in the first and second embodiments.

In the first and second embodiments, code judgment and phase error detection are performed using the response waveform of the class 4 partial response (PR4). An extension class 4 (EPR)
By using a partial response of a more complicated class such as the partial response of 4), erroneous determination can be reduced. In the present embodiment, the sign determination for the phase comparison uses the response waveform of EPR4, and the phase error detection uses P
The response waveform of R4 is used.

FIG. 9 is a simplified block diagram showing the configuration of the data reproducing circuit according to the present embodiment. In the figure, the same reference numerals as in FIG. 2 are used for the components that are the same as those in FIG. 2 in the first embodiment. Hereinafter, mainly the points different from the first embodiment will be specifically described.

In the data reproducing circuit 39 of the present embodiment, the signal whose waveform has been equalized by the equalizer 34 so as to have the response waveform of PR4 is input to the synchronization signal generating circuit 38 'and further equalized. Is input to the container 91. The equalizer 91
From the response waveform of PR4 which is the output signal of the equalizer 34, EP
Waveform equalization for outputting a response waveform of R4 is performed. PR
To make the response waveform of EPR4 the response waveform of EPR4, (1+
A filter having the transfer function of D) may be used. Such a filter is configured as a circuit that implements the operation shown in Expression 12. When a class more complicated than EPR4 is used, an appropriate transfer function according to the class may be applied to the equalizer 91.

The Viterbi decoding circuit 35 reproduces the data output from the equalizer 91 by the Viterbi algorithm, decodes the signal into binary data, and outputs the binary data. At the same time, the output (equalized signal) of the equalizer 34 is supplied to the phase error detector 30.

The output of the equalizer 91 is also supplied to the synchronizing signal generation circuit 38. The synchronizing signal generation circuit 38, based on the signals output from the equalizer 34 and the equalizer 91,
A sampling clock for determining the sample timing in the analog / digital conversion circuit 33 is generated. The synchronization signal generation circuit 38 mainly includes a phase error detector 90, a loop filter 37, and the VCO 36. The functions of the loop filter 37 and the VCO 36 are as follows.
Basically, there is no difference from the first and second embodiments.

FIG. 10 is a simplified block diagram showing the configuration of the phase error detector 90 in the present embodiment.
In the figure, the same components as those of the phase error detector in the first embodiment shown in FIG. 3 are denoted by the same reference numerals as those in FIG.

In this embodiment, the output signal of the equalizer 34 is input to the delay circuit 17, and the output signal of the equalizer 91 is input to the sign determination circuit 11. The sign determination circuit 11
The sign is determined by the DTS algorithm, and the configuration corresponds to the response waveform of EPR4. The number of delay stages of the delay circuit 17 is set to be equal to the total delay time of the delay time of the equalizer 91, the delay time of the sign determination circuit 11, and the delay time of the arithmetic circuit 18. Excluding these points, the phase error detection circuit of the present embodiment also basically
The configuration is the same as that of the phase error detection circuit in the first embodiment.

The transfer function of EPR4 used in this embodiment can be divided as follows.

[0095]

(1−D) ² (1 + D) = (1−D) (1 + 2 · D + D ² ) (Expression 13) As in the second embodiment, the transfer function excluding (1−D) is (1 + 2 · D + D ² ).

For a partial response having an input of {1, 0, -1} and a transfer function of (1 + 2.D + D ² ), a state branch diagram is drawn as in FIGS. 11
The state branch diagram shown in FIG. In the figure, a white circle represents a node, and a state transition is made to the next node by a new input _Xn . The dotted line is a branch corresponding to X _n = 0, and the solid line is a branch corresponding to X _k = 1 or X _k = −1. Numerical values in the figure are values of X _k / Z _k corresponding to each branch. Where X
It is assumed that _k-1 = 0 and _Xk-2 = 0.

[0097] Similar to the first and second embodiment, the value of Z _n corresponding to each branch, when determining the value of the evaluation function metrics as follows.

[0098]

Equation 14] _{M0 (k) = (Y k} ) 2 + (Y k + 1) 2 + (Y k + 2) 2 M1 (k) = (Y k) 2 + (Y k + 1) 2 + ( Y _{k + 2} −Sg) ² M2 (k) = (Y _k ) ² + (Y _{k + 1} −Sg) ² + (Y _{k + 2} −2 · Sg) ² M3 (k) = (Y _k ) ² + (Y _{k + 1} −Sg) ² + (Y _{k + 2} −Sg) ² M4 (k) = (Y _k− Sg) ² + (Y _{k + 1} −2 · Sg) ² + (Y _{k + 2} −Sg) ² M5 (k) = (Y _k −Sg) ² + (Y _{k + 1} −2 · Sg) ² + (Y _{k + 2} −Sg) ² M6 (k) = (Y _k −Sg) ² + (Y _{k + 1} −Sg) ² + (Y _{k + 2} + Sg) ² M7 (k) = (Y _k −Sg) ² + (Y _{k + 1} −Sg) ² + (Y _{k + 2} ) ² ( (Equation 14) However, also here, it is necessary to correct the influence of the intersymbol interference due to the known X _k−1 and X _k−2 .

[0099]

Y _k ′ = Y _k − (X _k−1 + 2 _× X _k−2 ) Y _{k + 1} ′ = Y _{k + 1} − (X _k−1 ) (Equation 15) Is selected from among the metric values obtained in the above, and if the value having the minimum value is any of M0, M1, M2, and M3,
It is determined that X _k = 0, and the minimum values are M4, M5,
If it is one of M6 and M7, it is determined that X _k = Sg. In the latter case, the value is updated as Sg = -Sg.

In this embodiment, a series of processing is performed on one sample of data as described above. When a series of processing for one sample of data is completed, processing for the next data is performed in the same manner.

According to the present embodiment, by the above procedure,
It is possible to perform code determination using simplified FDTS corresponding to ERP4. By performing the code determination using the waveform of the high-order partial response in this manner, it is possible to perform a more accurate code determination as compared with the above-described embodiment, and to generate a high-precision phase difference signal. Becomes possible.

Next, as a fourth embodiment, a case where the recording / reproducing device is an optical disk device will be considered. In the case of an optical disk device, for example, a partial response of class 1 is used as a partial response class. At this time, the impulse response is ｛a ₀ , a ₁ , a
₂ ｝ = {1,1,0}. At this time, Equations 5 and 6 described above are rewritten as Equations 16 and 17 shown below, respectively.

[0103]

M _k = (Y _k −Z _k ) ² + (Y _{k + 1} −Z _{k + 1} ) ² (Equation 16)

[0104]

Equation 17] _{M0 (k) = Y k '} 2 + Y k + 1 2 M1 (k) = Y k' 2 + (Y k + 1 -1) 2 M2 (k) = (Y k '-1) 2 + (Y _{k + 1} −1) ² M3 (k) = (Y _k ′ −1) ² + (Y _{k + 1} −2) ² (Equation 17) Here, similarly to the first embodiment, Y _k 'needs to be corrected.

[0105]

Y _k ′ = (Y _k −X _k−1 ) (Equation 18) In the sign determination, the four metric values obtained from Equation 17 are compared, and the minimum metric value is selected. If the selected metric value is M0 or M1, X _k
= 0. On the other hand, if the selected metric value is M
In the case of 2, M3, it is determined that X _k = 1. As in the other embodiments, the FDTS corresponding to the class 1 partial response is formed by configuring the circuit based on the above determination formula.
A determination circuit can be configured.

FIG. 12 is a simplified block diagram showing the configuration of the phase comparison circuit in the present embodiment.

In the figure, the sign judging circuit 11 judges the sign by the FDTS algorithm based on the above-mentioned equations (17) and (18). The delay circuit 17 is a delay circuit for m time. The value m is affected by the delay time in the sign determination circuit 11, as in the third embodiment. The operation circuit 18 performs an operation represented by (1 + D) on the output of the sign determination circuit 11. By this processing, the original output signal of the class 1 partial response can be obtained. Adder circuit 81 takes the difference between the code the determined Z _k from the output value of the equalizer determines the equalization error. The delay circuit 84 is a delay circuit that delays an input signal by one time and outputs the delayed signal. The addition circuit 83 obtains a difference between the input signal and the output signal of the delay circuit 84. The multiplication circuit 82 obtains the product of the output of the addition circuit 83 and the output of the addition circuit 81.

The outputs of the arithmetic circuit 18 are "0", "1",
Takes any value of "2". Assuming that this output is W _k , an operation of W _k −W _k−1 ) is performed by a circuit including the delay circuit 84 and the addition circuit 83. The result of this operation is obtained as the output of the adder 83. From this output, the slope of the reproduced waveform at time k can be easily determined. That is, when (W _k −W _k−1 ) = 0, the slope is zero, when (W _k −W _k−1 ) = 1, the slope is positive, and (W _k −W _k−1 ) =
If -1, the slope is negative. In the class 1 partial response, the output is 0 to +2 or +2
From 0 to 0 in one time. Therefore, the output of the adding circuit 83 is always one of {+1, 0, -1}.

The value corresponding to the phase error Δφ can be obtained by multiplying the inclination of the reproduced waveform thus obtained by the equalization error obtained by the adding circuit 81.
This multiplication process is performed by the multiplication circuit 82.

As described above, it is possible to realize a phase comparator for a class 1 partial response used in an optical disk or the like.

As described above, by using a high-precision phase difference detector, it is possible to reduce the influence on the phase difference signal due to an error in level determination, thereby performing high-precision phase difference detection. Becomes possible. Further, it is possible to perform the phase control in a high band without extremely increasing the delay time for the phase control with the improvement of the accuracy. As a result, it is possible to provide a recording / reproducing device capable of high-density and high-speed operation.

Further, by using the code determination circuit as described in the second embodiment, an increase in circuit scale can be suppressed, and a low-cost and high-precision recording / reproducing apparatus can be realized. Furthermore, by applying the phase error detection described in the third embodiment, it is possible to perform high-accuracy phase control while suppressing costs.

[0113]

According to the present invention, in a recording / reproducing apparatus, it is possible to increase the accuracy of detecting a phase error performed when generating a synchronizing signal used for data reproduction, thereby achieving high-density and high-speed operation. It is possible to provide a recording / reproducing apparatus suitable for performing.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a magnetic disk device as an example of a recording / reproducing device.

FIG. 2 is a block diagram showing a schematic configuration of a data reproduction circuit 39.

FIG. 3 is a block diagram illustrating a schematic configuration of a phase error detector.

FIG. 4 is a diagram illustrating a tree structure of an FDTS according to the first embodiment.

FIG. 5 is a simplified block diagram illustrating an example of a code determination circuit that implements the FDTS algorithm.

FIG. 6 is a diagram illustrating a tree structure of FDTS in a second embodiment.

FIG. 7 is a simplified block diagram illustrating an example of a code determination circuit based on FDTS in a second embodiment.

FIG. 8 is a simplified block diagram illustrating a configuration of a phase error detection circuit according to a second embodiment.

FIG. 9 is a simplified block diagram illustrating a configuration of a data reproduction circuit according to a third embodiment.

FIG. 10 is a simplified block diagram illustrating a configuration of a phase error detection circuit according to a third embodiment.

FIG. 11 is a diagram illustrating a tree structure of FDTS according to the third embodiment.

FIG. 12 is a simplified block diagram illustrating a configuration of a phase error detection circuit according to a fourth embodiment.

FIG. 13 is a block diagram illustrating a configuration of a phase error detection circuit according to the related art.

[Explanation of symbols]

11 ... Sign judgment circuit, 12, 13 ... Delay circuit, 14,1
5 multiplication circuit, 16 addition circuit, 17 delay circuit, 18
.. Arithmetic circuit, 30 phase error detector, 31 variable gain amplifier, 32 band limiting filter, 33 analog-digital conversion circuit, 34 equalizer, 35 Viterbi detector,
36, VCO, 37, loop filter, 38, synchronization signal generation circuit, 39, data reproduction circuit, 41, recording medium, 4
Reference numeral 2: recording / reproducing amplifier, 43: decoding circuit, 44: encoding circuit, 45: host I / F, 81: addition circuit, 82: multiplication circuit, 83: addition circuit, 84: delay circuit, 90: phase error detection Vessel, 91 ... equalizer

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroshi Ide 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Co., Ltd. Within the Semiconductor Group of Hitachi, Ltd. F-term (Reference) 5D044 BC01 CC04 GL32 GM14 GM15

Claims (14)

[Claims] 1. A recording medium on which information is recorded, a read circuit for generating a reproduction signal corresponding to the information recorded from the recording medium, and a sampling of the reproduction signal in accordance with a supplied clock signal to convert the signal into amplitude information. A conversion circuit that performs sign determination based on the amplitude information, and outputs a digital information corresponding to the information; and a reproduction circuit that outputs digital information corresponding to the information. A phase error detection circuit that performs a code determination of the amplitude information with a short response time, and generates a phase error signal indicating a shift of a sampling timing in the conversion circuit based on the determination result. An oscillation circuit for adjusting the clock signal based on the phase error signal. 2. The information reproducing apparatus according to claim 1, wherein said phase error detection circuit makes said determination according to an FDTS algorithm. 3. The information reproducing apparatus according to claim 2, wherein said reproducing circuit performs a code determination according to a Viterbi algorithm. 4. The information according to claim 3, wherein said reproduction circuit has a decoding circuit for decoding a digital signal corresponding to said information from binary data obtained as a result of code determination according to said Viterbi algorithm. Playback device. 5. The analog-to-digital conversion circuit for sampling the reproduced signal based on the clock signal and outputting a corresponding digital value, performing a waveform equalization based on the digital value, and 4. The information reproducing apparatus according to claim 3, further comprising an equalizer that outputs amplitude information corresponding to the information. 6. The phase error detection circuit according to claim 5, wherein the phase error detection circuit generates the phase error signal from the determination information obtained as a result of the code determination of the amplitude information and the amplitude information.
The information reproducing apparatus according to the above. 7. A first equalizer for waveform-equalizing the digital value to generate first amplitude information, and a second amplitude for equalizing a waveform of the first amplitude signal. 6. The information reproducing apparatus according to claim 5, further comprising a second equalizer for generating information. 8. The phase error detection circuit receives the second amplitude information, performs the code determination according to the FDTS algorithm, and determines the determination result obtained by the determination and the first amplitude information. 8. The information reproducing apparatus according to claim 7, wherein the phase error signal is generated based on the following. 9. An information reproducing apparatus for reproducing digital data from a reproduction signal reproduced from a recording medium, wherein the reproduction signal reproduced from the recording medium is sampled according to a clock signal, converted into amplitude information, and at least two or more signals are reproduced. One piece of digital data is reproduced according to the FDTS algorithm using the amplitude information, and a phase difference, which is a difference between the sampling timings, is obtained using the obtained digital data and the amplitude information, so that the phase difference signal becomes zero. An information reproducing apparatus, further comprising a synchronization signal control circuit for adjusting the clock signal. 10. An information reproducing apparatus for reproducing digital data from a reproduction signal reproduced from a recording medium by using a partial response method, wherein an impulse response length of a partial response is set to N bits, and the reproduction signal is sampled according to a clock signal. To convert to amplitude information,
Data reproduction is performed by the FDTS algorithm using -1 or less pieces of the amplitude information, and a phase difference, which is a difference between sampling timings, is obtained using the obtained data and the amplitude information. An information reproducing apparatus, comprising: a synchronizing signal control circuit for adjusting a sample timing by the clock signal. 11. An information reproducing apparatus for reproducing digital data from a reproduction signal reproduced from a recording medium by using a partial response method, wherein the reproduction signal is sampled in accordance with a clock signal and converted into first amplitude information.
The first amplitude information is waveform-equalized to second amplitude information, data is reproduced by the FDTS algorithm using the second amplitude information, and the obtained data and the first amplitude information are used. An information reproducing apparatus comprising: a synchronization signal control circuit that obtains a phase difference, which is a deviation of the sampling timing, and adjusts a sample timing according to the clock signal so that the phase difference signal becomes zero. 12. An information reproducing apparatus according to claim 9, wherein the information reproducing apparatus is provided independently of the synchronization signal control circuit and includes a data reproducing circuit based on a Viterbi algorithm for reproducing digital data. An information reproducing apparatus characterized by the above-mentioned. 13. A recording medium on which information is recorded, a read circuit for generating a reproduction signal corresponding to the information recorded from the recording medium, and sampling the reproduction signal in accordance with a supplied clock signal to convert the signal into amplitude information. A conversion circuit that performs a code determination based on the amplitude information and outputs digital information corresponding to the information; a code that has a shorter response time than the code determination in the reproduction circuit and is based on a threshold. A phase error detection circuit that performs a code determination of the amplitude information in accordance with an algorithm having a higher determination accuracy than the determination, and generates a phase error signal indicating a sampling timing shift in the conversion circuit based on the determination result; An oscillation circuit that adjusts the clock signal based on the phase error signal obtained by the circuit. Reproducing apparatus. 14. The information reproducing apparatus according to claim 13, wherein said algorithm is an FDTS algorithm.