JP2001250341A - Asymmetry detecting device, jitter detecting device and recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the jitters and asymmetry of regenerative signals by using sampled data. SOLUTION: The asymmetry detecting device has a clock former which forms a clock signal in accordance with the regenerative signals, an analog-to- digital converter which samples the regenerative signals in synchronization with the clock signal, a decider which decides whether the magnitude of each of a plurality of the sample data obtained by sampling is above a prescribed level or not and a detector which detects the asymmetry of the regenerative signal by using the prescribed sample data in accordance with the output from the decider. The jitter detecting device has a clock former which forms the clock signal in accordance with the regenerative signals, an analog-to-digital converter which samples the regenerative signals in synchronization with the clock signal, and the decider which decides whether the magnitude of each of a plurality of the sample data obtained by sampling is above the prescribed level or not and the detector which detects the jitter of the regenerative signal by using the prescribed sample data in a plurality of the sample data in accordance with the output from the decider.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for recording / reproducing digital information using a recording medium, and more particularly, to a technique for detecting jitter or asymmetry of a reproduction signal obtained from a recording medium.

[0002]

2. Description of the Related Art A recording / reproducing apparatus capable of recording digital information on a removable recording medium and reproducing the digital information from the recording medium has been known.
As a recording medium, an optical disk having a recording layer formed of a phase change medium, a magneto-optical medium, or the like is widely used.

In a case where digital information is recorded on an optical disk having a phase change medium using a laser beam, a laser beam having a waveform as shown in FIG. 17A is applied to the optical disk. As a result, a mark having a length corresponding to the digital data to be recorded is recorded on the optical disc, as shown in FIG. The mark recorded on the optical disk is read using a laser beam, and a continuous analog signal as shown in FIG. 17C is detected as a reproduction signal. The analog reproduction signal is converted into a binary signal as shown in FIG. 17D by being sliced at a predetermined level Lv, and digital information is reproduced from the binary signal.

However, when recording is performed using laser light having the same laser power and pulse waveform,
The shape of the recording mark formed on the recording medium may differ depending on the individual difference between the device and the recording medium. If the shape of the recording mark deviates from the desired shape, the waveform of the analog reproduction signal and the waveform of the binary signal also deviate from the original waveform, and the quality of the reproduction signal deteriorates. Therefore, the recording / reproducing apparatus has a problem in that the quality of a reproduced signal when reproducing a signal recorded on a recording medium greatly differs depending on the apparatus or the recording medium.

In order to prevent such a decrease in the reliability of the reproduced signal, test recording and calibration are performed in the recording / reproducing apparatus when a recording medium is loaded. Specifically, data having a known pattern is recorded in a predetermined area on a recording medium, and the signal quality when the recorded data is reproduced is measured. The recording / reproducing apparatus optimizes the characteristics of the reproducing system and optimizes parameters related to recording (recording parameters) based on the measured signal quality.

[0006] The quality of a reproduced signal is determined, for example, by an error rate or jitter (fluctuation in the time axis direction of the reproduced signal). The recording / reproducing apparatus optimizes the characteristics of the reproducing system or the recording parameters so as to minimize the error rate and jitter of the reproduced signal.

Particularly, in a recording medium on which information is recorded by heat using a laser beam or the like, heat interference occurs between the recording patterns before and after the recording medium, so that the shape of the recording mark formed on the medium differs from the desired shape. easy. When recording is performed on such a recording medium, it is necessary to set optimal recording parameters for each recording pattern.

As shown in FIG. 17A, recording parameters include a parameter in a time axis direction such as a recording pulse width and a parameter in a reproduction signal amplitude direction such as a recording power. The above-mentioned jitter can be used to evaluate the parameters of the recording pulse in the time axis direction. On the other hand, to evaluate the parameters in the amplitude direction,
Asymmetry of the reproduced signal, so-called asymmetry, can be used. If the recording power is not appropriate, asymmetry of the reproduced signal occurs.

A configuration of a conventional optical disk recording / reproducing apparatus that performs a calibration operation of a recording parameter using jitter and asymmetry of a reproduced signal will be described below with reference to FIGS.

As shown in FIG. 13, the reflected light from the optical disk 1 is converted into an electric signal by a photodiode or the like at a pickup portion of the optical head 2, whereby an analog reproduction signal corresponding to the digital information recorded on the optical disk. Is generated. The waveform of the reproduced signal thus obtained is shaped by the waveform equalizer 3. The waveform-shaped reproduced signal is supplied to a comparator 15 (see FIG. 14).
Is sliced at a predetermined level Vc by a binarizing circuit 4 and converted into a continuous binary signal.

The binary signal output from the binarizing circuit 4 is
PLL configured by using a phase comparator 5, an LPF (low-pass filter) 6, and a VCO (voltage controlled oscillator) 7
The reproduced clock signal is input to the circuit and is generated in the PLL circuit. In the phase comparator 5, the input binary signal and the clock signal output from the VCO 7 are compared, and these phase errors are detected. The detected phase error is averaged by the LPF 6 configured using a capacitor or the like, and is converted into a voltage for driving the VCO 7. By changing the drive voltage of the VCO 7 in accordance with the magnitude of the phase error in this way, the oscillation frequency of the VCO 7 is feedback controlled so that the phase error output from the phase comparator 5 approaches zero. Thus, 2
A reproduced clock signal synchronized with the value signal can be generated.

As described above, even when the reproduced clock signal synchronized with the binary signal is output from the VCO 7 using the PLL circuit, the length of the recorded mark is different from the ideal length. , A phase error occurs between the binary signal and the reproduced clock signal. The jitter detection circuit 11 calculates the amount of jitter by integrating the absolute value of the phase error output from the phase comparator 5 for a predetermined time or a predetermined zero cross point. This jitter amount is calculated for each recording pattern.

The jitter amount calculated in this way is sent to the recording parameter setting circuit 12. The recording parameter setting circuit 12 determines whether recording parameters such as a recording pulse width are appropriate based on the magnitude of the input jitter amount. If it is determined that the recording parameters are not appropriate, a more appropriate recording parameter is estimated and output to the recording compensation circuit 9.

The recording compensation circuit 9 uses the recording parameters output from the recording parameter setting circuit 12 to convert the recording pattern obtained from the pattern generating circuit 8 into a pulse waveform. The laser drive circuit 10 performs recording on the optical disk 1 according to the pulse waveform formed in this manner. After that, the recorded digital information is reproduced again,
The amount of jitter is determined in the same manner as described above. The recording / reproducing apparatus optimizes the recording parameters until the recording parameter setting circuit 12 determines that the jitter amount is equal to or less than the predetermined level.

Next, a case where a calibration operation is performed using asymmetry of a reproduced signal will be described. FIG. 14 shows a configuration of a conventional asymmetry detection unit. FIG. 15 shows a specific example of a reproduced signal having asymmetry.

As shown in FIG. 14, the asymmetry detecting section is provided with a comparator 15 of the binarizing circuit 4 shown in FIG.
Has an asymmetry detection circuit 17 to which the slice level (center voltage) Vc used in the above is input, a peak-side envelope voltage detection circuit 13 and a bottom-side envelope voltage detection circuit 14.

At the time of test recording, it is assumed that a continuous pattern having a mark / space duty ratio of 50% is recorded for asymmetry detection, and an analog reproduction signal as shown in FIG. 15 is obtained. The peak-side envelope voltage detection circuit 13 detects the peak-side envelope voltage Vp of the reproduction signal, and the bottom-side envelope voltage detection circuit 14 detects the bottom-side envelope voltage Vb of the reproduction signal. Sample and hold circuits are used as the envelope voltage detection circuits 13 and 14.

The reproduced signal is sliced by the comparator 15 at the center voltage Vc and converted into a binary signal.
This center voltage Vc is feedback-controlled using an integrating circuit 16 connected to the output side of the comparator 15. This utilizes the fact that the digital information sequence recorded on the medium has no DC component (DC free), and corrects the fluctuation of the reproduction signal caused by an external factor (for example, the fluctuation of the reflectance of the recording medium). As a result, the duty ratio of the binary signal output from the comparator 15 becomes 50
%. When the center voltage Vc shifts to a higher level than the appropriate level, the on-duty of the output binary signal decreases, and when the center voltage Vc shifts to a lower level than the appropriate level, 2 The on-duty of the value signal increases.

The integration circuit 16 provided for this purpose generates the center voltage Vc by smoothing the output binary signal. By performing such feedback control, the level of the center voltage Vc is set to a level at which the duty ratio of the binary signal output from the comparator 15 becomes 50%.

As a result, as shown in FIG. 15, the center voltage Vc differs from the center level of the amplitude of the reproduced signal. The asymmetry detection circuit 17 includes a peak-side envelope voltage Vp, a bottom-side envelope voltage Vb, and a center voltage Vc.
Is input, and based on these, the asymmetry amount As is calculated by the following equation: As = (Vp + Vb) / 2−Vc. The asymmetry amount As detected in this manner is sent to the recording parameter setting circuit 12 shown in FIG. Recording parameter setting circuit 12
Adjusts the recording power according to the value of the asymmetry amount As. Thus, in the recording / reproducing apparatus, the recording power is calibrated so that the asymmetry amount falls within a desired range.

If test recording is performed as described above and recording parameters are appropriately selected based on the amount of jitter or asymmetry obtained from the reproduced signal, higher-quality reproduction can be performed regardless of individual differences between devices or recording media. Information can be recorded under the condition that a signal can be obtained.

[0022]

On the other hand, in recent years, the recording density of a recording medium has been significantly increased. As a method for reproducing information recorded in such a high density, PRML (Partial Respond) combining partial response equalization (hereinafter referred to as "PR equalization") and Viterbi decoding is used.
A method of detecting a reproduced signal called a "se Maximum Likelihood" method (see U.S. Pat. No. 5,719,843) is used. FIG. 16 shows a signal processing circuit based on a general PRML system.

As shown in the figure, this signal processing circuit adjusts the signal amplitude of a reproduced signal to a predetermined value by an AGC (Automati
c Gain Control) circuit 18 and a waveform equalizer 19 for removing unnecessary high-frequency noise components and emphasizing a necessary signal band.
An A / D converter 20 for sampling a reproduced signal with a channel clock (sampling clock), a digital filter 21 for equalizing the sample data so that the frequency characteristic has a predetermined PR equalization, and discrete sample data. A Viterbi decoder 22 that outputs the most likely (in most probable probability based on information at the preceding and following points) binarized result
A phase comparator 23 for detecting a phase error from discrete sample data, an LPF (low-pass filter) 24 for extracting a reproduced clock, and a D / A converter 25 for converting a digital value output from the LPF 24 into an analog value. , VCO2
6 is provided.

In the signal processing circuit, the A / D converter 20
The original digital information is reproduced from the multi-level sample data obtained by sampling and quantizing the analog reproduction signal by using. The sampling clock in the A / D converter 20 is feedback-controlled by calculating a phase error from the sample data using the phase comparator 23 and controlling the oscillation frequency of the VCO 26 according to the phase error. As a result, sample data is generated with a sampling clock synchronized with the reproduction signal.

Even when an optical disk recording / reproducing apparatus using the above PRML signal processing is used, it is preferable to detect the asymmetry and jitter of the reproduced signal and optimize the recording parameters at the time of recording. However, when such a recording / reproducing apparatus adopts the conventional detection method as shown in FIGS. 13 and 14, there is a problem that the scale of the entire circuit becomes large. In the conventional asymmetry detection circuit shown in FIG. 14, an envelope voltage is detected by using a peak-side envelope voltage detection circuit 13 and a bottom-side envelope voltage detection circuit 14. Further, the conventional jitter detection circuit 11 shown in FIG. 13 detects the amount of jitter by calculating the average of the absolute values of the pulse widths of the phase error detection pulses from the phase comparator 5. Required. As described above, the recording / reproducing apparatus including both the analog signal processing circuit for optimizing the recording parameters and the digital signal processing circuit conforming to the PRML method has a problem that the circuit scale becomes unnecessarily large. Occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and is an apparatus capable of detecting a jitter amount and an asymmetry amount of a reproduction signal from sample data obtained by sampling the reproduction signal. Or to provide a method. It is another object of the present invention to provide a recording / reproducing apparatus for optimizing recording parameters using such a detecting apparatus.

[0027]

An asymmetry detection circuit according to the present invention is an asymmetry detection apparatus for detecting the asymmetry of a reproduced signal obtained by reproducing digital information recorded on a recording medium, wherein A clock generator that generates a clock signal based on a signal, an A / D converter that samples the reproduction signal in synchronization with the clock signal, and a size of each of a plurality of sample data obtained by the sampling. And a determiner for determining whether or not is greater than or equal to a predetermined level, and selecting predetermined sample data among the plurality of sample data based on an output from the determiner, and selecting the selected predetermined sample. A detector for detecting asymmetry of the reproduction signal using data.

In a preferred embodiment, the detector selects sample data having a maximum value and sample data having a minimum value from the plurality of sample data based on an output from the determiner.

In a preferred embodiment, the detector accumulatively adds the sample data having the maximum value and the sample data having the minimum value, thereby detecting the asymmetry of the reproduced signal.

[0030] In a preferred embodiment, the determiner acquires information on the polarity of the sample data, and the detector detects sample data having a maximum value and sample data having a minimum value based on the polarity.

In a preferred embodiment, the clock signal generator detects a phase error between the reproduced signal and the clock signal using the sample data, and feeds back the clock signal based on the detected phase error. Control.

The recording / reproducing apparatus of the present invention comprises the above-mentioned asymmetry detecting apparatus, a recording parameter setting section for setting parameters relating to recording according to the asymmetry of the reproduced signal detected by the asymmetry detecting apparatus,
A recording device for recording digital information on the recording medium using the recording parameters.

A jitter detector according to the present invention is a jitter detector for detecting a jitter of a reproduced signal obtained by reproducing digital information recorded on a recording medium, wherein the clock signal is detected based on the reproduced signal. , An A / D converter that performs sampling of the reproduction signal in synchronization with the clock signal, and a case where each of a plurality of sample data obtained by the sampling has a predetermined level or more. A determination unit that determines whether or not there is a signal; and a detector that detects a jitter of the reproduction signal using predetermined sample data of the plurality of sample data based on an output from the determination unit.

[0034] In a preferred embodiment, the determiner acquires information on the polarity of the sample data.

In a preferred embodiment, the detector detects the jitter of the reproduced signal by selectively accumulating the sample data when the polarity of the plurality of sample data is inverted.

[0036] In a preferred embodiment, the detector accumulates the absolute value of the phase error of the predetermined sample data.

In a preferred embodiment, a signal pattern formed by the plurality of sample data is detected based on an output from the determiner.

In a preferred embodiment, when the signal pattern is determined to be a predetermined pattern, the jitter related to the predetermined pattern can be detected by detecting the jitter.

A recording / reproducing apparatus according to the present invention uses the above-described jitter detecting apparatus, a recording parameter setting section for setting parameters relating to recording in accordance with the jitter of a reproduced signal detected by the jitter detecting apparatus, and using the recording parameters. A recording device for recording digital information on the recording medium.

The asymmetry detection method according to the present invention is a method for detecting the asymmetry of a reproduced signal obtained by reproducing digital information recorded on a recording medium, wherein a clock signal is generated based on the reproduced signal. Performing the sampling of the reproduction signal in synchronization with the clock signal; and accumulating and adding the selected sample data of the plurality of sample data obtained by the sampling, thereby obtaining the reproduction signal. Detecting asymmetry.

A jitter detection method according to the present invention is a method for detecting jitter of a reproduced signal obtained by reproducing digital information recorded on a recording medium, and generating a clock signal based on the reproduced signal. Performing the sampling of the reproduction signal in synchronization with the clock signal; and accumulating and adding the selected sample data of the plurality of sample data obtained by the sampling, thereby obtaining the reproduction signal. Detecting jitter.

According to the asymmetric detection method of the present invention, a multi-level equalized output is obtained by equalizing a reproduced signal from a recording medium by a partial response, and an equalizing output having a maximum value among the equalized outputs is provided. Detecting the asymmetry of the reproduced signal by cumulatively adding the output and the equalized output having the minimum value.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an optical disk recording / reproducing apparatus according to an embodiment of the present invention. Hereinafter, a case where test recording is performed using the illustrated recording / reproducing apparatus will be described.

In test recording, the optical disk controller 39 outputs the initially set recording parameters to the recording compensating circuit 41, and the pattern generating circuit 40 outputs a predetermined recording pattern to the recording compensating circuit 41. Recording compensation circuit 4
1 generates a laser emission control pulse waveform corresponding to a recording pattern using the input recording pattern and recording parameters. The laser drive circuit 42 drives the optical head 28 according to the laser emission control pulse waveform, and records digital information on the optical disk 27.

In order to check whether the recording state at this time is good, the digital information recorded on the optical disk 27 is reproduced.

First, a reproduction laser is irradiated onto the optical disk 27 using the optical head 28. The light reflected from the optical disk 27 is converted into an electric signal using a photodiode or the like in the pickup section of the optical head 28, and an analog reproduction signal is generated. The waveform of the generated reproduction signal is shaped by a waveform equalizer 29 after being amplified. The waveform-shaped reproduced signal is sampled and quantized in an analog-to-digital converter (A / D converter) 30 configured using a plurality of comparators and the like, whereby sample data having a multi-level level is generated. Is done. The sample data is output from the A / D converter 30 as a digital signal. Note that the sampling frequency in the A / D converter 30 is a VCO (voltage controlled oscillator) 3
5 is determined based on the output.

The band limiting circuit 31 removes unnecessary low frequency components that can be included in the quantized reproduction signal (sample data). The band-limited sample data is output to the phase comparison processing block 32 and the digital filter 43.

The phase comparison processing block 32 generates a reproduction signal and a clock signal (ie, V
The phase error with the output of the CO 35 is detected. A method for detecting this phase error will be described later. An LPF (low-pass filter) 33 determines a frequency component to be followed by a VCO (voltage controlled oscillator) 35 from the detected phase error. L
The signal output from the PF (low-pass filter) 33 is
The signal is converted into an analog signal by a digital-analog converter (D / A converter) 34 and used as a control voltage of the VCO 35. As described above, in the present embodiment, the phase comparison processing block 32 and the LPF 33 that perform digital signal processing
, A D / A converter 34, and a VCO 35
A circuit is configured, and the oscillation frequency of the VCO 35 is feedback-controlled so that the magnitude of the phase error approaches zero. In this way, a clock signal synchronized with the reproduction signal is generated.

On the other hand, the digital filter 43 shapes the waveform of the output from the band limiting circuit 31 so as to achieve a predetermined partial response equalization (PR equalization). An equalized output from the digital filter 43 is output to a Viterbi decoder 44.
And a maximum likelihood binarized output is generated. 2
The digitized output is sent to the next-stage digital signal processing circuit via the optical disk controller 39. Error correction processing and the like are performed in this digital signal processing circuit, and desired reproduction data can be obtained.

The recording / reproducing apparatus of this embodiment is provided with an asymmetry detection processing block 37 and a jitter detection processing block 38 for detecting the asymmetry and the jitter of the reproduced signal based on the output from the phase comparison processing block 32.

The asymmetry detection processing block 37 includes a band limiting circuit 31 and a phase comparison processing block 32.
, Multi-valued discrete sample data SD generated by the A / D converter 30 is input. Further, polarity determination information POL for the sample data SD is input. The asymmetry detection processing block 37 calculates digital asymmetry information As using the sample data SD selected based on the polarity determination information POL. The asymmetry information As is sent to the optical disk controller 39.

On the other hand, the jitter detection processing block 38 includes:
The absolute value Abs of the phase error detected by the phase comparison processing block 32 and the polarity determination information POL are input.
The jitter detection processing block 38 detects a signal pattern indicated by the sample data SD from the polarity determination information POL, and detects a phase error absolute value A related to the sample data SD.
The digital jitter information Jr is calculated by using the bs. The jitter information Jr is also sent to the optical disk controller 39.

Based on the digital asymmetry information As input from the asymmetry detection processing block 37 and the digital jitter information Jr input from the jitter detection processing block 38, the optical disk controller 39 adjusts recording parameters such as recording power and recording pulse width. Determine if it is appropriate. If it is determined from the asymmetry information As or the jitter information Jr that the initial recording parameters are not appropriate, the optical disk controller 39
Estimates a more appropriate parameter, and sets a new recording parameter in the recording compensation circuit 41. Test recording is performed again using the recording parameters updated in this manner. The recording / reproducing apparatus performs test recording repeatedly until it is determined that the recording parameters are appropriate, and optimizes the recording parameters.

Hereinafter, more specific configurations of the asymmetry detection processing block 37 and the jitter detection processing block 38 will be described with reference to FIG.

The asymmetry detection processing block 37
A multi-level level determination unit 50 for performing a multi-level level determination of the sample data SD sent from the A / D converter 30 via the band limiting circuit 31 and the phase comparison processing block 32.
And an asymmetry calculation means 60 for calculating digital asymmetry information As based on an asymmetry information calculation permission command Ea issued according to the determination result by the multi-value level determination means 50.

The multi-level level determination means 50 determines the polarity of the sample data SD and outputs polarity determination information POL. The multi-level level determination means 50 determines the maximum value of the sample data SD based on the polarity determination information POL. A peak value detecting means 54 for detecting (or identifying) sample data (maximum data) SDmax having the minimum value and sample data (minimum data) SDmin having the minimum value among the sample data SD. The peak value detecting means 54 in the multi-value level determining means 50 is the maximum data SD
It is configured to output an asymmetry information calculation permission command Ea when detecting the max or the minimum data SDmin.

The asymmetry calculating means 60 calculates digital asymmetry information As by accumulatively adding the sample data SD when the permission command Ea from the peak value detecting means 54 is input.

The asymmetry detection processing block configured as described above selectively accumulates the data having the maximum value and the data having the minimum value among the sample data, and calculates the asymmetry amount of the reproduced signal from the addition result. Detected. The reason why the asymmetry amount conventionally calculated using the analog circuit can be digitally detected in this way is that the sample data is data sampled by the clock formed using the PLL circuit,
This is because, when asymmetry occurs in the reproduced signal, the asymmetry amount is reflected in the sample value.
For example, when a signal as shown in FIG. 15 is reproduced, if sampling is performed with a synchronized clock, the center voltage V
Sample data corresponding to c (reference sample data)
And sample data corresponding to the peak-side envelope voltage and the bottom-side envelope voltage (that is, sample data having a maximum value and sample data having a minimum value) are repeatedly generated. The value of the reference sample data is ideally 0
When set to be, each sample value of the maximum sample data and the minimum sample data,
It is detected as a value having different magnitudes on the positive and negative sides. The difference between the sample values has a value corresponding to the asymmetry amount of the reproduced signal. Therefore, by adding the maximum value and the minimum value of the sample data, it is possible to calculate the same asymmetry amount as the above-mentioned conventional asymmetry amount As.

The jitter detection processing block 38 includes a phase error absolute value generating means 70 for generating the absolute value Abs of the phase error between the reproduction signal and the sampling clock using the sample data SD, and the multi-level level determination. Means 5
The sample polarity determination means 52 used also at 0
A recording pattern extraction unit 80 for extracting a recording pattern KP of the sample data SD based on the polarity determination information POL generated by the sample polarity determination unit 52.
And the extracted recording pattern KP as a reference pattern KP
th, a pattern determination unit 85 that outputs a jitter information calculation permission command Ej when they match, and a phase error from the phase error absolute value generation unit 70 when the jitter information calculation permission command Ej is input. And a jitter calculating means 90 for calculating digital jitter information Jr by accumulating the absolute values Abs.

In the jitter detection processing block configured as described above, the recording pattern is determined using the polarity determination information POL, and the jitter amount related to the recording pattern is calculated from the phase error absolute value Abs of the predetermined sample data. . In this way, the amount of jitter for each recording pattern can be calculated separately, so that appropriate recording parameters can be set for each recording pattern.

As shown in FIG. 2, in this embodiment, the circuit provided in the phase comparison processing block 32 is used as the sample polarity determination means 52 and the phase error absolute value generation means 70. However, the present invention is not limited to such a configuration.

Next, specific circuit configurations of the phase comparison processing block 32, the asymmetry detection processing block 37, and the jitter detection processing block 38 will be described. Here, the case where the PR (a, b, b, a) system is used as the PR equalization system and 8-16 modulation is used as the recording code will be described as an example. The aforementioned a and b are arbitrary positive constants. For details of the signal reproducing method using the PR equalization method, see, for example, US Pat. No. 5,719,84.
No. 3.

In the PR (a, b, b, a) equalization method, the frequency characteristics of a recording / reproducing signal processing circuit including a recording medium such as the optical disk 27 have a predetermined PR (a, b, b, a) equalization. The waveform of the reproduced signal is shaped so that At this time, the sample data SD output from the band limiting circuit 31 is:
Ideally, “0”, “a”, “a + b”, “a + 2”
b "and" 2a + 2b ", where" -ab "," -b ", and" 0 "with reference to" a + b "for easy understanding. ”,
It is assumed that five values “b” and “a + b” are taken.

FIG. 3 is a circuit diagram showing a specific logic circuit configuration of the phase comparison processing block 32. FIG. 4 is an n-bit parallel flip-flop circuit DFF ₁ shown in FIG.
FIG. 5 is a circuit diagram showing a specific logic circuit configuration of FIG.
Is a circuit diagram showing a specific logic circuit configuration of the selector SEL ₁ in FIG. 3, FIG. 6 is a state transition diagram of the signal / information of each part in the phase comparison process block 32.

The reproduced signal from the optical disk 27 is shown in FIG.
When the waveform shown in FIG. 6A is input to the A / D converter 30, sampling is performed based on a clock signal as shown in FIG. 6B, and quantization is performed as shown in FIG. You. The quantized data has the above five values “0”, “b”, “a + b”, “−b”, “−ab”.
Take one of: Here, since a sine wave is taken as an example of the reproduction signal, “0”, “b”, “a + b”,
"B", "0", "-b", "-ab", "-b" are repeated.

It should be noted that the above-described multi-level level judging means 50
Determines which of the above five values the sample data SD takes, and outputs the permission command Ea, which is the result of the determination, to the asymmetry calculating means 60.

The phase comparison processing block 32 shown in FIG.
Is an n-bit data type (delay type) flip-flop circuit DFF _{1 to} DFF ₄ , an adder circuit ADD _1, and a single data type (delay type) flip-flop circuit F
F ₁₁ , FF ₁₂ , exclusive OR circuit EOR, inverting circuit Inv, absolute value calculating circuit ABS, and selector SEL ₁
And

An n-bit parallel flip-flop circuit D
As shown in FIG. 4, each of the FF _{1 to} DFF ₄ is an n-piece data type (delay type) flip-flop FF _1.
FF _n are connected in parallel. When a signal as shown in FIG. 6C is input to DFF ₁ , DFF ₁
FIG. 6D delayed by one clock from FF ₁
Is output.

The adder ADD ₁ receives the n-bit sample data SD and the sample data SD obtained by delaying the sample data SD by one clock via the DFF ₁ . Addition circuit ADD ₁ performs an addition of both, MSB of the addition result (Most S
ignificant Bit (the most significant bit). In the case of ideal PR (a, b, b, a) equalization,
0 + b = b, b + (a + b) = a + 2b, (a + b) +
b = a + 2b, b + 0 = b, 0 + (− b) = − b, (−
b) + (− ab) = − a−2b, (−ab) + (−)
b) = − a−2b, (−b) + 0 = −b,
Consequently, the result added by the adding circuit ADD ₁ is, "- a
-2b "," -. B "," b "," take four values of a + 2b "adding circuit ADD ₁ outputs the MSB of the addition result.

MSB output from adder ADD ₁
Indicates whether the average value of adjacent sample data SD is equal to or greater than a reference value (“0” in this example) or less than the reference value. Based on the output MSB, polarity determination information POL indicating the polarity of the sample data SD as shown in FIG. 6E is obtained. This polarity determination information POL corresponds to the recorded digital information. Note that the reason why the polarity determination information POL is formed using the MSB of the addition result is that, as shown in FIG. 12A or FIG. However, even if it actually has a slightly deviated value such as -1 or 1 due to the influence of jitter or the like, the polarity determination information POL corresponding to the recorded digital information can be obtained. It is. 12 (a) to 12 (i) correspond to FIGS. 6 (a) to 6 (i), respectively, and state transition of signal / information when the sampling clock signal is advanced with respect to the input reproduction signal. FIG.

As described above, the sample polarity determining means 52 including the n-bit parallel flip-flop circuit DFF ₁ , the adding circuit ADD ₁ , and the flip-flop FF ₁₁
The polarity determination information POL formed in the step (1) is used as the peak value detection means 5 in the asymmetry detection processing block 37.
4 and the recording pattern extracting means 80 in the jitter detection processing block 38. However, in the present embodiment, in order to perform timing adjustment, and it is output via a flip-flop FF _11, which is provided as a delay element. FIG. 6E shows the delayed polarity determination information POL.

MSB of result of addition by adder ADD ₁
Changes from “L” to “H” or from “H” to “L” indicates that the reproduction signal crosses the value “0”. At this time, a zero cross point is detected. MSB and the MSB are flip-flop FF ₁₁
When the exclusive OR with the value delayed by one clock is calculated by the exclusive OR circuit EOR, in the case of the combination of “H” and “L”, and in the case of the combination of “L” and “H”, Only in this case, the output of the exclusive OR circuit EOR becomes “H”. Therefore, from the exclusive OR circuit EOR, the output “H” corresponds to the zero cross point of the reproduction signal, and the zero cross point detection signal CR as shown in FIG.
OSS is output. The zero cross point detection signal CROSS is output to the gate of the LPF 33. However, and outputs via the flip-flop FF ₁₂ as a delay element for LPF33 for timing adjustment.

Next, a method for detecting a phase error will be described. FIG. 5 shows a selector S provided for detecting a phase error.
Shows a specific circuit configuration of the EL _1. Selector SEL ₁
Has an n-bit parallel flip-flop circuit DFF ₁
Are input, and the sample data A of n bits and the sample data B obtained by inverting the sample data A by the inverting circuit Inv are input. The selector SEL ₁ uses the MSB output from the adder ADD ₁ as a select signal,
The sample data A and the sample data B are switched and selected based on the value of the MSB. As a result, the selector SEL ₁ a phase error εφ as shown in FIG. 6 (g) is outputted. However, an n-bit parallel flip-flop circuit DFF provided as a delay element for the LPF 33 for timing adjustment
Output via _two .

When a phase error has occurred, the sample data SD corresponding to the zero cross point has a value other than "0" according to the magnitude of the phase error. However, these sample data need to have the same polarity using the inverting circuit as described above. For example, FIGS.
As shown in (i), when the channel clock (sampling clock) is ahead of the input signal, the sample data when the zero cross point detection signal CROSS becomes “H” has a negative value (“−1”). And a positive value ("1"). On the other hand, the phase error εφ generated using the inverting circuit is always a negative value (“−
1 ″). The phase error εφ thus generated
Is input to the LPF 33, and V is input through the D / A converter 34.
It is converted to the control voltage of CO35.

[0076] Further, as shown in FIG. 3, the output from the n-bit parallel flip flop circuit DFF ₁ (data sample data SD was 1 clock delay) is input to the absolute value calculation circuit ABS. Absolute value calculation circuit ABS
Takes the absolute value of the sample data SD, and outputs the jitter calculating unit 90 in the jitter detecting block 38 as a phase error absolute value Abs through the n-bit parallel flip flop circuit DFF ₃ as delay elements for timing adjustment . The absolute value Abs of the phase error is shown in FIG.
(H). Thus, so that the n-bit parallel flip flop circuit DFF ₁ and the absolute value calculation circuit ABS and n-bit parallel flip flop circuit DFF ₃ in the phase comparison process block 32 constitutes the phase error absolute value generating means 70 .

The phase comparison processing block 32 outputs sample data SD delayed by two clocks by n-bit parallel flip-flop circuits DFF ₁ and DFF ₂ . FIG. 6I shows the sample data SD delayed by two clocks in this manner. This sample data SD
Is input to the asymmetry calculation means 60 in the asymmetry detection processing block 37.

FIG. 7 shows an asymmetry detection processing block 3
7 is a circuit diagram showing a specific logic circuit configuration of a peak value detecting means 54 and an asymmetry calculating means 60 in FIG. Also, FIGS. 8 (a) to (i) and FIGS. 9 (j) to
(U) includes the following asymmetry detection processing block 3
7 shows the signals processed. 8A to 8I.
7 is a view similar to FIGS. 6A to 6I. FIG. However, in FIGS. 8A to 8I, the sample values 0, b, a + b, -b, and -ab shown in FIGS. 6A to 6I are 0, A, B, C, Indicated by D.

The peak value detecting means 54 includes flip-flops FF ₂₁ , FF ₂₂ , FF ₂₃ , an adder ADD _2, and a maximum / minimum value detector DET. Flip-flop FF _21, as shown in FIG. 9 (j), the polarity judgment information P which is input from the sample polarity determining circuit 52
The OL (see FIG. 8C) is delayed by one clock. Flip-flop FF _22, as shown in FIG. 9 (k), the polarity judgment information P that has been delayed by the flip-flop FF ₂₁
OL is further delayed by one clock, and the flip-flop F
F _23, as shown in FIG. 9 (l), the flip-flop F
Further 1 polarity determination information POL delayed by F ₂₂
Delay the clock. So four signals shifted by one clock is added by the adding circuit ADD _2. Although the input is "0000" the addition result when the to the summing circuit ADD ₂ becomes "0", the timing of the sample data SD "B" at this time is output from the DFF ₅ (in FIG. 6 "a + b") Is shown. When the input to the adder ADD ₂ is “000”
1 "becomes a sample data SD this time is" 1 "the addition result is when the" A "input to. Adder circuit ADD ₂ showing the timing of a" (FIG. 6 "b)" 0011 "
In this case, the addition result is "2". At this time, the timing indicates that the sample data SD is "0". Adder circuit A
Input to the DD ₂ is "0111" the addition result when the can becomes a "3" indicates the timing of sample data SD "C" at this time (in FIG. 6 "-b"). When the input to the addition circuit ADD2 is "1111", the addition result is "4". At this time, the sample data SD indicates the timing of "D"("-ab" in FIG. 6).

As shown in FIG. 9 (m), the addition circuit ADD
₂ (“0”, “1”, “2”, “3”,
"4") is input to the maximum / minimum value detection circuit DET. The maximum value / minimum value detection circuit DET has asymmetry information only when the input addition result is “0” and “4” (strictly, only when the addition result is “0” and “4”). The calculation permission command Ea (see FIG. 9 (n)) is output to the asymmetry calculation means 60. As can be seen from FIGS. 9 (m) and 9 (o), the fact that the addition result “0” is output means that the value of the sample data SD is “B”.
(“A + b” in FIG. 6) corresponds to detecting data, and the fact that the addition result “4” is output means that
When the value of the sample data SD is "D" (in FIG. 6, "-a-
b ") corresponds to detecting data.

The asymmetry calculating means 60 has an n-bit parallel flip-flop circuit DFF ₅ as a delay element.
When, a selector SEL _2, and an addition circuit ADD _3, a selector SEL _3, n-bit parallel flip-flop circuit D
It comprises FF ₆ , DFF ₇ and counter CONT ₁ . n-bit parallel flip-flop circuit DFF
₅ , DFF ₆ and DFF _{7 have} the same configuration as that of FIG.

[0082] When the maximum and minimum value detection circuit DET of the peak value detecting means 54 outputs the asymmetry information calculation permission command Ea, sample data SD of the maximum value to the selector _{SEL 2 (= "B" =} "a + b") Alternatively, either the minimum value (= "D" = "-ab") is input. At this time, the selector SEL ₂ outputs the maximum value or the minimum value to the addition circuit ADD _3. At other times, that is, when the maximum / minimum value detection circuit DET does not output the asymmetry information calculation permission command Ea, the selector S
EL ₂ selects and outputs "0" of the fixed value to the addition circuit ADD ₃ (FIG. 9 (p)). Adder circuit ADD ₃ is, n-bit parallel flip-flop circuit as a register DFF
N-bit accumulated value stored in ₆ (FIG. 9 (t))
When adds the output from the selector SEL _2. The addition result (FIG. 9 (s)) is stored in the n-bit parallel flip flop circuit DFF ₆ as register via the selector SEL _3. That is, n as a register
The bit parallel flip-flop circuit DFF ₆ accumulates only the maximum value and the minimum value of the sample data SD. This corresponds to calculating the asymmetry amount of the reproduction signal from the optical disk 27.

As shown in FIG. 9 (q), the counter CONT ₁ counts the number of times of input of the asymmetry information calculation permission command Ea from the maximum value / minimum value detection circuit DET. , An n-bit parallel flip-flop circuit DF as a gate
And outputs the enable signal (FIG. 9 (r)) to F _7, open the gate, the optical disk controller cumulative value between the maximum value and the minimum value accumulated so far as the digital asymmetry information As (Fig 9 (u)) Output to 39.

At this time, the counter CONT ₁ controls the selector SEL ₃ to select a fixed value “0”. As a result, the cumulative value of the n-bit parallel flip flop circuit DFF ₆ as registers are reset to "0".

FIGS. 10A and 10B show specific examples of the reproduced signal having asymmetry. In the case of a reproduced signal as shown in FIG. 10A, the detected asymmetry amount has a negative value, and the output digital asymmetry information As also has a negative value. Therefore, the optical disk controller 39
Outputs a recording parameter such that the asymmetry amount shifts to the plus side to the recording compensation circuit 41. In the case of a reproduced signal as shown in FIG. 10B, the detected asymmetry amount has a positive value, and the output digital asymmetry information As also has a positive value. Accordingly, the optical disk controller 39 outputs to the recording compensation circuit 41 a recording parameter that causes the asymmetry amount to shift to the minus side. Recording compensation circuit 4
1 controls the laser drive circuit 42 to output an appropriate laser emission control pulse waveform. The optical disk controller 39 controls the optical disk controller 39 until the optical disk controller 39 falls within a predetermined asymmetry amount based on the asymmetry detection result as described above.
The calibration operation is repeated to ensure the performance of the disk recording / reproducing device.

10A and 10B show an example of a reproduction signal in which a specific pattern is repeated. However, the asymmetry detection processing block 37 having the above-described configuration reproduces a random pattern. Even if it ’s a signal,
The asymmetry amount can be detected.

FIG. 11 shows the configuration of the jitter detection processing block 38. The jitter detection processing block 38 includes a recording pattern extraction unit 80, a pattern determination unit 85, and a jitter calculation unit 90.

The polarity judgment information POL from the sample polarity judging means 52 is input to the recording pattern extracting means 80, and the polarity judging information POL is sequentially shifted by a clock, thereby obtaining the recording pattern KP of the sample data SD. Is extracted. The recording pattern extraction unit 80 includes a shift register configuration in which cascaded nine flip-flops FF ₄₁ ~FF _49.

The pattern determining means 85 determines whether the reference pattern K
Pth is provided with a 10-input AND gate AND ₁₀ which is provided as a logic circuit that is set in advance. Recording pattern extraction inputs and front half four to the first flip-flop FF ₄₁ in unit 80 the flip-flop FF ₄₁
10-input AND gate A as output from FF ₄₄
Is connected to the five input terminals of the ND _10, and is connected to another five input terminals of the output is inverted 10-input AND gate AND ₁₀ the remaining second half of the five flip-flops FF ₄₅ ~FF _49. 10 input AND gate AND ₁₀ the pattern determination unit 85 that is configured using the polarity judgment information P
OL is, for example, “0”, “0”, “0”,
“0”, “0”, “1”, “1”, “1”, “1”,
A recording pattern KP of the sample data SD that changes to “1” is extracted.

The 10-input AND gate AND shown in FIG.
_In the case of ₁₀ , the 10-input AND gate AND ₁₀ permits the calculation of the jitter information when "0" is detected continuously for 5 channel clocks from the optical disk 27 and then "1" is detected continuously for 5 channel clocks. The command Ej will be output. In this case, it is customarily said that a recording pattern of "5T-5T" was detected. Here, T is the cycle of the channel clock.

The jitter calculating means 90 includes five n-bit parallel flip-flop circuits D for timing adjustment.
The FF ₁₁ ~DFF _15, a selector SEL _4, adder circuit A
And DD _4, a selector SEL _5, and n-bit parallel flip flop circuit DFF _16, DFF _17, the counter CON
And a T _2. The configuration of the n-bit parallel flip-flop circuits DFF _{11 to} DFF ₁₇ is similar to that of FIG.

The 10-input AN as the pattern determining means 85
When the D gate AND ₁₀ outputs the jitter information calculation permission command Ej, the selector SEL ₄ outputs the input absolute phase error value Abs to the addition circuit ADD ₄ . Otherwise, i.e., when the 10-input AND gate AND ₁₀ does not output jitter information calculation permission command Ej, the selector S
EL ₄ selects a fixed value “0” and outputs it to the addition circuit ADD ₄ .

When the jitter information calculation permission command Ej is output, the n-bit parallel flip-flop circuit DFF ₁₁
Because doing the timing adjusted using ～DFF _15, the selector SEL _4, sample data always corresponds to the zero crossing point (i.e., sample data when changing polarity) phase error absolute value abs of outputs . The number of n-bit parallel flip-flop circuits (that is, the number of clocks to be delayed) is determined according to the recording pattern to be detected, and when the polarity is changed when the jitter information calculation permission command Ej is output. It is sufficient that the phase error absolute value abs of the sample data is output. As described above, in the present embodiment, the recording pattern is extracted using the polarity determination information POL, and the phase error absolute value abs of the sample data corresponding to the zero cross point in this recording pattern is used to extract the jitter related to the extracted recording pattern. I try to measure the amount.

The adder ADD ₄ has a register n
The n-bit accumulated value stored in the bit parallel flip-flop circuit DFF ₁₆ is added to the n-bit phase error absolute value Abs from the selector SEL ₄ . N of the addition result as the register via the selector SEL ₅
It is stored in bit parallel flip flop circuit DFF _16. That is, the n-bit parallel flip-flop circuit DFF ₁₆ as a register accumulates the phase error absolute value Abs relating to the recording pattern KP.

Thus, the jitter of the reproduction signal from the optical disk 27 can be calculated for each recording pattern. Counter CONT ₂ has 10 inputs AN
The number of inputs of the jitter information calculation permission command Ej from the D gate AND ₁₀ is counted. When the count value reaches a predetermined value, an enable signal is output to the n-bit parallel flip-flop circuit DFF ₁₇ as a gate. Then, the gate is opened, and the accumulated value of the phase error absolute value Abs accumulated so far is output to the optical disk controller 39 as digital jitter information Jr.

At this time, the counter CONT ₂ controls the selector SEL ₅ to select a fixed value “0”. As a result, the accumulated value of the n-bit parallel flip-flop circuit DFF ₁₆ as a register is reset to “0”.

The optical disk controller 39 sets the recording parameters such that the amount of jitter approaches zero to the recording compensation circuit 4.
Output to 1. Based on the output recording parameters, the recording compensation circuit 41 controls the laser drive circuit 42 to output an appropriate laser emission control pulse waveform. The optical disk controller 39 repeats the calibration operation until the jitter amount falls within a predetermined amount on the basis of the above-described jitter detection result, thereby ensuring the performance of the disk recording / reproducing apparatus.

In the above example, the case of detecting the jitter of the 5T-5T recording pattern KP has been described. However, the recording pattern KPj (j = 1, 2, 3,...) Is known in advance. Since it is preferable to determine the jitter amount for each of these recording patterns,
The recording / reproducing apparatus is provided with pattern determination means 85 corresponding to each recording pattern KPj. When the number of input bits in the pattern determining means 85 is 10,
Five n-bit parallel flip-flop circuits D in recording pattern extracting means 80 and jitter calculating means 90
The FF _{11 to} DFF ₁₅ can be used, but if not, it is necessary to provide a recording pattern extracting means 80 and a delay element (shift register) corresponding to each.

As described above, by providing the jitter detection processing blocks 38 as many as the number of recording patterns requiring the calibration operation, even when recording information composed of a plurality of recording patterns randomly combined is reproduced. Then, a predetermined recording pattern is extracted from the reproduced signal, and the amount of jitter relating to the extracted recording pattern can be obtained. Therefore, it is possible to appropriately calibrate the recording parameters.

As described above, in the recording / reproducing apparatus of the present embodiment, the waveform-shaped reproduced signal is quantized by the A / D converter 30, and the quantized data is subjected to partial response equalization. This sample value is determined to be a multi-value level in the asymmetry detection processing block 37, and sample values corresponding to the maximum and minimum levels are cumulatively added. In the jitter detection processing block 38, the amount of jitter of a specific pattern is detected from the reproduced signal. The optical disk controller 39 optimizes the recording parameters based on the detected asymmetry amount and the jitter amount, and performs a calibration operation so that the asymmetry amount and the jitter amount are equal to or less than a predetermined allowable value. The effect of variations in device characteristics can be reduced, and highly reliable recording performance can be achieved.

The embodiments of the present invention have been described above in detail. However, the present invention is not limited to the above embodiments, and may include the following embodiments. (1) In the above embodiment, the jitter detection processing block 38 is configured to accumulate the phase error absolute value Abs, but instead accumulates the square of the phase error and elapses a predetermined time. A configuration may be adopted in which a later accumulated value or an accumulated value after a predetermined number of additions is output as digital jitter information Jr. (2) In the above-described embodiment, the sample value of the sample data SD corresponding to the zero cross point is used as it is as the phase error and the absolute value of the phase error. , The slope of the rising or falling edge of the reproduced signal is obtained, and the result of normalizing the sample value of the sample data SD corresponding to the above-mentioned zero cross point (that is, the result of conversion into a shift amount in the time axis direction) is used as a phase error and a phase error. It may be used as an absolute value. (3) In the above embodiment, the multi-level level determination is performed by directly using the sample data SD output from the band limiting circuit 31 in the asymmetry detection processing block 37, and the digital asymmetry information As is calculated. Instead, the multi-value level of the sample data is indirectly determined using the decoding result of the Viterbi decoder 44 at the subsequent stage, and the data having the maximum value and the minimum value are specified from the determination result. May be obtained. (4) In the above embodiment, the band limiting circuit 31
The polarity determination information POL is generated based on the sample data SD output from the PDP, and the digital jitter information Jr is calculated based on the polarity determination information POL. Instead, the decoding result of the Viterbi decoder 44 is used. In this case, the recording pattern KPj may be detected by using this method, and the jitter amount may be obtained from the detection result.

[0102]

According to the present invention, jitter and asymmetry of a reproduced signal can be appropriately detected using data sampled from the reproduced signal with a sampling clock synchronized with the reproduced signal. Therefore, in a recording / reproducing apparatus including a digital signal processing circuit conforming to the PRML system, jitter and asymmetry can be detected without unnecessarily increasing the circuit scale.
If the recording parameters are optimized based on the jitter and asymmetry detected in this way, and digital information is recorded using the optimized recording parameters, the signal quality during reproduction can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a disk recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a more specific electrical configuration of an asymmetry detection processing block and a jitter detection processing block in the disk recording / reproducing apparatus of FIG.

FIG. 3 is a circuit diagram showing a specific logic circuit configuration of a phase comparison processing block in the disk recording / reproducing apparatus of FIG. 1;

FIG. 4 is a circuit diagram showing a specific logic circuit configuration of the n-bit parallel flip-flop circuit in FIG. 3;

FIG. 5 is a circuit diagram showing a specific logic circuit configuration of a selector in FIG. 3;

FIG. 6 is a state transition diagram of signals / information of each unit in a phase comparison processing block of the disk recording / reproducing apparatus of the embodiment.

7 is a circuit diagram showing a specific logic circuit configuration of a peak value detection unit and an asymmetry calculation unit in the asymmetry detection processing block of FIG. 2;

FIG. 8 is a state transition diagram of signals / information of each unit in a phase comparison processing block of the disk recording / reproducing apparatus according to the embodiment, and shows a form similar to FIG. 6;

FIG. 9 shows the signal / signal shown in FIG.
It is a state transition diagram of information.

FIG. 10 is a diagram showing a specific example of a reproduced signal having asymmetry.

11 is a circuit diagram showing a specific logic circuit configuration of a recording pattern extraction unit, a pattern determination unit, and a jitter calculation unit in the jitter detection processing block of FIG.

FIG. 12 is a state transition diagram of signals / information of each unit in the phase comparison processing block, which is different from FIG.

FIG. 13 is a block diagram illustrating an electrical configuration of a disk recording / reproducing apparatus according to the related art.

FIG. 14 is an explanatory diagram of a technique of asymmetry detection in a conventional technique.

FIG. 15 is a diagram showing a specific example of a reproduction signal with asymmetry.

FIG. 16 is a schematic diagram of a general PRML (partial response maximum likelihood) signal processing circuit.

17A and 17B are diagrams for explaining a recording operation and a reproducing operation of digital data with respect to an optical disc, and FIG.
Shows a laser beam waveform, (b) shows a mark recorded on a disk, (c) shows a reproduced analog signal, and (d) shows a binarized signal.

[Explanation of symbols]

 27 Optical Disk 28 Optical Head 29 Waveform Equalizer 30 A / D Converter 31 Band Limiting Circuit 32 Phase Comparison Processing Block 33 LPF 34 D / A Converter 35 VCO 37 Asymmetry Detection Processing Block 38 Jitter Detection Processing Block 39 Optical Disk Controller 40 Pattern Generation circuit 41 Recording compensation circuit 42 Laser 43 Digital filter 44 Viterbi decoder 50 Multi-level level determination means 52 Sample polarity determination means 54 Peak value detection means 60 Asymmetry calculation means 70 Phase error absolute value generation means 80 Recording pattern extraction means 85 Pattern determination Means 90 Jitter calculation means DET Maximum / minimum value detection circuit SD Sample data εφ Phase error CROSS Zero cross point detection signal Abs Phase error absolute value POL Polarity judgment information Ea Asymmet Reason information calculation permission command Ej Jitter information calculation permission command KP recording pattern KPth reference pattern

Continued on the front page (72) Inventor Haruharu Miyashita 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (16)

[Claims] 1. An asymmetry detection device for detecting the asymmetry of a reproduced signal obtained by reproducing digital information recorded on a recording medium, wherein the clock generator generates a clock signal based on the reproduced signal. An A / D converter that samples the reproduction signal in synchronization with the clock signal; and determines whether each of a plurality of sample data obtained by the sampling is at least a predetermined level. A determiner for determining, selecting predetermined sample data among the plurality of sample data based on an output from the determiner, and detecting asymmetry of the reproduction signal using the selected predetermined sample data. An asymmetry detection device comprising: a detector; 2. The asymmetry detection according to claim 1, wherein the detector selects sample data having a maximum value and sample data having a minimum value among the plurality of sample data based on an output from the determiner. apparatus. 3. The asymmetry detection apparatus according to claim 2, wherein the detector cumulatively adds the sample data having the maximum value and the sample data having the minimum value, thereby detecting the asymmetry of the reproduced signal. 4. The asymmetry detection apparatus according to claim 2, wherein the determiner acquires information on the polarity of the sample data and detects sample data having a maximum value and sample data having a minimum value based on the polarity. . 5. The clock signal generator detects a phase error between the reproduced signal and a clock signal using the sample data, and performs feedback control of the clock signal based on the detected phase error. Item 2. An asymmetry detection device according to item 1. 6. The asymmetry detection device according to claim 1, a recording parameter setting unit configured to set parameters related to recording according to the asymmetry of the reproduction signal detected by the asymmetry detection device, and using the recording parameter. A recording device for recording digital information on the recording medium. 7. A jitter detector for detecting jitter of a reproduction signal obtained by reproducing digital information recorded on a recording medium, wherein the clock generator generates a clock signal based on the reproduction signal. An A / D converter that samples the reproduction signal in synchronization with the clock signal; and determines whether each of a plurality of sample data obtained by the sampling is at least a predetermined level. And a detector that detects jitter of the reproduced signal using predetermined sample data of the plurality of sample data based on an output from the determiner. 8. The jitter detection device according to claim 7, wherein the determiner acquires information on a polarity of the sample data. 9. The jitter detection device according to claim 8, wherein the detector detects the jitter of the reproduction signal using sample data when the polarities of the plurality of sample data change. 10. The jitter detecting apparatus according to claim 7, wherein the detector accumulates an absolute value of a phase error of the predetermined sample data. 11. The jitter detection device according to claim 7, wherein a signal pattern formed by the plurality of sample data is detected based on an output from the determiner. 12. The jitter detecting apparatus according to claim 11, wherein when the signal pattern is determined to be a predetermined pattern, the jitter related to the predetermined pattern can be detected by detecting the jitter. 13. A jitter detection device according to claim 7, a recording parameter setting unit for setting a parameter relating to recording in accordance with a jitter of a reproduction signal detected by the jitter detection device, and using the recording parameter. A recording device for recording digital information on the recording medium. 14. A method for detecting asymmetry of a reproduced signal obtained by reproducing digital information recorded on a recording medium, comprising: generating a clock signal based on the reproduced signal; Sampling the reproduction signal in synchronization with the signal; and detecting asymmetry of the reproduction signal by accumulatively adding sample data selected from a plurality of sample data obtained by the sampling. An asymmetry detection method comprising: 15. A method for detecting jitter of a reproduced signal obtained by reproducing digital information recorded on a recording medium, comprising: generating a clock signal based on the reproduced signal; Sampling the reproduction signal in synchronization with a signal; and detecting jitter of the reproduction signal by accumulatively adding sample data selected from a plurality of sample data obtained by the sampling. And a jitter detection method including: 16. A step of obtaining a multi-value level equalized output by equalizing a reproduced signal from a recording medium with a partial response, and having an equalized output having a maximum value and a minimum value among the equalized outputs. Detecting the asymmetry of the reproduced signal by cumulatively adding the equalized output.