JPH11296987A - Reference amplitude level updating circuit, adaptive type viterbi decoder, and recording and reproducing device - Google Patents

Reference amplitude level updating circuit, adaptive type viterbi decoder, and recording and reproducing device

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Publication number
JPH11296987A
JPH11296987A JP9034398A JP9034398A JPH11296987A JP H11296987 A JPH11296987 A JP H11296987A JP 9034398 A JP9034398 A JP 9034398A JP 9034398 A JP9034398 A JP 9034398A JP H11296987 A JPH11296987 A JP H11296987A
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Japan
Prior art keywords
reference amplitude
amplitude level
level
old
reproduction signal
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Application number
JP9034398A
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Japanese (ja)
Inventor
Masaaki Hara
雅明 原
Original Assignee
Sony Corp
ソニー株式会社
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Priority to JP9034398A priority Critical patent/JPH11296987A/en
Publication of JPH11296987A publication Critical patent/JPH11296987A/en
Granted legal-status Critical Current

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Abstract

An object of the present invention is to provide a reference amplitude level updating circuit in which a circuit scale is reduced and an operation speed is improved. SOLUTION: A level comparing means 1a compares the level of an input reproduction signal with an old reference amplitude level. If the comparison result shows that the level of the input reproduction signal is higher than the old reference amplitude level, the reference amplitude level updating means 1b increases the old reference amplitude level by a certain value to generate a new reference amplitude level,
When the level of the input reproduction signal is lower than the old reference amplitude level, the reference amplitude level is updated by reducing the old reference amplitude level by a certain value and generating a new reference amplitude level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference amplitude level updating circuit, an adaptive Viterbi decoding device, and a recording / reproducing control device, and more particularly to updating a reference amplitude level determined by intersymbol interference caused by a combination of recording data. A 6-level 4-state adaptive Viterbi decoding apparatus and a recording medium for performing maximum likelihood decoding by adaptively updating a reference amplitude level determined by intersymbol interference generated by a combination of a reference amplitude level updating circuit and recording data The present invention relates to a recording / reproduction control device for performing reproduction control of a recording signal recorded on a recording / reproduction device.

[0002]

2. Description of the Related Art In the field of digital mass storage such as a digital VTR, a hard disk, and an optical disk, reproduction equalization and detection called PRML (Partial Response Maximum Likelihood) are actively performed.

[0003] This is a multi-valued partial response equalization that enables recording and reproduction in a narrow band, and a good error rate compared to bit-by-bit identification by recursively calculating the likelihood of state transition. And the maximum likelihood decoding in which

[0004] A typical algorithm of maximum likelihood decoding is Viterbi decoding, and a decoding device that realizes this is called a Viterbi decoding device. FIG. 9 is a diagram showing a configuration of a conventional adaptive Viterbi decoding device used in a recording / reproducing system.
The reference amplitude level updating circuit 100 holds a reference amplitude level determined by intersymbol interference caused by a combination of recording data.

[0005] The branch metric calculation circuit 200
A branch metric which is a relative value of a Euclidean distance between the reference amplitude level and the input reproduction signal is calculated. The addition / comparison / selection circuit 300 adds a branch metric along a path to generate a path metric.
Then, selection information for selecting the minimum path metric is created, and the path metric is updated based on this selection information.

The path metric storage circuit 500 performs an overflow prevention process so that a path metric does not overflow. The path storage circuit 400 receives the selection information and outputs an identification result serving as a path metric history. The reference amplitude level updating circuit 100 sequentially updates the reference amplitude level based on a combination of the reproduction signal and the identification result, and adaptively controls the reference amplitude level.

Here, the reference amplitude level updating circuit 100
Performs a calculation such as “α × reproduced signal + (1−α) × reference amplitude level before update”, and outputs the calculation result as a newly updated reference amplitude level.

[0008] As described above, the conventional adaptive Viterbi decoding device has a very large circuit scale because it is realized by using each operation circuit such as addition and multiplication. For this reason, Japanese Patent Application No. 9-065653, which is a conventional technique, performs a bit shift operation for updating a reference amplitude level based on an input reproduction signal, thereby replacing a multiplier with a selector and reducing the circuit scale. ing.

[0009]

However, in the above prior art, since the multiplier is replaced with a selector and an adder circuit is required, the circuit scale cannot be said to be sufficiently reduced. , Which hindered high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and an object of the present invention is to provide a reference amplitude level updating circuit which reduces the circuit scale and improves the operation speed.
It is another object of the present invention to provide an adaptive Viterbi decoding device which can reduce the circuit scale and improve the operation speed.

Still another object of the present invention is to provide a recording / reproducing control device in which the circuit scale is reduced and the operation speed is improved.

[0012]

According to the present invention, there is provided a reference amplitude level updating circuit for updating a reference amplitude level determined by inter-symbol interference caused by a combination of recording data. Level comparison means for comparing the level of the input reproduction signal with the old reference amplitude level, and when the level of the input reproduction signal is higher than the old reference amplitude level, the old reference amplitude level is increased by a certain value. A new reference amplitude level is generated, and when the level of the input reproduction signal is smaller than the old reference amplitude level, the old reference amplitude level is reduced by a certain value to generate the new reference amplitude level. A reference amplitude level updating circuit, comprising: a reference amplitude level updating means for updating the amplitude level.

Here, the level comparing means compares the level of the input reproduced signal with the old reference amplitude level. The reference amplitude level updating means generates a new reference amplitude level by increasing the old reference amplitude level by a certain value when the level of the input reproduction signal is higher than the old reference amplitude level as a result of the comparison. When the level is smaller than the old reference amplitude level, the reference amplitude level is updated by reducing the old reference amplitude level by a certain value and generating a new reference amplitude level.

Further, in a 6-value 4-state adaptive Viterbi decoding apparatus which performs maximum likelihood decoding by adaptively updating a reference amplitude level determined by intersymbol interference caused by a combination of recording data, input / output Level comparing means for comparing the signal level with the old reference amplitude level, and when the result of the comparison indicates that the level of the input reproduction signal is higher than the old reference amplitude level, the old reference amplitude level is increased by a certain value. Generating a new reference amplitude level, and when the level of the input reproduction signal is smaller than the old reference amplitude level, reducing the old reference amplitude level by a certain value to generate the new reference amplitude level. A reference amplitude level updating unit configured to update a reference amplitude level, and a reference amplitude level updating unit including the input reproduction signal and the new reference amplitude level. A branch metric calculation unit that calculates a branch metric that is a relative value of the Euclidean distance; a path metric generation unit that adds the branch metric along the path reaching four states to generate a path metric; A maximum likelihood determination control unit that generates selection information for selecting the smallest one and updates the path metric based on the selection information; And a discrimination result output control unit that outputs a discrimination result which is the old reference amplitude level, which is the history of the adaptive Viterbi decoding apparatus.

Here, the level comparing means compares the level of the input reproduced signal with the old reference amplitude level. The reference amplitude level updating means generates a new reference amplitude level by increasing the old reference amplitude level by a certain value when the level of the input reproduction signal is higher than the old reference amplitude level as a result of the comparison. When the level is smaller than the old reference amplitude level, the reference amplitude level is updated by reducing the old reference amplitude level by a certain value and generating a new reference amplitude level. The branch metric calculation unit calculates a branch metric which is a relative value of a Euclidean distance between the input reproduction signal and the new reference amplitude level. The path metric generator is
Along the path reaching the four states, a branch metric is added to generate a path metric. The maximum likelihood determination control unit creates selection information for selecting the smallest path metric, and updates the path metric based on the selection information. The identification result output control unit receives the selection information and outputs an identification result that is a path metric history and an old reference amplitude level for each of the four states.

Further, in a recording / reproduction control device for controlling reproduction of a recording signal recorded on a recording medium, an input / reproduction signal for generating an input / reproduction signal after performing analog / digital conversion and waveform equalization of the recording signal. A generation unit, level comparing means for comparing the level of the input reproduction signal with the old reference amplitude level, and as a result of the comparison, if the level of the input reproduction signal is higher than the old reference amplitude level, When the level of the input reproduction signal is smaller than the old reference amplitude level, the old reference amplitude level is reduced by a certain value to generate the new reference amplitude. A reference amplitude level updating unit configured to update the reference amplitude level by generating a level,
A branch metric calculation unit that calculates a branch metric that is a relative value of a Euclidean distance between the input reproduction signal and the new reference amplitude level; and adding a branch metric along a path that reaches four states to obtain a path metric. A path metric generating unit to generate, create selection information for selecting the smallest one of the path metrics, and a maximum likelihood determination control unit that updates the path metric based on the selection information; and receiving the selection information. An identification result output control unit that outputs an identification result that is the history of the path metric and is the old reference amplitude level for each of the four states; and a maximum likelihood decoded data for a state path based on the selection information. A maximum likelihood decoded data output unit for outputting as a demodulated data, and a demodulated data generation unit for demodulating the maximum likelihood decoded data to generate demodulated data , Reproduction control apparatus characterized by having a are provided.

Here, the input reproduction signal generation unit performs analog / digital conversion and waveform equalization of the recording signal,
Generate an input reproduction signal. The level comparing means compares the level of the input reproduction signal with the old reference amplitude level. The reference amplitude level updating means generates a new reference amplitude level by increasing the old reference amplitude level by a certain value when the level of the input reproduction signal is higher than the old reference amplitude level as a result of the comparison. When the level is smaller than the old reference amplitude level, the reference amplitude level is updated by reducing the old reference amplitude level by a certain value and generating a new reference amplitude level. The branch metric calculation unit calculates a branch metric which is a relative value of a Euclidean distance between the input reproduction signal and the new reference amplitude level. The path metric generation unit adds a branch metric along a path that reaches the four states to generate a path metric. The maximum likelihood determination control unit creates selection information for selecting the smallest path metric, and updates the path metric based on the selection information. The identification result output control unit receives the selection information and outputs an identification result that is a path metric history and an old reference amplitude level for each of the four states. The maximum likelihood decoded data output unit outputs a state path based on the selection information as maximum likelihood decoded data. The demodulated data generator demodulates the maximum likelihood decoded data to generate demodulated data.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram of a reference amplitude level updating circuit according to the present invention. Reference amplitude level update circuit 1
Performs an update of a reference amplitude level determined by intersymbol interference caused by a combination of recording data.

The level comparing means 1a is, for example, a DVD (Di
gital Video Disc) and compares the level of the input playback signal with the old reference amplitude level. When the level of the input reproduction signal is higher than the old reference amplitude level as a result of the comparison, the reference amplitude level updating means 1b generates a new reference amplitude level by increasing the old reference amplitude level by a certain value, and generates the new reference amplitude level. Is smaller than the old reference amplitude level, the old reference amplitude level is reduced by a certain value to generate a new reference amplitude level, thereby updating the reference amplitude level. The equation for updating the reference amplitude level is represented by the following equation.

[0020]

Newrv = oldrv + 2 × ((signal> oldrv) −1) (1) where newrv indicates the new reference amplitude level, oldrv indicates the old reference amplitude level, and signal indicates the level of the input reproduction signal.

Signal> oldrv is 1 when the magnitude relation is true, and is 0 otherwise. The specific configuration of the reference amplitude level updating circuit 1 will be described later.

Next, the adaptive Viterbi decoder according to the present invention will be described. FIG. 2 is a diagram showing the principle of the adaptive Viterbi decoding device according to the present invention. The adaptive Viterbi decoder 1-1 has been described with reference to FIG. 1 for a 6-level 4-state Viterbi decoder effective for a digital recording / reproducing system using a recording modulation code having a minimum inversion width of 2. The reference amplitude level updating circuit 1 is applied.

The reference amplitude level updating unit 10 updates a reference amplitude level determined by intersymbol interference caused by a combination of recording data. The branch metric calculation unit 20 calculates a branch metric that is a relative value of the Euclidean distance between the input reproduction signal and the new reference amplitude level.

The path metric generating unit 31 adds a branch metric along a path reaching the four states to generate a path metric. The maximum likelihood determination control unit 32 creates selection information for selecting the smallest path metric,
Update the path metric based on the selection information.

The identification result output control unit 40 receives the selection information and outputs an identification result as a path metric history for each of the four states. Next, an embodiment of the adaptive Viterbi decoding device according to the present invention will be described. FIG. 3 is a block diagram of the adaptive Viterbi decoding device 1-1.
In the following description, [M: N] means M-N + 1 bits from lower N bits to upper M bits.

A branch metric calculation circuit (BMC: Br
Anch Metric Calculator) 20a corresponds to the branch metric calculator 20, and calculates a relative value of a Euclidean distance between the reproduction signal z [k] and the reference amplitude level to obtain a branch metric. This may be calculated over m clocks.

If the branch metrics for Viterbi decoding in 6 values and 4 states are b000 to b111, the equation becomes as shown in equation (2). The reference amplitude levels c000 to c111 are provided from a reference amplitude level updating circuit 10a corresponding to the reference amplitude level updating unit 10.

[0028]

B000 = (c000−2 × z [k + m]) × c000 b001 = (c001−2 × z [k + m]) × c001 b011 = (c011-2 × z [k + m]) × c011 b100 = (c100) −2 × z [k + m]) × c100 b110 = (c110−2 × z [k + m]) × c110 b111 = (c111−2 × z [k + m]) × c111 (2) Addition / Comparison / Selection Circuit (ACS) : Add Compare & Selec
t) 30a corresponds to the path metric generation unit 31 and the maximum likelihood determination control unit 32, adds the branch metric and the past path metric, compares them, selects the smallest one, and selects path selection information. Is output to the path storage circuit 50.

A path metric storage circuit (MMU:
Metric Memory Unit) 50 stores the latest path metric and supplies it to the addition / comparison / selection circuit 30a, and also processes the path metric so as not to overflow.
The path metric is updated as follows by combining these two operations.

[0030]

M00 [k] = s00 × (m00 [k−1] + b000) +! s00 * (m01 [k-1] + b001) m01 [k] = m11 [k-1] + b011 m10 [k] = m00 [k-1] + b100 m11 [k] = s11 * (m11 [k-1] + b111) ) +! s11 × (m10 [k-1] + b110) (3) Further, the selection information of the path metric is s00, and for s11,

[0031]

S00 = (m00 [k-1] + b000) <(m01 [k-1] + b001) s11 = (m11 [k-1] + b111) <(m10 [k-1] + b110) (4) Is defined.

A path storage circuit (PMU: Path Memory Uni)
t) 40a is a circuit corresponding to the identification result output control unit 40 and storing the identification result as the history of each state and sequentially updating it.

Each of the four states is composed of an n-stage shift register. The identification result of the state i bits before is pm00 [i] to pm11 [i] (i = 1
~ N)

[0034]

[Equation 5] pm00

[0] = 0; pm00 [i] = pm00 [i-1] x s00 + pm00 [i-1] x! s00 pm01

[0] = 0; pm01 [i] = pm11 [i-1] pm10

[0] = 1; pm10 [i] = pm00 [i-1] pm11

[0] = 1; pm11 [i] = pm11 [i−1] × s11 + pm10 [i−1] ×! s11... (5) For s00 and s11, parallel load or serial shift is performed according to s00 and s11.
Parallel loading is always performed for s01 and s10.
If the number n of stages of the shift register is sufficiently large,

[0035]

(6) Since pm01 [n] = pm11 [n] = pm10 [n] = pm00 [n] (6), for example, pm00 [n] is output as the identification result dec [kn]. I do.

Reference amplitude level updating circuit (RAU: Refere)
nce Amplitude Update) 10a is c000-c111
By receiving the initial value of from the outside and updating and changing it sequentially according to the combination of the input amplitude and the identification result,
The function of adaptively controlling the reference amplitude level is added to the Viterbi decoding device.

For example, pm00 [n] = 0, pm00
If [n-1] = 1 and pm00 [n-2] = 1, this is a combination of the identification results for the input z [k-n + 2].

[0038]

C011 ← α × z [k−n + 2] + (1−α) × c011 (7) c011 may be updated and used for the calculation of the next branch metric.

Here, α is an update coefficient. Since the initial value of the reference amplitude level is given externally and is not directly related to the operation, it is omitted in the figure. Next, a specific configuration of the reference amplitude level updating circuit 10a will be described. FIG. 4 is an overall block diagram of the reference amplitude level updating circuit 10a.

The shift register (SHR) 11 has m + n
-2 stages of registers, delaying the input z [k + m] until the identification result is determined. Demultiplexer (D
MP) 12 demultiplexes the latest three bits of identification results. Update operation circuit (UPD) 13-1 to 13
Step -6 performs an update operation.

First, the latest three bits of identification results are demultiplexed as follows.

[0042]

[Expression 8] u000 =! pm00 [n] ×! pm00 [n-1] ×! pm00 [n-2] u001 =! pm00 [n] ×! pm00 [n-1] x pm00 [n-2] u011 =! pm00 [n] x pm00 [n-1] x pm00 [n-2] u100 = pm00 [n] x! pm00 [n-1] ×! pm00 [n-2] u110 = pm00 [n] x pm00 [n-1] x! pm00 [n-2] u111 = pm00 [n] x pm00 [n-1] x pm00 [n-2] (8) Then, in the update operation circuits 13-1 to 13-6,

[0043]

C000 ← u000 × α × (z [k−n + 2] −c000) + c000 c001 ← u001 × α × (z [k−n + 2] −c001) + c001 c011 ← u011 × α × (z [k−n + 2) ] -C011) + c011 c100 ← u100 × α × (z [k−n + 2] −c100) + c100 c110 ← u110 × α × (z [k−n + 2] −c110) + c110 c111 ← u111 × α × (z [k− (n + 2] -c111) + c111 (9)

The reproduced signal is an 8-bit signal [7: 0] obtained by expanding the signal converted to 6 bits, and the reference amplitude level is the upper 8 bits used for calculating the branch metric. Is calculated as 16-bit ref [15: 0], and the update coefficient α
Is a [7: 0], the updating circuit:

[0045]

Ref [15: 0] ← update × a [7: 0] × (signal [7: 0] −ref [15: 8]) + ref [15: 0] (10) become. Here, “update” is a flag that permits update calculation of each reference amplitude level.

Next, a case will be described in which the above-described update operation is configured using a conventional multiplier. FIG. 5 is a block diagram of an update operation circuit when the update operation is configured using a multiplier.

An input 8 bit, output 8 bit subtractor (C
= A−B) 13a, input 8 bit, output 16 bit multiplier (C = A × B) 13b, input 8 bit, output 8 bit adder (C = A + B) 13c, 16 bit 2-to-1 Selector (16-bit SEL) 13d, 16-bit D
It is composed of a type latch (16-bit DFF) 13e.

Here, a [7: 0] = 8′h01 is α =
A [7: 0] = 8′h10 is α =
This corresponds to 1/16. However, the reference amplitude level updating circuit must perform each operation during one clock cycle. Therefore, the presence of such a multiplying circuit 13b greatly restricts the operation speed and leads to an increase in circuit scale.

Next, a case will be described in which the above-described update operation is configured using a conventional selector. FIG. 6 is a block diagram of an update operation circuit when the update operation is configured using a selector.

The difference from FIG. 5 is that a [7: 0] is changed to b [2:
0], and a multiplier 13b of input 8 bits and output 16 bits is a bit shift selector (B = A≪SE
L) 13b-1. This selector 13b-1
Is based on 16-bit input data A [15: 0] and a 3-bit selection signal SEL [2: 0].

[0051]

[11] B [15: 0] = A [7: 0] ≪SEL [2: 0] (11) Here, ≪ indicates an operator for shifting bits upward, and B [15: 0] is obtained by adding 0 to the lower part of A [7: 0] by the number of SEL [2: 0].
Is output. For example, SEL [2: 0] =
If 3'b101 = 3'h5,

[0052]

## EQU12 ## B [15: 0] = {3'b000, A [7: 0], 5'b00000} (12), and 5 bits of 0 below A [7: 0] and 3 bits above The result of adding 0 to B [15: 0]. Therefore, UPD using bit shift is

[0053]

Expression 13: ref [15: 0] ← update × {(signal [7: 0] −ref [15: 8])} b [2: 0]} + ref [15: 0] (13) Will do. a [7: 0] and b [2:
If the relationship between the 0] and a = 2 b, corresponding to alpha = 1/256 with b = 3'h0 if a = 8'h01, b = 3'h
If it is 4, then a [7: 0] = 8'h10, corresponding to α = 1/16. Therefore, as shown in the following equation (14), the calculation in FIG.

[0054]

Ref [15: 0] ← update × a [7: 0] × (signal [7: 0] −ref [15: 8]) + ref [15: 0] (14) is a [7: 0] is 1, 2, 4, 8, 16, 32, 64,
It can be seen that, except for being limited to the value of 128, the circuit of FIG. 6 can also be realized.

Here, in the actual updating of the reference amplitude level, there is no disadvantage that a [7: 0] cannot take an arbitrary integer from 0 to 255. Therefore, the circuit of FIG. It is possible to realize an update operation equivalent to.

Next, a specific configuration of the reference amplitude level updating circuit 1 of the present invention will be described. FIG. 7 is a diagram showing a configuration of the reference amplitude level updating circuit 1. The reference amplitude level updating circuit 1 is a circuit replacing (UPD) in FIG.
Here, the magnitudes of signal [7: 0] and ref [7: 0] are compared, and signal [7: 0]> ref [7:
0], the comparator (CMP) 1a that outputs UD = 1, otherwise UD = 0, and ref [7: 0] by one if UD = 1 when update = 1. And if UD = 0 when update = 1, r
ef [7: 0] is counted down by one.

As an operation, when update = 1, s
If signal [7: 0]> ref [7: 0], r
ef [7: 0] is increased by one, and signal [7:
0] ≦ ref [7: 0], ref [7: 0] is set to 1
Smaller.

As described above, the reference amplitude level updating circuit 1 of the present invention can update the reference amplitude level by following the fluctuation of the reproduction signal as in FIGS. Further, since the comparator (CMP) 1a uses only the MSB of the output of the subtractor (AB) 13a, the subtractor (AB)
7 and 5 in consideration of the fact that the circuit scale becomes the same as that of FIG.
6 and FIG. 6, the 8 bit × 8 bit multiplier (C = A × B) 13b, the 8 bit + 8 bit adder (C = A + B) 13c, and the 16-bit 2-input / 1-output selector of FIG. The (16-bit SEL) 13d and the 16-bit (16-bit DFF) 13e are replaced with only the 8-bit up / down counter (UDC) 1b in FIG.

Alternatively, the 8-bit shift operation unit (B
= A≪SEL) 13b-1, 8-bit + 8-bit adder (C = A + B) 13c, 16-bit 2-input / 1-output selector (16-bit SEL) 13d, 16-bit D
The FF (16-bit DFF) 13e is replaced with only the 8-bit up / down counter (UDC) 1b in FIG.

As described above, the reference amplitude level updating circuit 1 of the present invention is configured to update the reference amplitude level based on the comparison result between the level of the input reproduction signal and the old reference amplitude level.

As a result, the circuit can be composed of the comparator (CMP) 1a and the up / down counter (UDC) 1b, so that the circuit scale can be greatly reduced and the operation speed can be improved.

Next, the recording / reproducing control device of the present invention will be described. FIG. 8 is a principle diagram of the recording / reproducing control device of the present invention. The recording and reproduction control device 1-2 controls reproduction of a recording signal recorded on a recording medium. Hereinafter, a case where the recording / reproduction control device 1-2 is applied to a DVD system will be described.

The input reproduction signal generation unit 2a responds to the recording signal read from the DVD disk through the
After performing analog / digital conversion and waveform equalization in synchronization with the LL clock, an input reproduction signal is generated.

The adaptive Viterbi decoding device 1-1 performs Viterbi decoding of the input reproduced signal. The adaptive Viterbi decoding device 1-1 includes the reference amplitude level updating unit 10 described above,
It includes a branch metric calculation unit 20, a path metric generation unit 31, a maximum likelihood determination control unit 32, and an identification result output control unit 40.

The maximum likelihood decoded data output unit 50 further includes a maximum likelihood decoded data output unit 50.
And outputs a state path based on the selected information with the smallest path metric selected as maximum likelihood decoded data.

The demodulation generation data section 2b demodulates the maximum likelihood decoded data to generate demodulated data. For example, the demodulation generation data section 2b performs demodulation control of 8/16 modulation to generate demodulation data.

As described above, the recording / reproduction control device 1-2 of the present invention comprises the adaptive Viterbi decoding device 1 of the present invention.
1 to control recording and reproduction. As a result, the circuit scale can be significantly reduced, and the operation speed can be improved.

In the above description, the reference amplitude level updating circuit 1 is applied to a 6-level 4-state Viterbi decoding apparatus to constitute the adaptive Viterbi decoding apparatus 1-1.
The reference amplitude level updating circuit 1 of the present invention can be applied to a canceller, a local feedback type Viterbi decoding device, and the like.

[0069]

As described above, the reference amplitude level updating circuit of the present invention is configured to update the reference amplitude level based on the result of comparison between the level of the input reproduced signal and the old reference amplitude level. As a result, the circuit scale can be significantly reduced, and the operation speed can be improved.

The adaptive Viterbi decoding apparatus according to the present invention is configured to update the reference amplitude level and perform Viterbi decoding based on the comparison result between the level of the input reproduced signal and the old reference amplitude level. As a result, the circuit scale can be significantly reduced, and an adaptive Viterbi decoding device having an improved operation speed can be configured.

Further, the recording / reproduction control apparatus of the present invention updates the reference amplitude level based on the comparison result between the level of the input reproduction signal and the old reference amplitude level to obtain the maximum likelihood decoded data, Is performed. As a result, the circuit scale can be significantly reduced, and a recording / reproduction control device with an improved operation speed can be configured.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a reference amplitude level updating circuit according to the present invention.

FIG. 2 is a principle diagram of an adaptive Viterbi decoding device according to the present invention.

FIG. 3 is a block diagram of an adaptive Viterbi decoding device.

FIG. 4 is an overall block configuration diagram of a reference amplitude level updating circuit.

FIG. 5 is a block diagram of an update operation circuit when the update operation is configured using a multiplier.

FIG. 6 is a block diagram of an update operation circuit when an update operation is configured using a selector.

FIG. 7 is a diagram showing a configuration of a reference amplitude level updating circuit.

FIG. 8 is a principle diagram of a recording / reproduction control device of the present invention.

FIG. 9 is a diagram showing a configuration of a conventional adaptive Viterbi decoding device used in a recording / reproducing system.

[Explanation of symbols]

1. Reference amplitude level updating circuit, 1a Level comparison means, 1b Reference amplitude level updating means.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. 6 Identification code FI H04L 25/03 H04L 25/03 C

Claims (4)

[Claims]
1. A reference amplitude level updating circuit for updating a reference amplitude level determined by intersymbol interference caused by a combination of recording data, comprising: level comparing means for comparing a level of an input reproduction signal with an old reference amplitude level. As a result of the comparison, if the level of the input reproduction signal is higher than the old reference amplitude level, the old reference amplitude level is increased by a certain value to generate a new reference amplitude level, and the level of the input reproduction signal is Reference amplitude level updating means for updating the reference amplitude level by generating the new reference amplitude level by reducing the old reference amplitude level by a fixed value when the reference amplitude level is smaller than the old reference amplitude level. A reference amplitude level updating circuit, characterized in that:
2. The method of updating the reference amplitude level, wherein the new reference amplitude level is newrv and the old reference amplitude level is o.
ldrv, where the level of the input reproduced signal is signal, newrv = oldrv + 2 × ((signal> ol
2. The reference amplitude level updating circuit according to claim 1, wherein the value of newrv obtained in (drv) -1) is used as the value of the new reference amplitude level.
3. A 6-level 4-state adaptive Viterbi decoding apparatus that adaptively updates a reference amplitude level determined by intersymbol interference caused by a combination of recording data and performs maximum likelihood decoding. Level comparing means for comparing the signal level with the old reference amplitude level, and when the result of the comparison indicates that the level of the input reproduction signal is higher than the old reference amplitude level, the old reference amplitude level is increased by a certain value. Generating a new reference amplitude level, and when the level of the input reproduction signal is smaller than the old reference amplitude level, reducing the old reference amplitude level by a certain value to generate the new reference amplitude level. A reference amplitude level updating unit configured to update a reference amplitude level; and a unit for comparing the input reproduced signal with the new reference amplitude level. A branch metric calculation unit that calculates a branch metric that is a relative value of a grid distance; a path metric generation unit that adds the branch metric along a path reaching four states to generate a path metric; A maximum likelihood determination control unit that creates selection information for selecting the smallest one, and updates the path metric based on the selection information; and receives the selection information and selects the path metric for each of the four states. And a discrimination result output control unit that outputs a discrimination result that is the history of (i) and that is the old reference amplitude level.
4. A recording / reproduction control device for controlling reproduction of a recording signal recorded on a recording medium, comprising: performing an analog / digital conversion and a waveform equalization of the recording signal; and then generating an input reproduction signal. A generation unit, a level comparison unit that compares the level of the input reproduction signal with the old reference amplitude level, and as a result of the comparison, when the level of the input reproduction signal is higher than the old reference amplitude level,
The old reference amplitude level is increased by a certain value to generate a new reference amplitude level. If the level of the input reproduction signal is smaller than the old reference amplitude level, the old reference amplitude level is reduced by a certain value. A reference amplitude level updating unit configured to update the reference amplitude level by generating the new reference amplitude level; and a Euclidean distance between the input reproduction signal and the new reference amplitude level. A branch metric calculation unit that calculates a branch metric that is a relative value of: a path metric generation unit that adds the branch metric along a path reaching four states to generate a path metric; A maximum likelihood determination control unit that generates selection information for selecting one and updates the path metric based on the selection information An identification result output control unit that receives the selection information and outputs an identification result that is the history of the path metric and the old reference amplitude level for each of the four states, based on the selection information A maximum-likelihood decoded data output unit for outputting the state path obtained as the maximum likelihood decoded data, and a demodulation data generation unit for demodulating the maximum likelihood decoded data to generate demodulated data. .
JP9034398A 1998-04-02 1998-04-02 Reference amplitude level updating circuit, adaptive type viterbi decoder, and recording and reproducing device Granted JPH11296987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9034398A JPH11296987A (en) 1998-04-02 1998-04-02 Reference amplitude level updating circuit, adaptive type viterbi decoder, and recording and reproducing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9034398A JPH11296987A (en) 1998-04-02 1998-04-02 Reference amplitude level updating circuit, adaptive type viterbi decoder, and recording and reproducing device

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JPH11296987A true JPH11296987A (en) 1999-10-29

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US7616726B2 (en) 2005-03-11 2009-11-10 Hitachi, Ltd. Optical disk apparatus and PLL circuit
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