JP2004288369A - Viterbi decoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem; conventionally, when reproducing the data recorded on a recording medium by a Viterbi algorithm, a favorable reproducing performance cannot be maintained if there are non-uniformity of recording mark shapes caused by medium characteristics and non-linear distortion of a reproduced waveform. <P>SOLUTION: Based on a decoded data sequence outputted from a path memory 12, a data estimation circuit 14 outputs an estimated data estimating the input data at a point in time before a predetermined bit period earlier than the input data. A target value calculation circuit 15 corrects a target value adopting a difference between the estimated data and the input data as a target value error, and outputs a plurality of 1st target values obtained to a branch metric operation circuit 11 as a plurality of target values. Since the branch metric operation circuit 11 is able to perform branch metric operation based on the plurality of 1st target values approaching to a plurality of averages values with the highest appearance frequency (having a peak in a histogram), the decoding performance can be improved rather than using a fixed target value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a Viterbi decoding method, and more particularly to a Viterbi decoding method for decoding recorded data from a digital recording medium such as an optical disk or a magnetic disk.

  In a reproducing apparatus for a digital recording medium such as an optical disk or a magnetic disk, since the asymmetry of the reproduced signal occurs due to the length and depth of the recording pit, a detection circuit for slicing the reproduced signal at a predetermined threshold and detecting the digital signal. A device (auto slicer) for controlling the slice position based on the asymmetric component of the reproduced signal has been used conventionally. Conventionally, in order for a Viterbi decoder to cope with such asymmetry of a reproduced signal, an asymmetry amount of pit information is detected, corrected pit information is generated based on the asymmetry amount, and this corrected pit information is Viterbi decoded. There is known an "optical information reproducing apparatus" (Japanese Patent Laid-Open No. Hei 6-150549) in which demodulation is performed by a device.

JP-A-6-150549

  However, according to the invention described in Japanese Patent Application Laid-Open No. 6-150549, it is difficult to follow a characteristic change in a recording area only by correcting an area where a known pit is recorded. Difficulty in media application is expected.

  For example, for an isolated waveform having a width of 1T (T is a bit period: the same applies hereinafter), a response waveform having a value of approximately 1,1,1,1 or a so-called transmission characteristic of a partial response (hereinafter abbreviated as PR). When the waveform equalization is performed so as to be (1,1,1,1), and the level (peak value) of the reproduced waveform is approximately -2, -1, 0, 1, 2, for example, the symmetry is obtained. FIG. 10 shows a result of sampling a reproduced signal having a good value at the bit period T, that is, measuring a histogram of peak values at the input position to the Viterbi decoder.

  However, due to power excess or deficiency during recording or a change in the characteristics of the medium, a non-linear distortion that makes it impossible to equalize the waveform to the PR (1,1,1,1) characteristic occurs. As a result, FIG. In some cases, only a reproduced waveform having very poor symmetry as shown in the figure may be obtained. In the example of FIG. 11, the waveform equalizer operates to converge the waveform to the level of −2, −1, 0, 1, and 2. As a result, the variance of the sample that should converge to the level of 2 is large. There is a problem that a conventional Viterbi decoder cannot perform a good decoding operation on an input wave having such a large nonlinear distortion.

  The present invention has been made in view of the above points, and when reproducing recorded data recorded on a recording medium using the Viterbi algorithm, recording power and irregularity of recording mark shapes due to medium characteristics, It is an object of the present invention to provide a Viterbi decoding method capable of maintaining good reproduction performance even when non-linear distortion of a reproduction waveform caused by reproduction characteristics occurs.

The present invention provides a Viterbi decoding method having the following configuration to achieve the above object.
A first step of performing a branch metric operation on the input data using a plurality of target values to generate a selection signal;
A second step of outputting a decoded data sequence obtained by Viterbi decoding input data based on the selection signal;
A third step of delaying the input data by a predetermined bit period;
A fourth step of correcting a target value using a difference between a target value based on the decoded data and the input data delayed in the third step as a target value error, and using the obtained plurality of corrected target values as a plurality of target values; And a viterbi decoding method.

  According to the present invention, the branch metric calculation is performed based on a plurality of first target values approaching a plurality of average values having a highest frequency of appearance (having a peak in a histogram), so that input data having nonlinear distortion is obtained. Also, accurate Viterbi decoding with a smaller error rate than before can be performed.

  Further, according to the present invention, the branch metric calculation based on a plurality of initial target values is performed at the time of calculation start and at the time of error calculation non-convergence. Can be.

  Further, according to the present invention, when the equalized waveform (input data) input to the Viterbi decoder is significantly distorted, each of the plurality of first target values is centered around a median target value. Is made to be symmetrical, based on the corrected target value corresponding to each of the plurality of first target values, the branch metric calculation that minimizes the influence of the distortion of the input data can be performed. Even for input data, accurate Viterbi decoding can be performed without causing asymmetry in the branch metric error calculation.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a Viterbi decoder according to the present invention. As shown in FIG. 1, in this embodiment, a branch metric operation circuit 11 to which input data y _(k) is supplied via an input terminal 10, a path memory 12 for outputting a decoded data sequence, and a path memory 12 A delay circuit 13 having a delay time determined by the length of the data, a data estimating circuit 14 for outputting estimated data Y _(ki) , and a target value calculating circuit 15 for supplying a target value to the branch metric calculating circuit 11. Have been. This embodiment is characterized in that a delay circuit 13, a data estimation circuit 14, and a target value calculation circuit 15 are provided in a conventional Viterbi decoding circuit including a branch metric calculation circuit 11 and a path memory 12.

  In this embodiment, in a reproducing apparatus for a recording medium on which a digital signal whose shortest recording reversal interval is limited to 3T is recorded, transmission is performed so that the transmission characteristic becomes approximately PR (1,1,1,1). A case where the present invention is applied to the case of performing road equalization will be described as an example. Recording media in which the shortest recording inversion interval is limited to 3T include a compact disk (CD) and a DVD (Digital Versatile Disc). In the present embodiment, the case where the shortest recording reversal interval is 3T will be described, but the present invention is also applicable to other recording modulation and transmission path equalization methods.

  FIG. 2A illustrates waveform equalization performed on a solitary wave having a 1T width so as to have a response waveform having a value of approximately 1,1,1,1 or a so-called PR (1,1,1,1) characteristic. FIG. 4B shows a recording waveform in the case where the recording is performed, and FIG. In this embodiment, as shown in FIG. 2B, the reproduced waveform is subjected to waveform equalization so that the level (peak value) becomes approximately -2, -1, 0, 1, 2.

  FIG. 3 shows a state transition diagram corresponding to FIG. In the figure, S0, S1, S2, S3, S4, and S5 indicate the states of the input data (similar to the decoded data), and the symbols attached to the arrows between the states indicate the input bits (input bits) on the left. (1 bit of data), and the right shows the output peak value. FIG. 4 shows a decoding trellis of PR (1, 1, 1, 1) corresponding to the state transition diagram of FIG. As for the symbols attached to the arrows between the states, the left side shows the 1-bit value of the input data, and the right side shows the output peak value as in FIG.

The Viterbi decoder shown in FIG. 1 is a circuit that performs Viterbi decoding using PR (1, 1, 1, 1), and a branch metric operation circuit 11 in the Viterbi decoder is represented by a state transition diagram in FIG. A waveform obtained by sampling the reproduced waveform subjected to the waveform equalization at a bit cycle interval is received as input data y _(k) via a terminal 10, and a five-value target value TU is output from a target value calculation circuit 15 described later. , MU, ZE, ML, and TL, and performs a branch metric operation based on these to output two selection signals 0 and 1. The present embodiment is characterized in that a target value, which has been a fixed value in the past, is changed based on a target value error signal.

FIG. 5 is a circuit diagram of an example of the branch metric operation circuit 11. In the figure, target values TU, MU, ZE, ML, and TL are quintuple peak values "2", "1", "0", "-1", and "-5" shown in the decoding trellis of FIG. 4, respectively. -2 ". The subtracter 21 ₁ performs subtraction of subtracting the target value TL from the input data y _(k), the subtractor 21 ₂ and 21 ₃ performs a subtraction to subtract the target value ML from the input data y _(k), the subtractor 21 ₄ and 21 ₅ performs a subtraction to subtract the target value ZE from the input data y _(k), the subtractor 21 ₆ and 21 ₇ performs a subtraction to subtract the target value MU from the input data y _(k), the subtracter 21 ₈ input data A subtraction of subtracting the target value TU from y _(k) is performed.

Subtractor 21 ₁ to 21 the difference value between the target value corresponding to the ₈ input data y fetched respectively _(k) (error signal) are respectively the square circuit 22 ₁ to 22 ₈ provided corresponding 2 after being squared, is supplied to the adder 23 ₁ to 23 _8, the state S0, S1, S2, S3, S4, metric at time k-1 in _{S5 L 0 (k-1)} , L 1 (k- ₁₎ , L2 _(k-1) , L3 _(k-1) , L4 _(k-1) and L5 _(k-1) . That is, the adder 23 ₁ and 23 ₃ the output signal of the squaring circuit 22 _1, 22 ₃ and metric L _{0 (k-1)} and the sum, adder 23 ₂ is the square circuit 22 _{and second} output signal and metric L _{1 (k-1)} and the sum, an adder 23 _4, 23 _5, 23 _7, respectively squaring circuit 22 _4, 22 _5, 22 ₇ the output signal of the metric _{L 2 (k-1),} L 3 (k _-1), by adding the L 4 _(k-1), the adder 23 ₆ and 23 ₈ squaring circuit 22 _6, 22 ₈ output signals of the metric L _{5 (k-1)} and added.

The comparison circuit 24 compares the levels of both the output signal of the adder 23 ₁ and 23 _2, the adder 23 ₁ of the adder 23 from the selection circuit 25 when less than the output signal towards the output signal adder 23 _{2 1} the output signal, the selected output as metric L _{0 (k)} at time k in the state S0, in the case of the reverse to output the output signal of the adder 23 ₂ from the selection circuit 25 metric L ₀ as _(k) . The time k represents an arbitrary time one bit period T after the time k-1.

On the other hand, the comparator circuit 27 compares the two output signals of the adders 23 ₇ and 23 _8, the adder 23 ₇ adder 23 ₇ from the selection circuit 26 when towards the output signal is less than the output signal of the adder 23 ₈ the output signal, the selected output as metric L _{5 (k)} at time k in the state S5, in the case of the reverse to output the output signal of the adder 23 ₈ from the selection circuit 26 metric L ₅ as _(k) .

The adder 23 _3, 23 _4, 23 ₅ and 23 _6, respectively state S3, S1, S4 and metric L ₃ at time k in _{S2 (k), L 1 (} k), L 4 (k) And L _{2 (k)} are extracted. Further, the selection signals 0 and 1 are extracted from the comparison circuits 24 and 27, respectively. These selection signals are signals indicating which signal is selected in the selection circuits 25 and 26.

As a result, the metrics L _{0 (k)} , L _{1 (k)} , L _{2 (k)} , at time k in the states S 0, S 1, S 2, S 3, S 4 and S 5 output from the branch metric calculation circuit 11 are _obtained . L _{3 (k)} , L _{4 (k)} , and L _{5 (k)} are represented by the following equations, respectively.
L0 _(k) = min [[L0 _(k-1) + (y _(k) -(-2)) ² }, [L1 _(k-1) + (y _(k) -(-1) ) ² ]]
L1 _(k) = L2 _(k-1) + (y _(k) -(0)) ²
L2 _(k) = L5 _(k-1) + (y _(k) -(1)) ²
L3 _(k) = L0 _(k-1) + (y _(k) -(-1)) ²
L4 _(k) = L3 _(k-1) + (y _(k) -(0)) ²
L5 _(k) = min [[L5 _(k-1) + (y _(k) -(2)) ² }, [L4 _(k-1) + (y _(k) -(1)) ² ]]
However, min [a, b] is an operator that outputs the smaller of a and b.

The selection signals 0 and 1 extracted from the branch metric operation circuit 11 having the above configuration are supplied to a path memory 12 as shown in FIG. 1, where a Viterbi-decoded data sequence is generated. For example, as shown in the block diagram of FIG. 6, the path memory 12 includes n selectors 31 _{1 to} 31 _n that perform an operation of selecting one of two input signals according to a selection signal 0, and two selectors 31 _{1 to} 31 _{n according} to a selection signal 1. comprises n selectors 32 ₁ to 32 _n to perform an operation for selecting one of the input signals, the delay elements 33 _to 333 ₆ each having a delay time of the bit period _{T, 34 1 ~34 6, 35} 1 ~35 6 And the majority circuit 36.

0,1 inputted to the selector 31 ₁ of FIG. 6, the delay element 33 _2, 33 ₃ to 1 respectively input, 0 is input to the delay element 33 ₄ and 33 ₅ are inputted to the selector 32 ₁ The value of each one bit of 0 and 1 is finally extracted from the majority circuit 36 as one decoded data sequence by the decoding operation in the path memory 12. Here, the value of each 1-bit corresponds to the value of the decoding trellis shown in FIG.

In this path memory 12, when the selector 31 ₁ outputs L _{0 (k−1)} + (y _(k) − (− 2)) ² as L _{0 (k) in the} metric operation, Selects bit value 0 by selection signal 0 and selects bit value 1 by selection signal 0 when L _{1 (k−1)} + (y _(k) − (− 1)) ² is output . On the other hand, in the selector 32 ₁ , when L _{5 (k−1)} + (y _(k) − (− 2)) ² is output as L _{5 (k) in the} metric operation, the selection signal 1 If bit value 1 is selected and L _{4 (k−1)} + (y _(k) − (− 1)) ² is output, bit value 0 is selected. Similarly, the operations of the other selectors are performed in accordance with the selection signal and Viterbi decoding based on the decoding trellis shown in FIG. 4 is performed.

Although the selector _{31 1 ~31 n, 32 1 ~32} n, the number of such delay elements 33 _to 333 _6, 34 ₁ to 34 _6, 35 ₁ to 35 ₆ is determined by decoding performance, usually of the n Is selected to be about 32.

The decoded data sequence extracted from the path memory 12 in this manner is output from the output terminal 16 in FIG. The data estimation circuit 14 outputs to the target value calculation circuit 15 the estimation data Y _(ki) i times before k based on the length of the path memory 12.

FIG. 7 is a block diagram illustrating an example of the data estimation circuit 14. As shown in the drawing, the data estimating circuit 14 includes four cascaded delay elements 41, 42, 43, and 44 driven by a clock having a bit period T in PR (1, 1, 1, 1). An adder 45 that adds the delay signals from the delay elements 41 to 44 into one combined signal, and an estimated data converter that receives the combined signal from the adder 45 as an input and outputs estimated data Y _(ki) 46.

The operation of the data estimating circuit 14 will be described. The decoded data sequence output as a bit string (binary string) is sequentially delayed by the bit period T by the delay elements 41 to 44 and each of the delay elements 41 to 44 The output delay signal is added and synthesized by the adder 45 to be a synthesized signal, and then supplied to the estimated data converter 46. The estimated data converter 46 converts the output value of the adder 45 and outputs one of the target values TU, MU, ZE, ML, TL in FIG. 5 as the estimated data Y _(ki) .

The data conversion by the estimated data converter 46 is performed according to the following rules. That is, when all the output signals of the delay elements 41 to 44 are “0” (0000), the value of the output combined signal of the adder 45 is “0”, and at this time, the estimated data converter 46 TL is output as estimated data Y _(ki) . When the output signal of the delay element 41 or 44 is “1” and the remaining three output signals are “0” (1000 or 0001) among the output signals of the delay elements 41 to 44, the addition is performed. The value of the output combined signal of the unit 45 is “1”, and at this time, the estimated data converter 46 outputs the target value ML as the estimated data Y _(ki) .

Further, among the output signals of the delay elements 41 to 44, the output signals of the delay elements 41 and 42 or the output signals of the delay elements 43 and 44 are “1”, and the remaining two output signals are “0”. At this time (1100 or 0011), the value of the output combined signal of the adder 45 is “2”, and at this time, the estimated data converter 46 outputs the target value ZE as the estimated data Y _(ki) . Further, when the output signal of the delay element 41 or 44 among the output signals of the delay elements 41 to 44 is “0” and the remaining three output signals are “1” (1110 or 0111), the addition is performed. The value of the output synthesized signal of the delay unit 45 is “3”. At this time, the estimated data converter 46 outputs the target value MU as the estimated data Y _(ki) , and all the output signals of the delay elements 41 to 44 are “1”. (1111), the value of the output combined signal of the adder 45 is "4", and at this time, the estimated data converter 46 outputs the target value TU as the estimated data Y _(ki) . The above is summarized in Table 1.

That is, when four 0s continue as a decoded data sequence, the data estimating circuit 14 estimates that the data before the time point i before the time point k is the target value TL (corresponding to the conventional target value-2), Similarly, when 1 is one such as 0001 and 1000, the target value ML (corresponding to the conventional target value -1), and when two 1s continue as in 1100 and 0011, the target value ZE (the conventional target value ZE) (Corresponding to a value of 0) and output as estimated data Y _(ki) . Since the output of the Viterbi decoder has a low bit error, the estimation data can be obtained very accurately.

The estimated data Y _(ki) output from the data estimating circuit 14 is supplied to a target value calculating circuit 15 as shown in FIG. Further, the target value calculation circuit 15 receives the input data y _(k) to the branch metric calculation circuit 11 from the data estimation circuit 14 by the delay circuit 13 determined by the length of the path memory 12. Delayed input data y _(ki) delayed until the same time as data Y _{(i-1 )} is input.

The target value calculation circuit 15 updates the target value based on the input data Y _(ki) and y _(ki) and outputs the result to the branch metric calculation circuit 11. FIG. 8 is a circuit diagram of an example of the target value calculation circuit 15. As shown in the figure, a target value calculation circuit 15 includes a subtracter 51 for performing an error calculation, a multiplier 52 for multiplying by a correction coefficient, and selectors 53 and 54 for selecting and operating based on the estimated data Y _(ki) . an adder 55 _to 554 _5, a delay element 56 ₁ to 56 ₅ which constitute the adder 55 _to 554 ₅ and mutually independent feedback loop.

To explain the operation of the target value calculation circuit 15, the delay input data y _(ki) extracted from the delay circuit 13 is supplied to the subtractor 51, where it is selected by the selector 54 by the estimated data Y _(ki) . is subtracted with delay elements 56 ₁ to 56 any one of the delayed output signals of the _five, thereby being made a target value an error signal is multiplied by the correction coefficient G in multiplier 52, supplied to the selector 53 It is, among the adders 551 _to 554 ₅ in accordance with the estimated data Y _(ki), are selected input to any one of the adders.

For example, if the target value TL is estimated as the estimated data Y _(ki), since selecting a target value TL of 1 bit period T before the selector 54 is taken out from the delay element 56 _{5 (k-1),} subtraction The target value error signal represented by [y _(ki) -TL _(k-1) ] is taken out from the multiplier 51, multiplied by the correction coefficient G in the multiplier 52, and [G (y _(ki) -TL ₍ after being a signal represented by _k-1))], and the selected input to the adder 55 ₅ by selector 53, is added to the retrieved from the delay element 56 ₅ target value TL _(k-1) . Accordingly, the following equation TL from the adder _{55 5 (k) = TL (} k-1) + G (y (ki) -TL (k-1))
The corrected target value TL _(k) represented by the following expression is extracted and output to the branch metric calculation circuit 11.

The same applies to the case where other target value as the estimated data Y _(ki) is estimated, along with when the target value TU is estimated selector 53 outputs the input signal to the adder 55 _1, the selector 54 selects the output signal of the delay element 56 _1, along with when the target value MU is estimated selector 53 outputs the input signal to the adder 55 _2, the selector 54 selects the output signal of the delay element 56 ₂ , along with when the target value ZE is estimated selector 53 outputs the input signal to the adder 55 _3, the selector 54 selects the output signal of the delay element 56 _3, when the target value ML is estimated selector 53 outputs the input signal to the adder 55 _4, the selector 54 selects the output signal of the delay element 56 _4.

Incidentally, the target value calculation circuit 15, an initial target value is input, it is held in the delay element 56 ₁ to 56 _5, calculation start time and a large during non-convergence of the error operation caused by such no-signal state, initial In order to use the target value, for example, an initial target value selection signal is input from a system controller (not shown), a no-signal detection circuit, or the like, and the initial target value is used as the target value.

  The five updated target values thus extracted from the target value calculation circuit 15 and supplied to the branch metric calculation circuit 11 are the data input to the Viterbi decoder and have the highest appearance frequency (in the histogram). Since the average value is close to five average values (having a peak), good Viterbi decoding can be performed. That is, according to the present embodiment, the effect of improving the decoding performance can be expected with respect to a certain degree of non-linear distortion by correcting the target value.

  Next, another embodiment of the present invention will be described. In the above embodiment, an improvement effect of decoding performance can be expected for a certain degree of non-linear distortion, but for a waveform that is greatly distorted, asymmetry occurs in branch metric error calculation where distortion is large, and correction is performed. In some cases, it cannot be done. Therefore, in this embodiment, the circuit of the target value calculation circuit 15 in FIG. 1 is configured as shown in the block diagram of FIG. 9 so that the target value is symmetrical and the branch metric calculation circuit 11 Are configured to perform target value control so as to operate normally.

  In FIG. 9, five updated target values extracted from the target value calculation circuit 15 are supplied to a target value correction circuit 61 and corrected, while being directly supplied to a selector 62. The selector 62 selects the correction target value from the target value correction circuit 61 or the target value from the target value calculation circuit 15 according to the selection signal from the comparator 63. The output target value of the selector 62 is output to the branch metric operation circuit 11 shown in FIGS.

The target value correction circuit 61 sets the target values TU, MU, ZE, ML, and TL from the target value calculation circuit 15 such that the respective target values are symmetric with respect to the center target value ZE, as shown in FIG. A circuit for generating corrected target values TU ', MU', ZE ', ML', TL 'corresponding to each of these five target values, and specifically, five updated target values TU, MU, ZE, By using ML and TL, for example, modified target values TU ', MU', ZE ', ML', and TL 'are generated and output by the following equation.
TU ′ = − TL ′ = (TU−TL) / 2
ML ′ = − ML ′ = (MU−ML) / 2
ZE '= ZE

  That is, the corrected target values TU 'and TL' are the average of the target values TU and TL, and the corrected target values MU 'and ML' are the average of the target values MU and ML. Note that the target value correction circuit 61 can also generate the target correction value based on a more complicated mathematical expression.

The comparator 63 compares the target value error extracted from the subtractor 51 shown in FIG. 8 in the target value calculation circuit 15 with a threshold value set in advance from the outside. If the target value error is equal to or smaller than the threshold value, The selector 62 selects the target value from the target value calculation circuit 15 and selects the correction target value from the target value correction circuit 61 when the target value error exceeds the threshold value. Since the target value error corresponds to the waveform distortion of the input data y _(k) of the Viterbi decoder, if the waveform distortion is large enough to exceed a certain set value, the target value supplied to the branch metric calculation circuit 11 is By changing the correction value to the correction target value from the target value correction circuit 61, the target value is made symmetrical, and the branch metric calculation circuit 11 operates normally for a large distortion.

  The present invention is not limited to the above embodiments. For example, the target value error may be a value multiplied by a coefficient, or a signal after performing an integration process or the like. is there. Further, as the target value selected by the selector 62, an initial target value can be used.

FIG. 3 is a block diagram of a Viterbi decoder related to the present invention. It is explanatory drawing of PR (1,1,1,1). It is a state transition diagram of PR (1,1,1,1). FIG. 4 is a decoding trellis diagram corresponding to FIG. 3. FIG. 2 is a circuit diagram of an example of a branch metric calculation circuit in FIG. 1. FIG. 2 is a block diagram illustrating an example of a path memory in FIG. 1. FIG. 2 is a block diagram illustrating an example of a data estimation circuit in FIG. 1. FIG. 2 is a circuit diagram of an example of a target value calculation circuit in FIG. 1. FIG. 14 is a block diagram illustrating another example of a Viterbi decoder related to the present invention. It is a histogram of a symmetrical reproduction wave. It is a histogram of an asymmetric reproduction wave.

Explanation of reference numerals

Reference Signs List 10 input data input terminal 11 branch metric calculation circuit 12 path memory 13 delay circuit 14 data estimation circuit 15 target value calculation circuit 16 decoded data series output terminal 31 _{1 to} 31 _n , 32 _{1 to} 32 _n , 53, 54, 62 selector 41 to 44, 56 _{1 to} 56 ₅ Delay element 45, 55 _{1 to} 55 ₅ Adder 46 Estimated data converter 51 Subtractor 52 Multiplier 61 Target value correction circuit 63 Comparator

Claims (1)

A first step of performing a branch metric operation on the input data using a plurality of target values to generate a selection signal;
A second step of outputting a decoded data sequence obtained by Viterbi decoding input data based on the selection signal;
A third step of delaying the input data by a predetermined bit period;
A fourth step of correcting a target value using a difference between a target value based on the decoded data and the input data delayed in the third step as a target value error, and using the obtained plurality of corrected target values as a plurality of target values; And a viterbi decoding method.

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