JPH11203795A - Decoding device for optical disk - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoding device of an optical disk which is capable of executing a decoding process which is excellent in a noise-resisting characteristic and which enables proper decoding even with respect to a signal in which the signal-to-noise ratio of a reproduced RF signal waveform is low without using a circuit whose constitution is complex of without executing a complex arithmetic processing. SOLUTION: When the reproducing of a bit synchronizing clock is performed by a PLL by binarizing the reproduced waveform of an optical disk, a reference level for the binarization is adjusted with a level adjusting means 16 and, on the other hand, the reproduced waveform which is not yet binarized by using the bit synchronizing clock is discreted in an A/D converting means 18 and, moreover, the discreted output signal is decoded into a bit string by a viterbi detecting means 22 while using a viterbi algorithm and, moreover, at the time of performing a decoding in which a coding rule whose run length is limited is utilized, a prediction value control means 21 calculatingly outputting quinary prediction values to be used in a metric operation based on an error signal with which the level adjusting means performs a level adjustment or on the value discreted in the A/D converting means is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus for an optical disk used in a reproducing apparatus for reproducing digital data recorded on an optical disk such as a DVD (digital versatile disk) and a CD (compact disk).

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing the structure of a conventional optical disk decoding apparatus of this kind. In the figure, a reproduction R corresponding to information recorded on a track on a disc
An F (Radio Frequency) signal is applied to the variable gain amplifier 11. The variable gain amplifier 11 keeps the amplitude constant by the gain control signal and outputs the same. The output is applied to the waveform equalization circuit 12. The waveform equalization circuit 12 removes waveform distortion caused by a shortage of a band, that is, corrects an input signal waveform to reduce waveform interference and increase the density. The level detection control circuit 13 compares the output level of the waveform equalization circuit 12 with a predetermined target value, and outputs a gain control signal for matching the output level to the target value to control the gain of the variable gain amplifier 11.

The output of the waveform equalizer 12 is applied as one input to an adder 14, and the output of the adder 14 is binarized by a binarizer 15 and output as a reproduced code sequence. In this case, a shift occurs in the center level for performing the level comparison depending on the molding state of the optical disk. Therefore, the auto slicer 16 as the level adjusting means adjusts the center level, that is, the slice level, using the binarized signal. A DC voltage is applied as the other input of the adder 14. Also, based on the binarized reproduction code sequence, a PLL
(Phase Locked Loop) 17 generates and outputs a synchronization signal generated every basic period of the recording code, that is, a bit synchronization clock.

[0004]

In the conventional optical disk decoding apparatus shown in FIG. 9, the binarizing circuit 15 uses the center point of the envelope of the reproduced RF signal output from the optical pickup as a reference level. Since a high-density disc such as a DVD cannot output a sufficient signal-to-noise (S / N) ratio because of converting the value into a value and outputting it, it is difficult to obtain highly reliable digital data. Was. In order to solve this problem, a decoder that attempts to increase the apparent signal-to-noise ratio by Viterbi decoding processing,
The document "PIONEER R &D" (Vol.6 No.2) contains "D
Development of Viterbi decoding circuit for VD reproduction ". FIG. 10 is a block diagram showing the configuration of another conventional optical disk decoding apparatus using Viterbi decoding. In the figure, the same elements as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. Here, an A / D converter 18 including a limiter and a Viterbi detection circuit 19 are newly added to the components in FIG.

In FIG. 10, an A / D converter 18 has a P
The output signal of the waveform equalization circuit 12 is discretized using the bit synchronization clock of the LL 17 as a sampling pulse, and at the same time, the peak value is limited so that the value discretized by the limiter becomes three values. The Viterbi detection circuit 19 performs a metric operation using three values of high “H”, zero “0”, and low “L” as predicted values, performs a Viterbi decoding process, and outputs a reproduced code sequence.

Meanwhile, in the conventional optical disk decoding apparatus shown in FIG. 10, the peak value is limited by a limiter so that the metric operation is performed in three values. Energy, that is, the inter-symbol distance cannot be used sufficiently, so that there is a problem that the signal-to-noise ratio due to the Viterbi decoding process cannot be sufficiently improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a decoding process having excellent noise immunity without using a circuit having a complicated configuration or executing a complicated operation process. It is an object of the present invention to provide an optical disc decoding apparatus capable of executing the above-mentioned method and performing suitable decoding even for a signal having a low signal-to-noise ratio of a reproduced RF signal waveform.

[0008]

A conventional optical disk decoding apparatus that outputs a reproduced code sequence by performing a Viterbi decoding process has an improved signal-to-noise ratio because three prediction values are used for a metric operation. Is insufficient, and improvement in decoding performance can be expected by using a larger number of predicted values. The present invention is intended to estimate a large number of predicted values from an actual reproduced signal and to improve decoding performance by using these predicted values.

That is, according to the present invention, an automatic gain control means for always keeping the envelope level of a reproduced waveform of an optical disk constant, a waveform equalizing means for removing a reproduced waveform distortion outputted from the automatic gain control means, Binarizing means for binarizing the output of the automatic gain control means from which the waveform distortion has been removed, level adjusting means for adjusting the reference level of the input of the binarizing means, and bits based on the output of the binarizing means A PLL for reproducing a synchronous clock, an A / D converter for discretizing an output signal of the waveform equalizing means by a predetermined number of bits using a bit synchronous clock generated by the PLL, and outputting the signal. A Viterbi detection unit that decodes an output signal of the / D conversion unit into a bit string using a Viterbi algorithm, and performs decoding using a coding rule with a limited run length; And a predicted value controller adjusting means for calculating outputting a predicted value of at least 5 values used in metric calculation based on the error signal for level adjustment, decoding device of an optical disk having is provided.

According to the present invention, there is provided an automatic gain control means for always keeping the envelope level of a reproduction waveform of an optical disk constant, a waveform equalization means for removing a reproduction waveform distortion outputted from the automatic gain control means, Binarizing means for binarizing the output of the automatic gain control means from which waveform distortion has been removed, a PLL for reproducing a bit synchronous clock based on the output of the binarizing means, and a bit synchronous clock generated by the PLL A / D conversion means for digitizing and outputting the output signal of the waveform equalization means with a predetermined number of bits, and decoding the discretized output signal of the A / D conversion means into a bit string using a Viterbi algorithm A Viterbi detecting means for performing decoding using an encoding rule with a limited run length, and a metric calculation based on a value discretized by the A / D converting means. And a predictive value control means for calculating outputting a predicted value of at least 5 values, the decoding apparatus of an optical disc having is provided.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on preferred embodiments. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, the same elements as those of FIG. Here, based on the center value error signal of the auto slicer 16, a prediction value control circuit 21 for generating five prediction values with respect to the level that the sample value can take in a noise-free ideal case is newly added, The Viterbi detection circuit 22 is configured to determine a data sequence having the maximum existence probability in accordance with a predetermined Viterbi decoding algorithm and output the data sequence as a reproduced code sequence.

The operation of the present embodiment configured as described above will be described below. The eye pattern for the output of the waveform equalization circuit 12 is as shown in FIG. When A / D conversion is performed using the arrows ↑ in FIG. 2 as sampling points, one signal can be represented by five values.
The predicted value control circuit 21 shown in FIG. 1 generates five predicted values and adds them to the Viterbi detection circuit 22. Hereinafter, a method of generating these predicted values will be described.

An automatic gain control circuit (Automatic Ga) comprising a variable gain amplifier 11 and a level detection control circuit 13
In Control: AGC), the peak value of the reproduced RF signal is kept almost constant. Therefore, when the reference level in the binarization circuit 15, that is, the magnitude of the error signal of the slice level is zero, as shown in FIG.
The metric calculation may be performed using U, 0, -ML, and -L as predicted values. The state transition diagram at this time is as shown in FIG. FIG. 4B shows input symbols corresponding to each state in this state transition diagram. FIG. 5 shows a trellis diagram of the Viterbi detection circuit 22. The Viterbi detection circuit 22 has a configuration shown in this trellis diagram. According to this configuration,
Run Length like DVD or CD
Codes shorter than a predetermined run length can be removed from codes for which h) is restricted.

On the other hand, when the reference level in the binarization circuit 15 is shifted from zero, that is, when the binarization circuit 15
, The center value error signal output from the auto slicer 16 is not zero, and the levels U, MU, 0,
If a metric calculation is performed using −ML and −L as predicted values,
The decoding result output as the reproduced code sequence is degraded. Now, assuming that the magnitude of the center value error signal output from the auto slicer 16 is "-a" as shown in FIG. 3, "-a" may be subtracted from each predicted value used for the metric calculation. . That is, levels U + a, MU + a,
The metric calculation may be performed using a, -ML + a, and -L + a. Strictly speaking, the correction value is a central value error, for example, "-
a ", but the performance is hardly degraded by not using the function. The predicted value control circuit 21 uses the central value error signal of the binarization circuit 15 to calculate the predicted value M when there is no error. , MU, 0, -ML, and -L.

The calculation of the predicted value in the above-described embodiment can be executed at an appropriate time, such as at the time of calibration after disk replacement or after data seek. Further, the Viterbi detection circuit 22 has six states, and the configuration is almost the same as that of the conventional decoder, so that the configuration does not become complicated.

FIG. 6 shows, as a characteristic line A, the relationship between the S / N ratio and the error rate of the conventional device that has performed the Viterbi decoding processing based on three prediction values, and shows the Viterbi decoding based on the five prediction values. The relationship between the S / N ratio and the error rate of the first embodiment in which the processing is performed is shown as a characteristic line B. As is clear from this figure, according to the first embodiment, it is possible to sufficiently improve the signal-to-noise ratio by performing the Viterbi decoding process.

Thus, according to the first embodiment, it is possible to execute a decoding process excellent in noise immunity without using a circuit having a complicated configuration or executing a complicated operation process. Also, it is possible to perform suitable decoding even for a signal having a low signal-to-noise ratio of the reproduced RF signal waveform.

In the first embodiment, the predicted value control circuit 21 predicts a value based on a central value error, for example, "-a" when the auto slicer 16 corrects the reference level of the binarization circuit 15. Five predictions were computed for the eye pattern, but instead of A / D with limiters
5 based on the output of converter 18
Can be calculated. That is, A / D
When the frequency of occurrence of the discretized data output from the converter 18 is counted for each level divided into a predetermined number, a histogram as shown in FIG. 7 is obtained. An appropriate slice point R is found in this histogram, and this slice point R
The average level of the five points exceeding? Can be obtained, and the reference point can be obtained from the average level to obtain a total of five predicted values.

FIG. 8 is a block diagram showing the configuration of the second embodiment of the present invention according to this concept. In the figure, the same elements as those in FIG. I do. This is because the predicted value control circuit 21 shown in FIG. 1 executes a correction operation on five predicted values based on the center value error signal of the auto slicer 16, whereas the predicted value control circuit 21 shown in FIG. Reference numeral 23 differs from FIG. 1 only in that five prediction values are obtained based on the output of the A / D converter 18.

Here, the predicted value control circuit 23 first counts the frequency of occurrence of the discrete data, which is the output of the predicted value control circuit 23, for each level divided into a predetermined number. Then, a histogram as shown in FIG. 7 is obtained. And
The prediction value control circuit 23 finds an appropriate slice point R in the histogram, and calculates an average value of five points beyond this.
Next, a total of five predicted values are calculated, two each at the top and bottom, using the average value as a reference point. The predicted value control circuit 23 can be easily realized by a microcomputer such as a system controller. In this case, the trellis for decoding by the Viterbi detection circuit 22 is configured in the same manner as shown in the diagram of FIG.

The calculation of the predicted value in the above-described embodiment can be executed at an appropriate time, such as at the time of calibration after disc replacement or after data seek. Further, the Viterbi detection circuit 22 has six states, and the configuration is almost the same as that of the conventional decoder, so that the configuration does not become complicated. Thus, according to the second embodiment, the signal-to-noise ratio can be sufficiently improved by performing the Viterbi decoding process. In the above description, the prediction value is set to five values. However, the present invention is not limited to this, and it goes without saying that seven values, nine values, and the like can be used as the prediction values.

[0022]

As is apparent from the above description, according to the present invention, a decoding process having excellent noise immunity can be achieved without using a circuit having a complicated configuration or executing a complicated operation process. And a decoding device for an optical disk that can perform suitable decoding even for a signal having a low signal-to-noise ratio of a reproduced RF signal waveform can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an eye pattern after waveform equalization and a sampling point for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 3 is an explanatory diagram for obtaining a predicted value used for a metric calculation in order to explain an operation of the first embodiment shown in FIG. 1;

FIG. 4 is a state transition diagram of a Viterbi detection circuit for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 5 is a diagram showing a trellis diagram of a Viterbi detection circuit for explaining the operation of the first embodiment shown in FIG. 1;

FIG. 6 is a diagram showing a relationship between an S / N ratio and an error rate together with that of a conventional device in order to explain the operation of the first embodiment shown in FIG. 1;

FIG. 7 is a histogram of a sample level and the number of samples for explaining the principle of the second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional optical disk decoding device.

FIG. 10 is a block diagram showing a configuration of another conventional optical disk decoding device.

[Explanation of symbols]

 Reference Signs List 11 variable gain amplifier (automatic gain control means) 12 waveform equalization circuit (waveform equalization means) 13 level detection control circuit 14 adder 15 binarization circuit (binarization means) 16 auto slicer (level adjustment means) 17 PLL 18 A / D converter (A / D conversion means) 19 Viterbi detection circuit 21, 23 Predicted value control circuit (predicted value control means) 22 Viterbi detection circuit (Viterbi detection means)

Claims (2)

[Claims] 1. An automatic gain control means for constantly keeping an envelope level of a reproduction waveform of an optical disc constant, a waveform equalization means for removing a reproduction waveform distortion outputted from the automatic gain control means, and a reproduction waveform distortion removal. Binarizing means for binarizing the output of the automatic gain control means, a level adjusting means for adjusting a reference level of an input of the binarizing means, and bit synchronization based on an output of the binarizing means. A PLL that reproduces a clock; an A / D converter that discretizes an output signal of the waveform equalizer by a predetermined number of bits using a bit synchronization clock generated by the PLL; Viterbi detection means for decoding the output signal of the A / D conversion means into a bit string using a Viterbi algorithm and performing decoding using a coding rule with a limited run length; A predictive value control unit for calculating and outputting at least five predicted values used for metric calculation based on an error signal for performing the level adjustment by the level adjusting unit. 2. An automatic gain control means for constantly keeping an envelope level of a reproduction waveform of an optical disc constant, a waveform equalization means for removing a reproduction waveform distortion outputted from the automatic gain control means, and a reproduction waveform distortion removal. Binarization means for binarizing the output of the automatic gain control means, a PLL for reproducing a bit synchronization clock based on the output of the binarization means, and a bit synchronization clock generated by the PLL. A / D conversion means for discretizing the output signal of the waveform equalization means by a predetermined number of bits and outputting the same, and decoding the discretized output signal of the A / D conversion means into a bit string using a Viterbi algorithm And a Viterbi detecting means for performing decoding using a coding rule with a restricted run length; and a metric calculation based on a value discretized by the A / D converting means. And a predicted value control means for calculating and outputting at least five predicted values to be used.