JP2008276931A - Reproducing device, and recording and reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that high-density recording leads to a significant reduction in a level of a read-out signal having a small run-length, so that characteristics of a reproduced signal are deviated from characteristics of PR(a, b, b, a), and therefore, an error rate cannot be sufficiently suppressed. <P>SOLUTION: A temporary determination device 51 receives a waveform equalization reproducing signal from a transversal filter, output data D2 and Z2 of tap delay circuit parts 23a and 23b, respectively, a PR mode signal, and an RLL mode signal. On the basis of the input signals, the temporary determination device 51 performs a temporary determination operation which deftly uses the nature of partial response characteristics. A subtractor 52 subtracts a determination result obtained by the temporary determination device 51 from the tap delay output signal D3 of a current time to calculate an error signal, and then latches the error signal using a D flip-flop 53, and thereafter, outputs a tap coefficient to a transversal filter to make the error signal zero. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a playback device and a recording / playback device, and more particularly to a playback device including Viterbi decoding and run-length decoding means for a run-length limited code that is played back from a recording medium such as an optical disk, and a run-length to a recording medium such as an optical disk. The present invention relates to a recording / reproducing apparatus that records and reproduces a restriction code.

  In a playback apparatus that plays back a run-length limit code from a recording medium such as an optical disc on which the run-length limit code is recorded at a high density, partial response (hereinafter also referred to as PR) equalization is performed to remove waveform distortion of the playback signal. A device using a waveform equalization circuit having characteristics is conventionally known (see, for example, Patent Document 1). FIG. 35 shows a block diagram of an example of this conventional reproducing apparatus. In the figure, the run length limit code reproduced from the optical disc 1 by the recording / reproducing system 2 is supplied to the transversal filter 3, where the tap coefficient input from the tap coefficient determiner 6 in the parameter setter 5 is converted to the tap coefficient. Based on this, PR equalization is performed.

  The X value selector 10 selects an X value that is an intersymbol interference value in, for example, PR (1, X, X, 1) equalization in the transversal filter 3 based on the characteristics of the reproduced waveform. Xi is sequentially obtained from the determination result of the rate determiner 9, and finally the value of X that satisfies the allowable error rate is selected. The equalization target waveform generator 8 is based on the binary data given from the parameter setting binary data memory 7 and the X value of the intersymbol interference giving value in PR equalization selected by the X value selector 10. A target waveform after equalization is created and given to the tap coefficient determiner 6.

  Bits corresponding to the parameter setting binary data memory 7 are recorded in advance on the optical disc 1. The tap coefficient determiner 6 obtains a tap coefficient such that the reproduced waveform matches the equalized target waveform from the reproduced waveform corresponding to this bit and the equalized target waveform, and inputs it to the transversal filter 3. The discrimination point signal level determiner 11 obtains the discrimination point signal level based on the X value given from the X value selector 10 and supplies this to the ML decoder 4. The ML decoder 4 decodes the equalized reproduction waveform extracted from the transversal filter 3 into binary data with reference to the discrimination point signal level and outputs the binary data.

  The decoded data extracted from the ML decoder 4 is supplied to an error rate determination unit 9, where it is compared with the parameter setting binary data from the parameter setting binary data memory 7 to obtain an error rate. A determination result as to whether or not the error rate satisfies an allowable value is supplied to the X value selector 10. When the error rate determination unit 9 determines that the error rate satisfies an allowable value, the PR (1, X, X, 1) ML method using the tap coefficient and the discrimination point signal level at that time, PR, etc. And maximum likelihood decoding are performed.

  Conventionally, an optical disc signal reproduction method for performing maximum likelihood detection with a code inversion interval as a constraint condition after equalizing a reproduction signal by a run length limited code whose minimum code inversion interval is limited to a constant of 2 or more. Thus, a ternary equalization apparatus for only the amplitude excluding the point corresponding to the data string having the minimum code inversion interval among the points immediately before or after the code inversion position and only the amplitude of the code inversion position. Is also known (see, for example, Patent Document 2).

  However, of the above-described conventional reproducing apparatuses, the reproducing apparatus described in Patent Document 1 is based on the premise that bits corresponding to the parameter setting binary data memory 7 are recorded on the optical disk 1 in advance. If it is unknown whether the recording signal of the optical disk 1 corresponds to the binary data stored in the parameter setting binary data memory 7, the waveform equalization cannot be adaptively performed.

  Therefore, the known pattern data corresponding to the recorded binary data in the parameter setting binary data memory 7 is reproduced, and the tap coefficient of the transversal filter 3 is determined so that the waveform is normally equalized. There must be. For this reason, when a reproduction signal is input with a reproduction characteristic different from that when the tap coefficient is determined, it cannot be handled.

  Among the conventional playback devices described above, in the playback device described in Patent Document 2, since PR equalization performed by the playback device has multiple target values, a fine threshold comparison is required in the error rate determination unit, and noise There is a problem that the judgment becomes difficult due to the distortion. Therefore, in devices to which a plurality of types of signals are input (for example, playback devices such as CDs and DVDs), run lengths and PR characteristics to be equalized differ depending on the characteristics of the signals to be played back, so control for adjusting the threshold is complicated. Thus, there is a possibility that it takes a long time for the waveform equalization to be performed stably.

  In view of such a point, the present inventor aims to perform waveform equalization by higher quality PR equalization without the influence of noise and distortion, and can perform reproduction that can expand the convergence range and shorten the convergence time. An apparatus has been proposed (see, for example, Patent Document 3). Specifically, the reproducing apparatus proposed by the present inventor reproduces a run length limited code recorded on a recording medium, decodes the reproduced signal after performing partial response equalization using a transversal filter. In the reproducing apparatus, detection means for detecting whether or not the reproduction signal inputted to the transversal filter is a zero cross point and outputting 0 point information, and at least continuous 0 point information taken out in synchronization with the clock by the detecting means. Three output delay circuits, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run-length limit code of the reproduction signal, a plurality of 0-point information from the delay circuit, a transformer Receives the waveform equalized reproduction signal output from the Versal filter as input, and receives the PR mode signal. And a temporary discrimination value of the waveform equalization signal is calculated based on the state transition determined by the RLL mode signal and a plurality of 0 point information patterns, and the difference value between the temporary discrimination value and the waveform equalized reproduction signal is an error. The provisional discriminating circuit outputs as a signal, and the coefficient generating means for variably controlling the tap coefficient of the transversal filter based on the output error signal of the temporary discriminating circuit so that the error signal is minimized.

  Further, the reproducing apparatus proposed by the present inventor includes zero detecting means for outputting 0 point information indicating whether or not a zero cross point is obtained from a waveform equalized reproduced signal output from a transversal filter, and a detecting means. A delay circuit that outputs at least three consecutive 0-point information extracted in synchronization with the clock, a PR mode signal indicating the type of partial response equalization, and an RLL mode signal indicating the type of run-length limit code of the reproduction signal And a plurality of 0 point information from the delay circuit and a waveform-equalized reproduction signal output from the transversal filter as inputs, a state transition determined by the PR mode signal and the RLL mode signal, and a plurality of 0 point information Based on the pattern, a temporary discrimination value of the waveform equalization signal is calculated, and the temporary discrimination value and the waveform equalized reproduction signal are calculated. With the tentative determination circuit the difference value is output as an error signal, based on the output error signal of the provisional determination circuit, and a coefficient generating means for variably controlling so that the error signal the tap coefficients of the transversal filter is minimized.

  In this reproducing apparatus, a temporary discriminating value of a waveform equalization signal is calculated based on a state transition determined by the PR mode signal and the RLL mode signal by a temporary discriminating circuit and a plurality of 0 point information patterns, Since the difference value from the reproduced signal after waveform equalization is output as an error signal, an error signal that is an error from the convergence target value is generated and output without depending on the level of the current sampling point. By variably controlling the tap coefficient of the transversal filter based on the error signal, the partial response waveform equalization characteristic by the transversal filter can be controlled to be the error signal 0.

  In addition, the playback device proposed by the present inventor plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter. , The error signal output from the temporary determination circuit is input to the first input terminal, the temporary determination value output from the temporary determination circuit is input to the second input terminal, and an error signal is output according to the temporary determination value. Is further provided with an error selection circuit for selecting and outputting only effective components, and based on the signal output from the error selection circuit, the error signal is minimized by the coefficient generation means by the coefficient generation means. It is configured to be variably controlled.

  In this reproducing apparatus, the error selection circuit invalidates a signal indicating an uncertain error value among the error signals output from the provisional determination circuit, and can extract only a probable error signal as an effective component.

JP-A-10-106161 JP-A-7-192270 Japanese Patent No. 3395734

  However, as the density of the optical disk increases, the read level of a signal having a small run length (for example, 2T (T is a bit period)) is significantly reduced, and the reproduction signal has a characteristic of PR (a, b, b, a ), The reproduction apparatus proposed by the present inventor described in Patent Document 3 will amplify noise when trying to force PR (a, b, b, a). As a result, sufficient error rate suppression cannot be performed. In order to solve this problem, it may be equalized to PR (a, b, b, b, a) having a larger constraint length, but in that case, a process with more complicated state transition is required.

  In the playback device proposed by the present inventor, the polarity of the waveform equalized signal corresponding to the provisional discrimination detection target is used for polarity determination, but the level is low like a signal having a small run length. With a small signal, the polarity determination error becomes large.

  In addition, if the read level of a signal with a small run length (for example, 2T) is significantly reduced due to an increase in the density of the optical disc, a reliable clock cannot be reproduced. At this time, as a phenomenon, a bit slip occurs, the original bit may disappear in the time direction, or the correct number of bits until the phase lock loop circuit (PLL circuit) locks again may be lost. There is sex.

In the subsequent stage of the playback device, a reliable bit string can be estimated by using decoding having error correction capability such as Viterbi decoding, but the number of lost bits cannot be restored. In other words, the bit position shifts and the error increases even though it forms a part of the correct data string (if a bit shift occurs, the error rate deteriorates to 5 × 10 ⁻¹ during that period. To do.)

  When the sync signal is inserted in the playback signal, it can return to the correct position when the sync signal is played back, but a bit slip occurs between the sync signal and the sync signal, for example, immediately after the sync signal. In that case, the block is in error. Even in coding / decoding means for performing decoding corresponding to a coding modulation method for performing block coding (1-7pp modulation, 8-16 modulation, D4-6 modulation for performing run length limitation and DSV control), bit shift is not detected. If it occurs, it is impossible to decode it to the correct code.

  The present invention has been made in view of the above points, and even for characteristics that are difficult to make a temporary determination such as PR (a, b, b, b, a) having a target value of 9 or more. It is an object of the present invention to provide a reproducing apparatus that can perform waveform equalization by higher quality PR equalization without the influence of noise and distortion.

  Another object of the present invention is to provide a reproducing apparatus capable of realizing the expansion of the convergence range and the shortening of the convergence time as in PR (a, b, b, b, a).

  Another object of the present invention is to use the error signal of the synchronization signal to adjust the data length so that the correct data length and bit position are obtained even if a bit slip occurs between the synchronization signals. An object of the present invention is to provide a reproducing apparatus and a recording / reproducing apparatus capable of greatly improving the error rate by adjusting (interpolating / decimating).

  In order to achieve the above object, a first invention is a reproduction apparatus for reproducing a run-length limited code recorded on a recording medium, decoding the reproduced signal after performing partial response equalization using a transversal filter. , Zero detecting means for detecting a zero cross point from the waveform equalized reproduction signal output from the transversal filter and outputting zero point information; and the zero point information extracted from the zero detecting means in synchronization with a system clock. The first delay circuit that sequentially delays one clock at a time and outputs at least four continuous 0-point information and the waveform equalized reproduction signal output from the transversal filter are synchronized with the system clock. Sample one clock at a time, and at least reconstruct the signal after waveform equalization. A second delay circuit that outputs the values of the four sampling points, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run-length limit code of the reproduction signal, and the first Receiving a plurality of the 0 point information from one delay circuit and the values of the plurality of sampling points from the second delay circuit as input, and a state transition determined by the PR mode signal and the RLL mode signal; When calculating a temporary discriminant value of the reproduced signal after waveform equalization based on a plurality of 0 point information patterns and the polarity of the value of the target sampling point among the plurality of sampling points, the at least four consecutive 0s are calculated. The median value in the point information does not indicate the zero cross point, and the zero point information values before and after the median indicate the zero cross point. If there is, the Euclidean distance is calculated and added to the sampling sequence of the three consecutive waveform-equalized reproduction signals that differ by 1-bit clock period, corresponding to the reference value sequence of three consecutive state transitions. Comparing the sum of the first Euclidean distances with the second sum of the Euclidean distances calculated and added in correspondence with the reference value series of three consecutive state transitions having the same reverse polarity, The largest reference value in the reference value series used to calculate the sum of the Euclidean distances with the smaller value is calculated as the temporary determination value, and the temporary determination value and the second delay circuit output Temporary discrimination means for outputting a difference value from the sampling point value of interest as an error signal, and the transversal filter based on the output error signal of the temporary discrimination means Coefficient generating means for variably controlling the tap coefficient so that the error signal is minimized.

  In order to achieve the above object, the second invention reproduces the run-length limited code recorded on the recording medium, reproduces the reproduced signal after partial response equalization using a transversal filter, and decodes the reproduced signal. In the apparatus, zero detection means for detecting a zero cross point from the waveform equalized reproduction signal output from the transversal filter and outputting zero point information, and the zero detected from the zero detection means in synchronization with a system clock. The first delay circuit that sequentially delays the point information by one clock and outputs at least four consecutive zero point information, and the waveform equalized reproduction signal output from the transversal filter are used as the system clock. Synchronously, sample one clock at a time, and at least regenerate signal after waveform equalization A second delay circuit that outputs the values of four consecutive sampling points, a PR mode signal indicating the type of partial response equalization, an RLL mode signal indicating the type of run length limit code of the reproduction signal, The plurality of zero point information from the first delay circuit and the values of the plurality of sampling points from the second delay circuit are received as inputs, and the median value of the at least four consecutive zero point information If the value does not indicate a zero cross point, and the values of the zero point information both before and after the median value indicate zero cross points, or the median value in the at least four consecutive zero point information indicates the zero cross point Not shown and only the value of the 0 point information after the median indicates a zero cross point, or the at least 4 consecutive If the median value in the zero point information indicates a zero cross point, and the zero point information values other than the median value do not indicate a zero cross point, state transition determined by the PR mode signal and the RLL mode signal And based on the pattern of the plurality of 0 point information and the polarity of the value of the sampling point adjacent to the target sampling point among the plurality of sampling points, a temporary discrimination value of the reproduced signal after waveform equalization is calculated, Based on the temporary determination means for outputting the difference value between the temporary determination value and the value of the target sampling point output from the second delay circuit as an error signal, and the output error signal of the temporary determination means, Coefficient generating means for variably controlling the tap coefficient of the transversal filter so that the error signal is minimized.

  In order to achieve the above object, according to a third aspect of the present invention, in the first or second aspect of the invention, the zero detecting means reverses the polarity of the waveform equalized reproduction signal output from the transversal filter. In this case, the zero detector outputs a sample point closer to 0 out of two neighboring sample points as the 0 point information.

  In order to achieve the above object, the fourth invention provides encoding means for generating and encoding parity from input digital information, and every m bits of the encoded signal output from the encoding means. A run-length limit code generating means for generating a run-length limit code by converting it into n bits (where m <n), a recording means for recording the run-length limit code on a recording medium, and Reproduction means for reproducing a length limit code, A / D conversion means for converting the reproduced run length restriction code into a digital reproduction signal, extracting a phase error from the digital reproduction signal, and controlling a resampling frequency Phase locked loop means for generating a bit clock and resampling and outputting the digital reproduction signal, and the phase locked loop means Adaptive equalization means for performing waveform equalization processing on the digital reproduction signal using a transversal filter based on 0 point information detected as to whether or not the digital reproduction signal resampled and output is a zero cross point A decoding means for maximum likelihood decoding the reproduction signal output from the adaptive equalization means and outputting digital reproduction data together with likelihood information; and the run length limit code generation means for the digital reproduction data Run-length decoding means for converting the input n-bit likelihood information into the m-bit likelihood information, and converting the input n-bit likelihood information into the m-bit likelihood information, and the run-length decoding means The n-bit digital reproduction data and likelihood information output from the And having an error correction means for performing error correction using a tee.

  In the present invention, a run length limited code generated by converting the encoded signal into m bits for every m bits in the recording system is recorded on the recording medium, and the run length limited code reproduced from the recording medium is recorded every n bits. In addition to conversion to m bits, decoding can be performed by converting likelihood information for each input n bits into likelihood information for each m bits.

  In order to achieve the above object, the fifth invention reproduces a run-length limited code recorded on a recording medium, reproduces the reproduced signal after partial response equalization using a transversal filter, and decodes the reproduced signal. In the apparatus, A / D conversion means for converting the run-length limited code reproduced from the recording medium into a digital reproduction signal including a synchronization signal having a fixed period, and resampling calculation of the digital reproduction signal at a desired bit rate Then, the resampling data is generated and the bit clock is generated, the phase error is extracted to control the resampling frequency, and whether or not the digital reproduction signal is at the zero cross point is detected and 0 point information is output. Resampling calculation phase locked loop means and the resampling calculation phase locked loop Adaptive resequencing means for performing waveform equalization processing based on the 0-point information using a transversal filter with respect to the resampling data output from, and the reproduced signal output from the adaptive equalization means Decoding means for performing likelihood decoding and outputting digital reproduction data together with likelihood information; synchronization signal detecting means for extracting the synchronization signal from the digital reproduction data; and counting intervals between two extracted adjacent synchronization signals. A data length error determining means for outputting data length error information indicating whether or not the counted synchronization signal interval is equal to the reference data length, and the absolute value of the phase error supplied from the phase locked loop means is a predetermined value. When the threshold value is exceeded, or the maximum value of the phase error is extracted, slip point information having the position information is detected, and the When it is determined that the length is not a regular length based on the data length error information, the data length is adjusted at the position based on the slip point information with respect to the digital reproduction data and the likelihood information. Thus, the data length recovery means for recovering the data length, and the digital reproduction data output from the data length recovery means are converted to m bits (n> m) every n bits by run length limited decoding. And run length decoding means for converting likelihood information for each input n bits into likelihood information for each m bits.

  In the present invention, even if the bit slip is likely to occur between the synchronization signals, even if the absolute value of the phase error supplied from the phase locked loop means exceeds a predetermined threshold value, or the maximum phase error The value is extracted, the position information is estimated as a slip point, and when it is determined that the interval of the synchronization signal is not a regular interval, the digital reproduction data and the likelihood information are compared with the data at the position based on the slip point information. The length can be adjusted.

  In order to achieve the above object, the sixth invention reproduces a run-length limited code recorded on a recording medium, reproduces the reproduced signal after partial response equalization using a transversal filter, and decodes the reproduced signal. In the apparatus, A / D conversion means for converting the run-length limited code reproduced from the recording medium into a digital reproduction signal including a synchronization signal having a fixed period based on a predetermined clock, and a phase error from the digital reproduction signal. Extracting and controlling the resampling frequency to generate and output the predetermined clock; and a zero-crossing of the digital reproduction signal with respect to the digital reproduction signal output from the phase synchronization loop means Transversal filter based on 0 point information obtained by detecting whether or not it is a point Using adaptive equalization means for performing waveform equalization processing, maximum likelihood decoding of a reproduction signal output from the adaptive equalization means, and outputting digital reproduction data together with likelihood information; and from the digital reproduction data The synchronization signal detecting means for extracting the synchronization signal, the interval between the extracted two adjacent synchronization signals is counted, and the data length error information indicating whether or not the counted interval between the synchronization signals is equal to the reference data length A data length error determination means for outputting a slip when the absolute value of the phase error supplied from the phase-locked loop means exceeds a predetermined threshold, or the maximum value of the phase error is extracted and the position information is included When the point information is detected and it is determined that the length is not a regular length based on the data length error information, the digital reproduction data and the Data length recovery means for recovering the data length by adjusting the data length at a position based on the slip point information for the degree information, and for the digital reproduction data output from the data length recovery means Run length decoding means for converting every n bits into m bits (where n> m) by run length limited decoding, and converting likelihood information for each input n bits into likelihood information for each m bits; It is characterized by having.

  In this invention, in place of the resampling calculation phase locked loop means used in the sixth invention, a phase error is extracted from the digital reproduction signal, and a predetermined clock is generated and output by controlling the resampling frequency. By performing the same processing as in the tenth invention using the phase locked loop means, when it is determined that the interval of the synchronization signal is not a regular interval, the slip point information is converted into the digital reproduction data and the likelihood information. The data length can be adjusted at the base position.

  In order to achieve the above object, according to a seventh aspect, the adaptive equalization means according to the fifth or sixth aspect includes the first aspect according to the first aspect, in addition to the transversal filter. And a second delay circuit, the provisional discrimination means, and the coefficient generation means.

  According to the present invention, an error signal that is an error between a zero-cross sample and a convergence target value determined from a state transition is not based on the current sampling point level, but based on four or more consecutive 0-point information. The partial response equalization characteristic PR (a) specified by the PR mode signal is generated based on the provisional discriminant value generated in this way, and the tap coefficient of the transversal filter is variably controlled so that the error signal is minimized. , B, b, b, a) waveform equalization is performed, so that PR (a, b, b, b, a), which is difficult to determine temporarily, is accurate regardless of the current sampling point level. Waveform equalization can be applied to different partial response characteristics, and the convergence range can be shortened compared to the conventional waveform equalization circuit with fixed tap coefficient. Kill.

  Further, according to the present invention, when the median value in four or more consecutive 0 point information does not indicate a zero cross point, the values of 0 point information both before and after the median value indicate a zero cross point. The first is obtained by calculating and adding the Euclidean distance corresponding to the target value series of three consecutive state transitions with respect to the sampling series of three consecutive waveform equalized signals that are different by 1 bit clock period. The sum of the Euclidean distances is compared with the sum of the second Euclidean distances calculated and added in correspondence with the target value series of three consecutive state transitions having the opposite polarity, and the value is small. Since the sum of the Euclidean distances is selected as a more probable polarity, correct judgment is possible even for signals near the zero cross with a low level.

  In addition, according to the present invention, the temporary determination means is configured to output a fixed value 0 without outputting an error signal of a sample point other than the sample points near the zero cross in the error signal. In the present invention, an uncertain error signal among error signals can be invalidated, and only a probable one can be used as an effective component of the error signal. Therefore, a signal that has a large distortion and is not correctly PR-equalized. Can be converged to the correct target value, and as a result, the error rate can be improved.

  In addition, according to the present invention, it is possible to cope with any run-length limit code of the minimum inversion interval 2 and 3, and since it can be constituted by a digital circuit, it is more reliable than an analog circuit and the circuit scale is almost increased. It can be configured without doing.

  Further, according to the present invention, when the pattern of four or more consecutive 0 point information is predetermined, the temporary determination means is adjacent to the target sampling point, not the polarity of the target sampling point value. By determining the state transition based on the polarity of the value of the sampling point, it is possible to determine the state transition based on the polarity of the value of the adjacent sampling point having a higher level than the target sampling point. Therefore, a more accurate provisional discrimination value can be obtained.

  Furthermore, according to the present invention, even in a high-density recording, even if a signal with a small run length, for example, a signal level of 2T becomes small and bit slip easily occurs between the synchronization signal and the synchronization signal, When the absolute value of the phase error supplied from the means exceeds a predetermined threshold, or the maximum value of the phase error is extracted and its position information is estimated as a slip point, and the interval of the synchronization signal is determined not to be a regular interval When this is done, the data length is adjusted at the position based on the slip point information for the digital playback data and likelihood information, so that the bit position after the slip point can be set to a probable location. The error rate can be greatly improved.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of a first embodiment of a reproducing apparatus according to the present invention. In the figure, the run-length limit code (digital signal) photoelectrically converted and amplified by the PD head amplifier 16 from the optical disk 15 on which the run-length limit code is recorded at a high density is blocked by the DC blocking circuit 17 and then the DC component is blocked. Then, the AGC circuit 18 performs automatic gain control (AGC) through an A / D converter (not shown) so that the amplitude becomes constant, and then supplies the result to the resampling / DPLL 19. The position where the A / D converter is provided may be anywhere before the resampling / DPLL 19.

  The resampling / DPLL 19 is a digital PLL circuit in which a loop is completed in its own block. It resamples an input signal sampled with a fixed system clock by an A / D converter at a desired bit rate. Sampled digital data (that is, resampling data of 180 ° out of the phase of digital data of 0 ° and 180 °) is generated and supplied to an adaptive equalization circuit 20 (to be described later) constituting the main part of the present embodiment. .

  Here, “resampling” refers to obtaining sampling data at the timing of the bit clock by performing a thinning interpolation operation from data obtained by A / D conversion at the timing of the system clock. Further, the resampling / DPLL 19 detects a zero cross of the resampling data having a phase of 0 °, and supplies 0 point information obtained thereby to the adaptive equalization circuit 20.

  The 0 point information indicates the point at which bit sampling data crosses the zero level in bit clock units. Further, the resampling / DPLL 19 sets the resampling timing, that is, the frequency and the phase so that it becomes 0 based on the value of the resampling data of the phase 180 ° corresponding to the zero cross point indicated by the 0 point information. Lock it.

  The equalized reproduction waveform to which the PR characteristic is given by the adaptive equalization circuit 20 is supplied to the decoding circuit 38 and is subjected to, for example, Viterbi decoding. The circuit configuration of this Viterbi decoding is well known. For example, a branch metric calculation circuit that calculates a branch metric from sample values of an equalized reproduction waveform, and a path that calculates a path metric by accumulating the branch metrics for each clock. A metric calculation circuit and a path memory for storing a signal for selecting a most probable data series having a minimum path metric. The path memory stores a plurality of candidate series, and outputs the candidate series selected according to the selection signal from the path metric calculation circuit as decoded data.

  The ECC circuit 39 uses the error correction code in the decoded data series from the decoding circuit 38 to correct the code error of the generation element of the error correction code, and outputs decoded data with greatly reduced errors. . In the above configuration, the present embodiment is characterized by the configuration of the adaptive equalization circuit 20, and the adaptive equalization circuit 20 will be described in more detail below.

FIG. 2 shows a block diagram of a first embodiment of the adaptive equalization circuit of the main part of the reproducing apparatus of the present invention.
In the figure, the same components as those in FIG. As shown in FIG. 2, the adaptive equalization circuit 20a of the first embodiment of FIG. 2 corresponding to the adaptive equalization circuit 20 of FIG. Delay of the transversal filter 21 for providing the conversion characteristics, the multiplier / low-pass filter (LPF) 22 for changing the coefficient of the transversal filter 21 according to the error signal, and the resampling / DPLL 19 A tap delay circuit 23, a temporary determination circuit 24 that generates the error signal based on the output signal of the transversal filter 21 and the delay signal from the tap delay circuit 23, and a multiplier / LPF 22 that inverts the polarity of the error signal. And an inverter (INV) 25 to be supplied.

  The tap delay circuit 23 and the provisional discrimination circuit 24 are circuit units that constitute the main part of this embodiment, and have a circuit configuration as shown in FIG. 3, for example. In the figure, the temporary discriminator 51, the subtractor 52, and the D-type flip-flop 53 constitute the temporary discriminating circuit 24 described above. Further, a tap delay circuit unit 23a to which the waveform equalized reproduction signal D5 from the transversal filter 21 is input via the terminal 41, and a tap delay circuit unit 23b to which 0-point information is input via the terminal 42, The tap delay circuit 23 is configured.

  The tap delay circuit unit 23a includes D-type flip-flops 231, 232, and 233 that are cascade-connected in three stages. Further, the tap delay circuit unit 23b is connected in a delay adjuster 234 that delays the 0 point information input via the terminal 42, and a three-stage cascade connection that delays the delay 0 point information output from the delay adjuster 234. It consists of D-type flip-flops 235, 236 and 237.

  The temporary discriminator 51 receives the waveform equalized reproduction signal D5 from the transversal filter 21 input via the terminal 41, the output data D2 and Z2 of the tap delay circuit units 23a and 23b, and the terminal 43. An input later-described PR mode signal and an later-described RLL mode signal input via the terminal 44 are input. The temporary discriminator 51 is composed of a logic circuit, and performs a temporary discriminating operation that skillfully utilizes the characteristics of the partial response characteristics according to an algorithm described later, based on the input signal.

  The subtracter 52 uses a temporary discrimination result from the temporary discriminator 51 based on data (sampling value) D3 obtained by delaying the waveform equalization reproduction signal from the transversal filter 21 by two clock cycles of the system clock by the tap delay circuit unit 23a. Is subtracted to generate an error signal. In the D-type flip-flop 53, the error signal from the subtractor 52 input to the data input terminal is input via the terminal 40 in synchronization with the system clock from the terminal 45 input to the clock terminal. When the bit clock is at a high level, it is latched, and this is output from the Q output terminal to the multiplier / LPF 22 of FIG. 2 via the terminal 54 and the INV 25 of FIG.

  A bit clock is input to each enable terminal (not shown) of the D-type flip-flop 53 and the D-type flip-flops 231 to 233 and 235 to 237 in the tap delay circuit units 23a and 23b via the terminal 40, respectively. In addition, a system clock is input to each clock terminal via a terminal 45, and a reset signal is input to each clear terminal via a terminal 46. As described above, since both the tap delay circuit units 23a and 23b and the provisional determination circuit 24 are configured by digital circuits, the tap delay circuit units 23a and 23b are not affected by aging and parameter variations peculiar to analog, and have high reliability. In addition, the circuit scale hardly increases.

  Here, the partial response (PR) characteristic will be described. For example, if the characteristic of PR (a, b, b, b, a) is added to the solitary wave shown in FIG. As is well known, the waveform is as shown in FIG. Further, in the continuous wave, this equalization waveform takes 10 values of 0, a, 2a, a + b, 2a + b, 2b, a + 2b, 3b, a + 3b, 2a + 3b (provided that a = 1, b = 2, etc.) Since 2a + b = 2b, it takes 9 values.)

  When these 10 values are input to the Viterbi decoder, the original data (input value) and the reproduction signal (output value) after PR equalization are subject to past signal constraints and input by this and (1, 7) RLL. It is known that the signal “1” can be represented by a state transition diagram as shown in FIG.

  In FIG. 4C, S0 to S9 indicate states determined by the immediately preceding output value. From this state transition diagram, for example, in the state S2, when the input value is a + 2b, the output value becomes 1 and the state transitions to the state S3. When the input value is 2b, the output value becomes 1 and the state transitions to the state S4. It can be seen that no other input value is input, and if it is input, it is an error.

  FIG. 5 is a diagram showing the relationship between the characteristics of the PR (a, b, b, b, a) and the temporary discrimination value output by the temporary discriminator 51. In the figure, the row indicated by the PR mode indicates the value of the PR mode signal input to the temporary determination circuit 24 (temporary determination device 51) via the terminal 43 of FIG. The value of this PR mode signal has a partial response characteristic of PR (1, 2, 2, 2, 1), PR (1, 3, 3, 3, 1) and PR (1, 1, 1, 1, 1). One of them. PR (3, 4, 4, 4, 3) or the like is also possible.

  In FIG. 5, RLL (1, X) is a minimum length inversion interval of “2”, and the maximum inversion interval is a run length restriction rule with a predetermined value X that varies depending on the modulation method. RLL (2, X) is the minimum. A run-length limiting rule having a predetermined value X with an inversion interval of “3” and a maximum inversion interval depending on the modulation scheme is shown.

  In the case of RLL (1, X), as described in conjunction with FIG. 4, the equalized waveform is 0, a, 2a, a + b, 2a + b, 2b, a + 2b, PR (a, b, b, b, a). Ten values of 3b, a + 3b, and 2a + 3b are taken, and provisional determination values in each partial response characteristic corresponding to these are shown in FIG. RLL (2, X) indicates a provisional determination value similar to RLL (1, X), but there are no values in two rows indicated by 2a + b and 2b of RLL (1, X). This is because the state transition diagram for PR (a, b, b, b, a) and RLL (2, X) is as shown in FIG. 4 (D), and RLL (1, This is because there are no transitions of S2 → S4, S4 → S7, S7 → S5, and S5 → S2 in the state transition diagram at the time of (X).

  Next, returning to FIG. 3 again, the operation of the circuit shown in FIG. 3 will be described. The waveform equalized reproduction signal from the transversal filter 21 input via the terminal 41 is supplied to the tap delay circuit unit 23a. The tap delay output is input to the temporary discriminator 51. Here, the sampling value of the waveform equalization reproduction signal supplied to the tap delay circuit unit 23a is set to D5, and the output sampling values (tap delay outputs) of the D-type flip-flops 231, 232, and 233 in the tap delay circuit unit 23a. Are D4, D3, and D2, sampling values (signals to be determined) at the current time are handled as D3, and signals (sampling values) at times before and after the current time are handled as D2 and D4.

  On the other hand, 0 point information from the resampling / DPLL 19 is supplied to the tap delay circuit unit 23 b via the terminal 42, and the tap delay output is input to the temporary discriminator 51. Here, 0 point information output after delay adjustment by the delay adjuster 234 is Z5, and output 0 point information of the D flip-flops 235, 236, and 237 is Z4, Z3, and Z2. Z2, Z3, and Z4 correspond to D2, D3, and D4 in terms of time. The tentative discriminator 51 performs tentative discrimination (convergence target setting) based on partial response equalization according to an algorithm described later.

  The tap delay output signal D3 at the current time output from the tap delay circuit unit 23a is also supplied to the subtractor 52. The subtractor 52 is obtained by the temporary discriminator 51 from the tap delay output signal D3 at the current time. An error signal is calculated by subtracting the discrimination result, the error signal is latched by the D-type flip-flop 53, and then the polarity is inverted by the inverter 25 of FIG. 2 via the output terminal 54, and then output to the multiplier / LPF 22. . The error signal whose polarity has been inverted by the inverter 25 is multiplied by the tap output from the transversal filter 21 by the multiplier / LPF 22, and then the high frequency component is removed. It is output to the transversal filter 21 as a coefficient (filter coefficient).

  Next, the operation of the temporary discriminator 51 will be described in more detail with reference to the flowcharts of FIGS. Here, when the value Z of the 0 point information is “1”, this indicates a zero cross point, which is represented by PR (a, b, b, b, a) shown in FIG. In the state transition diagram of (1, X), it occurs in the process of transition from state S2 → S3 or state S2 → S4 or state S7 → S6 or state S7 → S5. In the case of PR (a, b, b, b, a), there is no sample point corresponding to 0 cross, so when the value Z of 0 point information is “1”, the value immediately after the zero cross is performed. , A + 2b, 2b, a + b, and 2a + b.

  In the above example, the handling is performed immediately after the zero crossing, but even if the 0 point information is associated immediately before, the same effect can be obtained if the flowchart described later is modified accordingly. . In this case, when the value Z of the 0 point information is “1”, the state transition diagram of RLL (1, X) in PR (a, b, b, b, a) in FIG. In the state S1 → S2 or the state S5 → S2 or the state S8 → S7 or the state S4 → S7.

  In this case, in FIG. 4C, the right half follows the path of the positive value and the left half follows the path of the negative value. Therefore, by referring to the value before or after the zero cross point, the positive path Or whether it is a negative path.

  Moreover, if the interval from one zero cross point to the next zero cross point is known, that is, “from state S3 to state S6, from state S3 to state S5, from state S4 to state S5, or state From S4 to state S6, or "From state S6 to state S3, from state S6 to state S4, from state S5 to state S3, or from state S5 to state S4" If the number of transitions of “,” is known, the route is determined, and the possible values are clear for each sample point.

  In the state transition diagram, when the value other than “a + b” is not a zero cross point, the value Z of the above 0 point information is “0”. From this state transition diagram, two zero-cross points (Z = 1) are not extracted consecutively, and in the case of RLL (1, X), at least one "" between adjacent Z = 1. 0 ″ exists (when the value Z of the 0 point information changes from 1 → 0 → 1, that is, when the state S4 → S7 → S5 or the state S5 → S2 → S4 transitions). In the case of RLL (2, X), there are at least two “0” s between adjacent Z = 1. This is because there are no values of 2a + b and 2b.

  In the actual signal, it is fully expected that the detection of the zero cross point itself will be erroneous due to the influence of noise, etc., but in the case of feedback control, if the probability of correct determination exceeds the probability of error, it converges in the correct direction. In addition, it is considered that there is no practical problem with single noise because of sufficient integration processing.

  Paying attention to the above points, the temporary discriminator 51 first identifies the value Z of the 0 point information output from the tap delay circuit 23 for each cycle of the bit clock, and the four values Z of the continuous 4 clock cycles. It is determined whether or not (value obtained by arranging Z2, Z3, Z4, and Z5) is all “0” (step 61 in FIG. 6). Hereinafter, FIGS. 6 and 7 show an example in which the RLL mode is (1, X).

This pattern is a case where the values Z3 and Z4 of the front and rear 0 point information are both “0” when the center value 0 point information value Z3 of interest is “0”. Since the signal waveform is stuck on the positive side or the negative side, when this pattern is satisfied, Q = 2a + 3b (when D3 ≧ 0) depending on whether the current time signal D3 is 0 or more or negative )
Q = 0 (when D3 <0) (1)
The provisional determination value Q is calculated by the following formula (Steps 71, 81a, 81b in FIG. 6).

If it is not the above pattern, it is determined whether or not the first three (Z2, Z3, Z4) of the four zero point information values Z of four consecutive clock cycles are “101” (step 62 in FIG. 6). ). In FIG. 6, * means that the value may be 0 or 1. This pattern is a case where the value Z3 of the 0-point information of the median value of interest is “0”, and both the two Z values adjacent to both sides before and after the median value are “1”. As described above, it may occur only when RLL (1, X). When this pattern is satisfied, Q = 2b (when D3 ≧ 0) depending on whether the signal D3 at the current time is 0 or more or negative.
Q = 2a + b (when D3 <0) (2a)
Or, depending on whether the signal D4 is negative or not, Q = 2b (when D4 <0)
Q = 2a + b (when D4 ≧ 0) (2b)
The provisional discrimination value Q is calculated by the following formula (steps 72, 82a, and 82b in FIG. 6).

  Here, when the determination is made using the signal D3, the polarity is likely to be erroneous because the 2T peak level (D3) is small due to the high density of the optical disk. By using the fact that the signal D4 has a reverse polarity, a more accurate determination can be made (a more reliable determination method will be described in the second embodiment).

If it is not the above pattern, it is determined whether or not the first three (Z2, Z3, Z4) of the four zero point information values Z of four consecutive clock cycles are “001” (step 63 in FIG. 6). ). This pattern is a case where only one side Z4 of two Z values adjacent to both sides before and after the median is “1” when the Z value of the median 0 point information of interest is “0”. When the pattern is satisfied, Q = a + 2b (when D3 ≧ 0) depending on whether the current time signal D3 is 0 or more or negative.
Q = a + b (when D3 <0) (3a)
Or Q = a + 2b (when D2 ≧ 0) depending on whether the signal D2 is 0 or more or negative
Q = a + b (when D2 <0) (3b)
The provisional discrimination value Q is calculated by the following formula (steps 73, 83a, 83b in FIG. 6).

  Here, when the determination is made using the signal D3, since it is close to the zero cross point, D3 becomes small and the polarity is likely to be erroneous. On the other hand, if the signal D2 has the same polarity and has a large level, more accurate determination can be made.

If it is not the above pattern, it is determined whether or not the values 0 of the four 0-point information in successive four clock cycles are “1000” (step 64 in FIG. 6). This pattern is a case where the value Z3 of the 0-point information of the median value of interest is “0”, and only the previous information Z2 is “1”. When this pattern is satisfied, the current time signal Q = a + 3b (when D3 ≧ 0) depending on whether D3 is 0 or more or negative
Q = a (when D3 <0) (4)
The provisional determination value Q is calculated by the following formula (steps 74, 84a, 84b in FIG. 6).

If it is not the above-mentioned pattern, it is determined whether or not the values 0 of the four 0-point information in successive four clock cycles are “0001” (step 65 in FIG. 6). This pattern is the case where the last value Z5 is "1" when the median zero point information value Z3 of interest is "0". When this pattern is satisfied, the signal D3 at the current time is Q = a + 3b (when D3 ≧ 0) depending on whether 0 or more or negative
Q = a (when D3 <0) (5)
The temporary determination value Q is calculated by the following formula (steps 75, 85a, 85b in FIG. 6).

If it is not the above pattern, it is determined whether or not the values 0 of the four 0-point information in four consecutive clock cycles are “0101” (step 66 in FIG. 7). This pattern is a case where the last value Z5 is "1" when the value Z3 of the 0-point information of the median value of interest is "1". When this pattern is satisfied, the signal D3 at the current time is 0. Q = 2b (when D3 ≧ 0) depending on whether it is above or negative
Q = 2a + b (when D3 <0) (6)
The provisional determination value Q is calculated by the following equation (steps 76, 86a, 86b in FIG. 7).

If it is not the above pattern, it is determined whether or not the values 0 of the four 0-point information in four consecutive clock cycles are “0100” (step 67 in FIG. 7). In this pattern, when the value Z3 of the 0-point information of the median value of interest is “1”, all other information is “0”. If this pattern is satisfied, the signal D3 at the current time is 0 or more. Q = a + 2b (if D3 ≧ 0)
Q = a + b (when D3 <0) (7a)
Or Q = a + 2b (when D4 ≧ 0) depending on whether the signal D4 is 0 or more or negative
Q = a + b (when D4 <0) (7b)
The provisional determination value Q is calculated by the following formula (steps 77, 87a, 87b in FIG. 7).

  Here, when the determination is made using the signal D3, the 2T peak level (D3) becomes small and the polarity is likely to be erroneous. On the other hand, if the signal D4 has the same polarity and has a large level, more accurate determination can be made.

If it is not the above pattern, it is determined whether or not the values 0 of the four 0-point information in successive four clock cycles are “1001” (step 68 in FIG. 7). This pattern is a case where the first information Z2 and the last information Z5 are "1" when the value Z3 of the 0-point information of the median value of interest is "0". Q = 3b (when D3 ≧ 0), depending on whether the signal D3 is greater than 0 or negative
Q = 2a (when D3 <0) (8)
The provisional determination value Q is calculated by the following formula (steps 78, 88a, 88b in FIG. 7).

If none of the above patterns is possible, it is impossible on the state transition diagram. Therefore, when this pattern is satisfied, Q = 2b (D3 ≧ 0) depending on whether the signal D3 at the current time is 0 or more or negative. in the case of)
Q = 2a + b (when D3 <0) (9)
The provisional temporary determination value Q is calculated by the following formula (steps 79, 89a, 89b in FIG. 7).

The above provisional determination processing is described for the case where the RLL mode is (1, X), but the provisional determination processing for the case where the RLL mode is (2, X) is as shown in the flowcharts of FIGS. Become. In both figures, the same processes as those in FIGS. 6 and 7 are denoted by the same reference numerals, and the description thereof is omitted. As described above, in the case of RLL (2, X), at least two “0” s between adjacent Z = 1.
"Is present.

  Therefore, as shown in FIGS. 8 and 9, in the temporary determination processing of RLL (2, X), the three consecutive 0 point information (Z2, Z3, Z4) in step 62 of FIG. 6 is “101”. 7 and the determination of whether or not the four consecutive zero point information values Z in Step 66 in FIG. 7 are “0101” are not necessary, and accordingly, Steps 72, 82a, 82b, 76, 86a and 86b. This processing is unnecessary. Other than that, it is the same as the provisional discrimination processing of RLL (2, X).

  The provisional judgment value Q obtained by the above provisional judgment processing is supplied to the subtracter 52 in FIG. 3 and is taken as a difference signal from the waveform equalization signal D3 at the current time, and as described above, After being latched by the D-type flip-flop 53, it is output to the multiplier / LPF 22 of FIG. 2 via the output terminal 54 and the INV 25 of FIG. 2, and after being multiplied here, the high frequency component is removed, and the transversal filter 21 Is output as a tap coefficient.

  In this way, the tap coefficient of the transversal filter 21 is variably controlled so that the error signal extracted from the subtractor 52 in FIG. It can be suitably performed by enlarging.

  Next, the waveform equalization by the provisional determination process will be described more specifically. For example, when the equalized reproduction signal having the waveform shown by the solid line in FIG. 10A is extracted from the transversal filter 21 shown in FIG. 2 and input to the temporary discrimination circuit 24 via the tap delay circuit 23, The temporary discrimination circuit 24 also receives 0 point information of the value Z as shown at the bottom of the waveform of FIG. Here, in FIG. 10 (A), ◯ indicates a sample point for equalization when partial response equalization is performed by the transversal filter 21, and this is in the same phase as the original data point (other FIG. 10). (B) and FIGS. 11A and 11B are the same).

  In FIG. 10A, first, the value Z of four consecutive 0-point information becomes “0100”, and at this time, equalization is performed based on the above-described equation (7) (step 67 in FIG. 7). Note that the waveform equalization based on the calculation result of the above equation (7) is performed according to four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3 or D4. What is performed is as described above. Here, since D3> 0, Q is a + 2b (steps 77 and 87a in FIG. 7).

  Next, in FIG. 10A, the value Z of the four consecutive 0-point information becomes “1000”, and at this time, equalization is performed based on the equation (4) (step 64 in FIG. 6). Note that the waveform equalization based on the calculation result of the above equation (4) is performed according to the four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3. This is as described above. Here, since D3> 0, Q is a + 3b (steps 74 and 84a in FIG. 6).

  Next, in FIG. 10A, the values Z of the continuous four 0-point information are all “0”, and at this time, the waveform is equalized based on the equation (1) (step 61 in FIG. 6). . Note that the waveform equalization based on the calculation result of the above equation (1) is performed according to four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3. This is as described above. Here, since D3> 0, Q is 2a + 3b (71 and 81a in FIG. 6).

  Next, the value Z of the four consecutive zero point information is all “0” in the same manner as described above, and the same waveform equalization as described above is performed. Subsequently, in FIG. 10A, the value Z of the four consecutive 0 point information becomes “0001”, and at this time, the waveform is equalized based on the equation (5) (step 65 in FIG. 6). Note that the waveform equalization based on the calculation result of the above equation (5) is performed according to four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3. This is as described above. Here, since D3> 0, Q is a + 3b (steps 75 and 85a in FIG. 6). Thereafter, by repeating the same operation as described above, the waveform after equalization in FIG. 10A becomes as shown in FIG.

  FIG. 11A shows another example of the output signal waveform after output equalization of the transversal filter 21. A reproduced signal after equalization of the waveform indicated by a solid line in FIG. 11A (which is assumed to be a signal of RLL (1, X)) is extracted from the transversal filter 21 shown in FIG. When input to the provisional discrimination circuit 24 via the circuit 23, the zero-point information of the value Z as shown in the lower part of the waveform in FIG. The Here, in FIG. 11 (A), a circle indicates a sample point for equalization when the partial response equalization is performed by the transversal filter 21, and this is the same phase as the original data point.

  In FIG. 11A, first, the value Z of four consecutive 0-point information is “0101”. At this time, the waveform is equalized based on the equation (6) (step 66 in FIG. 7). Note that the waveform equalization based on the calculation result of the above expression (6) is performed according to four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3. This is as described above. Here, since D3 <0, Q is 2a + b (steps 76 and 86b in FIG. 7).

  In FIG. 11 (A), the first three (Z2, Z3, Z4) of the following four consecutive zero point information values Z are “101”. At this time, based on the above equation (2) The waveform is equalized (step 62 in FIG. 6). Note that the waveform equalization based on the calculation result of the above equation (2) is performed according to three consecutive zero point information values Z (Z2, Z3, Z4) and the polarity of the waveform equalization signal D3 or D4. This is as described above. Here, since D4> 0, Q is 2a + b.

  Subsequently, in FIG. 11A, the value Z of the continuous four 0-point information becomes “0100”, and at this time, waveform equalization is performed based on the equation (7) (step 67 in FIG. 7). . Note that the waveform equalization based on the calculation result of the above expression (7) depends on the four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3 or D4. What is performed is as described above. Here, since D3> 0, Q is a + 2b (steps 77 and 87a in FIG. 7).

Further, in FIG. 11 (A), the value Z of the following four consecutive 0-point information becomes “1001”, and at this time, the waveform is equalized based on the equation (8) (step 68 in FIG. 7).
Note that the waveform equalization based on the calculation result of the above equation (8) is performed according to four consecutive zero point information values Z (Z2, Z3, Z4, Z5) and the polarity of the waveform equalization signal D3. This is as described above. Here, since D3> 0, Q is 3b. Thereafter, by performing the same operation, the post-equalization waveform shown in FIG. 11A becomes a waveform shown in FIG.

  As described above, in this embodiment, the value Z of the 0 point information is referred to, and the waveform is equalized to a value determined directly from the state transition, so that it does not depend on the level of the current sample point (others (Even if it is close to the target value, it is not affected.) Accurate waveform equalization is possible. In addition, it is possible to cope with different partial response equalization, and further, since the probability of erroneous determination is less than that of a conventional device with a fixed threshold, the convergence time can be shortened. Note that the present embodiment can be similarly applied to RLL (2, X). This is because the state transition substantially similar to RLL (1, X) is performed as described with reference to FIG.

12 and 13 show examples of the eye pattern of the output signal of the decoding circuit of this reproducing apparatus.
12 and 13, the vertical axis represents the quantization level, and the horizontal axis represents time. The example shown in FIG. 12 is an example in which the value of the PR mode signal is “1”, that is, PR (1, 2, 2, 2, 1) and RLL (1, X), and 0, a, 2 a, a + b. , 2a + b, 2b, a + 2b, 3b, a + 3b, 2a + 3b corresponding to 9 values of 0, 1, 2, 3, 4, 5, 6, 7, 8 (however, the actual data is 8 Since it is a value quantized with bits or the like, it is a value multiplied by the gain.)

  The example shown in FIG. 13 is an example in which the value of the PR mode signal is “2”, that is, PR (1, 3, 3, 3, 1) and RLL (1, X), and 0, a, 2 a, a + b. , 2a + b, 2b, a + 2b, 3b, a + 3b, 2a + 3b corresponding to 10 values of 0, 1, 2, 4, 5, 6, 7, 9, 10, 11 (however, the actual data is Since it is a value quantized by 8 bits, etc., it is a value multiplied by the gain.) As shown in FIG. 12 and FIG. 13, according to the reproducing apparatus of the present embodiment, it can be seen that the values converge well to each value and accurate waveform equalization is achieved.

  Next, another embodiment of the present invention will be described. FIG. 14 shows a block diagram of a second embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. As shown in FIG. 14, the adaptive equalization circuit 20b of the second embodiment corresponding to the adaptive equalization circuit 20 of FIG. 1 has a PR equalization characteristic for the resampling data from the resampling / DPLL 19a. A transversal filter 21 to be applied, a multiplier / low-pass filter (LPF) 22 that varies the coefficient of the transversal filter 21 according to an error signal, a tap delay circuit 23, an output signal of the transversal filter 21, and a tap Based on the delay signal from the delay circuit 23, the error signal is generated and supplied to the multiplier / LPF 22, and the zero crossing point of the output signal of the transversal filter 21 is detected to the tap delay circuit 23. A zero detector 26 is provided.

  For example, when the polarity of the reproduction signal after input equalization is inverted, the zero detector 26 supplies the tap delay circuit 23 with 0 point information that is closer to 0 out of the two neighboring sample points. Thus, this embodiment also performs the same operation as that of the embodiment of FIG.

  By the way, the resampling / DPLLs 19 and 19a have an AGC circuit and an ATC circuit on their input sides and an adaptive equalization circuit 20 (20a and 20b) on their output sides. Therefore, there is an advantage that reliable convergence can be expected, an external circuit is not required, the configuration is simple, and the digital circuit is highly reliable. However, the present invention is not limited to this, and can be applied to a configuration that does not use resampling / DPLL as in the following embodiments.

  FIG. 15 shows a block diagram of a third embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. As shown in FIG. 15, the adaptive equalization circuit 20 c of the third embodiment corresponding to the adaptive equalization circuit 20 of FIG. 1 performs A / D conversion on the reproduction signal, not the signal from the resampling / DPLL 19. In addition, a signal subjected to automatic gain control and further subjected to DC control (ATC control) is received as an input signal, and zero point information is received by a zero-cross detection / phase comparator 31 to which a reproduction signal after equalization of the transversal filter 21 is input. There is a feature in the point to detect.

  The zero cross detection / phase comparator 31 detects the zero cross signal after the equalization reproduction signal of the transversal filter 21 and compares the phase of the detected zero cross point with the phase of the bit clock from the voltage controlled oscillator (VCO) 33. A phase error signal is generated. This phase error signal is applied as a control voltage to a voltage controlled oscillator (VCO) 33 through a loop filter 32, and variably controls its output system clock frequency. The system clock of the VCO 33 includes the above-described bit clock, and is applied to each block that requires the device clock.

  The loop filter 32 and the VCO 33 can be configured as either digital or analog. In the case of analog, an interface for performing D / A conversion is required. This embodiment also has the same features as the above embodiments.

  FIG. 16 shows a block diagram of a fourth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. As shown in FIG. 16, the adaptive equalization circuit 20d of the fourth embodiment corresponding to the adaptive equalization circuit 20 of FIG. 1 is not a signal from the resampling / DPLL 19, but is pre-equalized as necessary. The digital signal obtained by A / D converting the reproduced signal by the A / D converter 34 is input to the zero detector 27 together with the transversal filter 21 to detect 0 point information.

  The input reproduction signal of the A / D converter 34 is supplied to the phase comparator 35, and the phase of the zero cross point and the phase of the bit clock from the voltage controlled oscillator (VCO) 37 are phase-compared and converted into a phase error signal. After that, it is applied as a control voltage to a voltage controlled oscillator (VCO) 37 through a loop filter 36 to variably control its output system clock frequency. The loop filter 36 and the VCO 37 can be configured as either digital or analog. In the case of analog, an interface for performing D / A conversion is required. The system clock of the VCO 37 includes the above-described bit clock, and is applied to each block that requires the device clock. Delay adjustment is performed as necessary.

  On the other hand, when the polarity of the signal from the A / D comparator 34 is inverted, for example, the zero detector 27 sends the closer to zero of the two neighboring sample points to the tap delay circuit 23 as 0 point information. Supply. This embodiment also has the same features as the above embodiments.

  FIG. 17 shows a block diagram of a fifth embodiment of the adaptive equalization circuit of the main part of the apparatus of the present invention. In the figure, the same components as those in FIG. As shown in FIG. 17, the adaptive equalization circuit 20 e of the fifth embodiment corresponding to the adaptive equalization circuit 20 of FIG. 1 is that an error selection circuit 55 is provided between the temporary determination circuit 24 and the INV 25. There are features.

For example, as shown in FIG. 18, the error selection circuit 55 receives the error signal output from the temporary determination circuit 24 at the first input terminal 551 and another output from the temporary determination circuit 24 at the second input terminal 552. The temporary discrimination information is input, and includes a selection circuit 553, a switch circuit 554, and a zero generator 555. The temporary determination information output from the temporary determination circuit 24 should be set to the target value for PR equalization, and the deviation from the target value is output as an error signal. A value where the circuit 24 is away from the zero cross point as a target value, for example,
0, 2a + 3b
Or 0, a, a + 3b, 2a + 3b
Or 0, a, 2a, 3b, a + 3b, 2a + 3b
In the case of “0”, “0” is output. Otherwise, “1” is output.

  That is, the switch circuit 554 receives the error signal input to the terminal 554a and the fixed value 0 from the 0 generator 555 input to the terminal 554b as inputs, and supplies the output signal of the selection circuit 553 as a switching signal. When the output signal of the selection circuit 553 is “1”, the effective component of the error signal input to the terminal 554a is selected. When the output signal of the selection circuit 553 is “0”, the value input to the terminal 554b. Select 0 to disable the error signal.

  The signal selected by the switch circuit 554 is supplied to the multiplier / LPF 22 via the output terminal 556 via the INV 25 in FIG. 17, and after being multiplied by the tap output from the transversal filter 21, the high frequency component is obtained. After the removal, tap coefficients (filter coefficients) that make the above error signal zero are input to the transversal filter 21.

  Next, the operation of this embodiment will be described taking the case of PR (1, 2, 2, 2, 1) as an example. In the adaptive equalization circuit 20a or the like that does not have the error selection circuit 55, when the output signal of the adaptive equalization circuit 20 is a signal that is correctly PR equalized as indicated by I in FIG. The error signal output from the temporary discrimination circuit 24 has a slight deviation from the target value as schematically shown in FIG. 19B, and correct waveform equalization is achieved. can get.

  However, as seen in the reproduction signal from the optical disk, when the output signal of the adaptive equalization circuit 20 has a large distortion in the reproduction signal as indicated by II in FIG. Deviation occurs in the waveform portion III that is a sample point and deviates from the zero cross, and the error signal output from the temporary discrimination circuit 24 has a large deviation from the target value as schematically shown by IV in FIG. An error occurs. That is, inaccurate data appears at sample points that are not near the zero cross.

  Therefore, in this embodiment, the error selection circuit 55 having the configuration shown in FIG. 18 is provided on the output side of the temporary discrimination circuit 24 as shown in FIG. 17, and error signals at sample points other than the sample points near the zero cross are output. Since the error signal is invalidated by outputting a fixed value of 0, a signal that has a large distortion and is not correctly PR-equalized as shown in FIG. In the adaptive equalization circuit 20e, sample points where the error signal output from the error selection circuit 55 is not near zero-crossing are indicated by black triangles, as shown in FIG. Is replaced with a fixed value of 0.

  Therefore, even in a sample position where a large deviation from the target value occurs when the error selection circuit 55 is not present, in this embodiment, as indicated by V in FIG. 21B, there is no deviation from the target value. To be. As described above, in this embodiment, an uncertain error signal among error signals is invalidated, and only the probable one is used as an effective component of the error signal, so that it can be converged to a correct target value. Can improve.

  The DC component that deviates from the target value of the partial response is integrated for each target value, and a new target value for Viterbi decoding in the subsequent stage is generated based on this value, so that it is possible to detect with certainty.

  Next, another embodiment relating to step 62 in FIG. 6 will be described. This pattern is a case where when the value Z3 of the 0-point information of the median value of interest is “0”, both of the two Z values adjacent to both sides before and after the median value are “1”. As described above, it may occur only when RLL (1, X). When this pattern is satisfied, the levels of the signals D2, D3, and D4 are concentrated near the zero cross, and the polarity determination error is most likely to occur. That is, it is easy to erroneously determine whether the state transition is S4 → S7 or S5 → S2.

Therefore, reference values for the state transition of S2 → S4 → S7 → S5 as shown in FIG. 22A, for example (2b), (2b), (2a + b), and S7 → as shown in FIG. By preparing reference values for state transitions of S5 → S2 → S4, for example (2a + b), (2a + b), (2b), calculating Euclidean distances with D2, D3, and D4, respectively, and comparing the sum, Make a probable decision. That means
UD1 = (D2- (2b)) 2 + (D3- (2b)) 2 + (D4- (2a + b)) 2
UD2 = (D2- (2a + b)) ² + (D3- (2a + b)) ²
+ (D4- (2b)) ²
And
Q = 2b (when UD1 ≦ UD2)
Q = 2a + b (when UD1> UD2)
The provisional determination value Q is calculated by the following formula. Here, transitions of S2->S4->S7-> S6 and S7->S5->S2-> S3 are also conceivable, but there is no problem in making a relative comparison in the determination of the Euclidean distance. In this way, the correct polarity determination can be performed even in a small level and a lot of noise, so that a correct provisional determination value can be obtained.

  FIG. 23 is a circuit diagram of these operations, and shows a block diagram of another embodiment of the temporary discriminator 51. In the figure, the signal D2 is subtracted by the output signals of the 2b generator 101, 2a + b generator 102 and the subtractors 103, 104, respectively, and then squared by square calculators (multipliers) 105, 106. Similarly, the signal D3 is subtracted by the output signals of the 2b generator 107 and 2a + b generator 108 and the subtractors 109 and 110, respectively, and then squared by the square calculators (multipliers) 111 and 112, and the signal D4 Are subtracted by the subtractors 115 and 116 from the output signals of the 2a + b generator 113 and 2b generator 114, respectively, and squared by square calculators (multipliers) 117 and 118, respectively.

  The adder 119 adds the output signals of the square calculators (multipliers) 105, 111, and 117 to output a first addition signal represented by the arithmetic expression represented by the UD1, and the adder 120 By adding the output signals of the multipliers (multipliers) 106, 112, and 118, a second addition signal represented by the arithmetic expression represented by UD2 is output. The subtractor 121 performs subtraction by subtracting the second addition signal from the first addition signal, and supplies the obtained subtraction result to the determination circuit 122.

  The determination circuit 122 outputs 1 when the value of the input subtraction result is positive (ie, UD1> UD2), and outputs 0 when it is 0 or less (ie, UD1 ≦ UD2). The switch circuit 123 outputs the 2a + b value signal output from the 2a + b generator 125 as the temporary determination value Q when the output signal of the determination circuit 122 is 1, and the 2b generator when the output signal of the determination circuit 122 is 0. A signal having a value of 2b output from 124 is output as a temporary determination value Q.

  Next, the recording / reproducing apparatus of the present invention in which an error countermeasure due to bit slip is taken will be described. 24A and 24B are block diagrams of the recording system and the reproducing system of the first embodiment of the recording / reproducing apparatus according to the present invention. In FIG. 9A, digital information is supplied to an ECC parity generation circuit 131 and added with parity (turbo code, LDPC, etc.), and then subjected to a known interleaving process in an interleave circuit 132 to obtain a run length code. Is supplied to the circuit 133.

  The run-length encoding circuit 133 generates a code string (that is, a run-length limited code) subjected to run-length restriction / DSV (Digital Sum Variation) by 1-7pp modulation or 8-15 modulation. The strategy circuit 134 converts the laser light into a high frequency pulse for modulating the laser based on the run length limit code, and supplies the high frequency pulse to an optical head (not shown) to record digital information on the optical disk.

  Next, the reproduction system shown in FIG. A signal read from the optical disk by a known means by an optical head is supplied to an A / D converter 141 and sampled by a master clock to be converted into a digital signal, and then an AGC / ATC circuit. 142, automatic gain control (AGC) in which the amplitude is controlled to be constant, and automatic threshold control (ATC) in which direct current (DC) control is appropriately performed for the threshold of the binary comparison are performed.

  The output signal of the AGC / ATC circuit 142 is supplied to the resampling / DPLL 143. Resampling / DPLL 143 is a digital PLL (phase-locked loop) circuit in which a loop is completed in its own block, and is generated by resampling (decimating interpolation) an input signal at a desired bit rate. Data (that is, resampling data of 180 ° out of the phase 0 ° and 180 ° of the resampling data) is supplied to the transversal filter in the adaptive equalization circuit 144.

  The resampling / DPLL 143 detects the zero crossing of the resampling data, and based on the value of the resampling data corresponding to the zero crossing point, the resampling timing, that is, the frequency is set so that the phase error becomes zero. Lock it. From the resampling / DPLL 143, zero point information, which is a zero cross detection signal, is supplied to the adaptive equalization circuit 144, and a phase error is supplied to a run length decoding circuit 147 described later.

  The resampling / DPLL 143 is configured as shown in the block diagram of FIG. 25, for example. In the figure, an interpolator 1431 receives a digital signal output from the AGC / ATC circuit 142 shown in FIG. 24B and data point phase information and a bit clock output from a timing generator 1434 described later. It is received as a signal, and the data value of the phase point data is estimated by interpolation from the input data point phase information and the bit clock, and is output.

  The output data value of the interpolator 1431 is supplied as a resampling signal to the adaptive equalization circuit 144 in FIG. 24B and also to the phase detector 1432. The phase detector 1432 detects the zero cross point from the resampling signal and outputs it as a phase error signal using the data value at the zero cross point. This phase error signal is integrated by the loop filter 1433 and then supplied to the timing generator 1434, where the next data point phase of the output of the loop filter 1433 is estimated. The generated bit clock is supplied to the interpolator 1434.

  Referring back to FIG. 24B again, the adaptive equalization circuit 144 uses the resampling / DPLL 143 to resample data generated by resampling (decimating interpolation) the input signal at a desired bit rate. This is received as an input signal, and a partial response (PR) characteristic is given to this input signal and supplied to the decoding circuit 145. The decoding circuit 145 performs, for example, Viterbi decoding (or SOVA or MAP decoding) on the equalized reproduction waveform supplied from the adaptive equalization circuit 144.

The circuit configuration of Viterbi decoding is well known, and as described above, for example, a branch metric calculation circuit that calculates a branch metric from sample values of a post-equalization reproduction waveform, and a path metric by accumulating the branch metric every clock. And a path memory for storing a signal for selecting the most probable data series having the smallest path metric. The path memory stores a plurality of candidate series, and outputs the candidate series selected according to the selection signal from the path metric calculation circuit as decoded data.
Viterbi decoding may be binary with hard decision, or may be output together with likelihood information by soft decision. Of course, the posterior probability method (APP) may be used.

  The decoded signal obtained by decoding by the decoding circuit 145 includes a main signal that is a decoded signal of digital information and likelihood information, and is supplied to the synchronization signal detection circuit 146 where it is added in advance to the reproduction signal. The synchronization signal is detected and output as synchronization signal timing information, and the main signal and likelihood information are output as they are and supplied to the run-length decoding circuit 147. The phase error output from the resampling / DPLL 143 is also supplied to the run-length decoding circuit 147.

For example, the run-length decoding circuit 147 has a configuration shown in the block diagram of FIG.
In FIG. 26, the main signal and likelihood information output from the synchronization signal detection circuit 146 are delayed by the delay circuit 1471, and the above phase error is delayed by the delay circuit 1472 to the data length recovery unit 1473. Supplied. On the other hand, in the synchronization signal timing information output from the synchronization signal detection circuit 146, the time interval between two adjacent synchronization signals is counted based on the clock by the counting circuit 1474, and the count result is supplied to the error determination circuit 1475. The

  The error determination circuit 1475 compares the reference data length from the reference data length generator 1476 with the count result corresponding to the synchronization signal interval from the counting circuit 1474, and generates data length error information indicating whether they are equal. To the data length recovery unit 1473. The data length recovery unit 1473 extracts the maximum value of the phase error when the absolute value of the phase error exceeds a predetermined threshold, detects slip point information having the position information, and based on the data length error information. When it is determined that the length is not a regular length, the data length is adjusted (interpolated or thinned out) at the position based on the slip point information for the input main signal and likelihood information. , Recover the data length.

  The main signal and likelihood information output from the data length recovery unit 1473 are supplied to the run-length decoder 1477, and are run-length decoded (likelihood conversion) to obtain a run-length decoded signal. Here, in the case of run-length decoding, in addition to normal RLL decoding, work for converting LLR (likelihood ratio of posterior probabilities) is required. That is, the LLR corresponding to each channel bit is input, and the LLR corresponding to each decoded data bit is output.

In the run length encoding in the recording system described above, when 1-7pp modulation is performed, 1-7pp is encoded by conversion from 2 bits to 3 bits. Therefore, when decoding 3 bits into 2 bits, Look at each of the three bits before and after (sliding window).
If this total of 9 bits is {C0, C1, C2, C3, C4, C5, C6, C7, C8}, the possible combination of 1 and 0 as a code is converted into 2 bits (dk, dk) of data bits. In correspondence with (+1), the table shown in FIG. 27 is created and decrypted using this table. There are 4 tables in each of 20 rows, and there are a total of 80 patterns. Depending on the pattern, the front and rear may be 2 bits and 7 bits.

  The LLR corresponding to the decoded data bit can be calculated by the following arithmetic expression.

また、前述した記録系でのランレングス符号化に際して、８−１５変調を行ったときには、８−１５変調は８ビットを１５ビットの変換により符号化するので、ある１５ビットを８ビットに復号する場合は、前後の各１５ビットを同時に見る(スライディング・ウィンドウ)。この計４５ビットを｛Ｃ０，Ｃ１，Ｃ２，・・・，Ｃ４４｝としたとき、符号として可能性のある１、０の組み合わせを、データビットの８ビット（ｄk，ｄk+1，ｄk+2，・・・，ｄk+7）に対応させて、図２８に示すテーブルを作成し、これを用いて復号す
る。

In addition, when 8-15 modulation is performed in the above-described run length encoding in the recording system, since 8-15 modulation encodes 8 bits by conversion of 15 bits, certain 15 bits are decoded into 8 bits. In this case, the 15 bits before and after are viewed simultaneously (sliding window). When the total 45 bits are represented as {C0, C1, C2,..., C44}, possible combinations of 1 and 0 as codes are represented by 8 bits (dk, dk + 1, dk + 2) of data bits. ,..., Dk + 7), the table shown in FIG. 28 is created and decrypted using this table.

  The LLR corresponding to the decoded data bit can be calculated by the following arithmetic expression.

なお、下記の演算式によりＬＬＲを求めることもできる。

Note that the LLR can also be obtained by the following arithmetic expression.

上式中、ｍｍａｘはスライディング・ウィンドウ内のビット数−１である。例えば、（Ｄ８−１５）の場合、前後の各１５ビットをすべて見る場合には、ｍｍａｘ＝４４となる。
なお、前述の通り、前後のコードについては、必ずしも１５ビットをすべて見る必要はない。

In the above equation, mmax is the number of bits in the sliding window minus one. For example, in the case of (D8-15), when all 15 bits before and after are viewed, mmax = 44.
As described above, it is not always necessary to see all 15 bits for the preceding and following codes.

  That is, for the target bit for which LLR is to be calculated, the addition of LLR including the preceding and succeeding codes for the code pattern whose value is 1 (however, the pattern value remains positive where the pattern value is 1). , The code pattern whose value is 0 is added to the LLR including the preceding and succeeding codes (however, the pattern value remains 0 at the place where the pattern value is 1 and the pattern value is 0). Can be indicated by subtraction. By doing this, even with a run-length modulation method such as 8-15 modulation with many patterns, it is possible to calculate a likely likelihood by minimizing the computation time, circuit scale, and memory scale.

  Returning to FIG. 24B again, the run-length decoded signal composed of the main information decoded by the run-length decoding circuit 147 and the converted likelihood information (LLR) is supplied to the deinterleave circuit 148. After being deinterleaved and returned to the original order, the ECC circuit 149 performs error correction or the like and outputs decoded digital information.

  Next, the operating principle of this embodiment will be described. FIG. 29 shows a state in which all bits after the bit slip are shifted due to the bit slip. That is, conventionally, when a bit slip occurs at the SL position after the synchronization signal SY1 is reproduced, all the bits until the next synchronization signal SY2 is detected are shifted to the error range ER1.

  FIG. 30 shows the effect of the present invention. In the present invention, when a bit slip occurs at the position SL after the synchronization signal SY1 is reproduced, the error occurrence position is determined with reference to the position of the synchronization signal SY2 to be reproduced next. Since the bit position after the bit slip is determined by detection, the error range can be significantly narrowed and minimized as compared with the conventional error range ER1, as indicated by ER2. In the case of an error correction method using a long code length such as LDPC, the present invention is effective because it is impossible to correct to a correct value if the bit position is shifted.

  Next, a second embodiment of the recording / reproducing apparatus according to the present invention will be described. FIGS. 31A and 31B are block diagrams showing a recording system and a reproducing system according to the second embodiment of the recording / reproducing apparatus of the present invention. In the figure, the same components as those in FIG. 24 are denoted by the same reference numerals, and the description thereof is omitted. In the recording system shown in FIG. 31A, digital information is supplied to the ECC parity generation circuit 151 and added with parity (RS / LPDC, etc.) and then supplied to the run-length encoding circuit 152. It is converted into a code string (that is, a run-length limited code) subjected to run length restriction / DSV (Digital Sum Variation).

  The run-length limited code output from the run-length encoding circuit 152 is supplied with a parity by the ECC parity generation circuit 153 and supplied to the strategy circuit 154. Here, the laser for modulating the laser based on the run-length code is supplied. It is converted into a high frequency pulse, and the high frequency pulse is supplied to an optical head (not shown) to record digital information on the optical disk.

  In the reproduction system of the present embodiment, as shown in FIG. 31B, the main information, likelihood information, and synchronization timing information output from the synchronization signal detection circuit 146 are the phase error output from the resampling / DPLL 143. At the same time, it is supplied to the data length recovery circuit 156. The data length recovery circuit 156 is configured as shown in the block diagram of FIG. 32, for example.

  In the same figure, the main signal and likelihood information output from the synchronization signal detection circuit 146 are delayed by a delay circuit 1561, and the above phase error is delayed by the delay circuit 1562 to the data length recovery unit 1563, respectively. Supplied. On the other hand, the synchronization signal timing information output from the synchronization signal detection circuit 146 is counted by the counting circuit 1564 based on the clock, and the count result is supplied to the error determination circuit 1565.

  The error determination circuit 1565 compares the reference data length from the reference data length generator 1566 with the count result corresponding to the synchronization signal interval from the counting circuit 1564, and generates data length error information indicating whether they are equal. To the data length recovery unit 1563. The data length recovering unit 1563 extracts the maximum value of the phase error when the absolute value of the phase error exceeds a predetermined threshold, detects slip point information having the position information, and based on the data length error information. When it is determined that the length is not a regular length, the data length is adjusted (interpolated or thinned out) at the position based on the slip point information for the input main signal and likelihood information. , Recover the data length.

  The main signal and likelihood information output from the data length recovery unit 1563 are error-corrected based on the error detection code RS / LDPC or the like by the ECC circuit 157, and then supplied to the run-length decoding circuit 158, where the run-length decoding ( Likelihood-converted) to obtain a run-length decoded signal. This run-length decoded signal is error-corrected by the ECC circuit 159 based on the error detection code RS / LDPC or the like and output.

  The present embodiment is fair in correspondence with the run-length limited ECC parity, but has the same effect as the recording / reproducing apparatus of the first embodiment described with reference to FIG.

  Next, a third embodiment of the recording / reproducing apparatus according to the present invention will be described. FIG. 33 shows a block diagram of the reproducing system of the third embodiment of the recording / reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 24 are denoted by the same reference numerals, and the description thereof is omitted. The third embodiment shown in FIG. 33 is characterized in that a PLL circuit 161 is used in place of the resampling / DPLL 143 used in the reproduction system of the first embodiment shown in FIG. There is.

  In FIG. 33, the output signal of the AGC / ATC circuit 142 is supplied directly to the adaptive equalization circuit 144 and to the PLL circuit 161. The PLL circuit 161 generates a system clock and supplies it to the A / D converter 141, supplies a phase error to the run length decoding circuit 147, and supplies 0 point information to the adaptive equalization circuit 144. This embodiment also has the same features as the embodiments shown in FIGS. 24 and 31, but is characterized by sampling with a synchronous clock.

  Next, a fourth embodiment of the recording / reproducing apparatus according to the present invention will be described. FIG. 34 shows a block diagram of a reproducing system of the fourth embodiment of the recording / reproducing apparatus according to the present invention. In the figure, the same components as those in FIG. 31B are denoted by the same reference numerals, and description thereof is omitted. The fourth embodiment shown in FIG. 34 is characterized in that a PLL circuit 162 is used in place of the resampling / DPLL 143 used in the reproduction system of the second embodiment shown in FIG. There is.

  In FIG. 34, the output signal of the AGC / ATC circuit 142 is directly supplied to the adaptive equalization circuit 144 and is also supplied to the PLL circuit 162. The PLL circuit 162 generates a system clock and supplies it to the A / D converter 141, supplies a phase error to the data length recovery circuit 156, and supplies 0 point information to the adaptive equalization circuit 144. This embodiment also has the same features as the embodiments shown in FIGS. 24, 31 and 33, but is characterized in that sampling is performed with a synchronous clock as in the embodiment of FIG.

  Note that the present invention is not limited to the above embodiment. For example, the data length recovery units 1473 and 1563 do not directly decimate and interpolate signals, but do not interpolate signals already stored in a memory. It is also possible to obtain the same effect as when direct decimation / interpolation is performed by operating the address (pointer). In addition, when the decoding circuit 145 performs soft decision, that is, likelihood information, it may be set to an uncertain value at the time of data length expansion (data interpolation). The adaptive equalization circuit 144 can use the adaptive equalization circuit 20a or 20e, and can further use any one of the configurations of the adaptive equalization circuits 20b to 20d. In the latter case, the 0 point information can be generated inside the adaptive equalization circuits 20b to 20d.

1 is a block diagram of a first embodiment of a playback apparatus of the present invention. 1 is a block diagram of a first embodiment of an adaptive equalization circuit of a main part of a playback apparatus of the present invention. FIG. FIG. 3 is a circuit diagram of an embodiment of a tap delay circuit and a temporary discrimination circuit in FIG. 2. It is explanatory drawing of a partial response characteristic. It is a figure which shows the relationship between the characteristic of PR (a, b, b, b, a), the run length restriction | limiting rule RLL mode, and the temporary determination value of a temporary discriminator. 6 is a flowchart (part 1) for explaining a provisional discrimination process when the RLL mode of the provisional discriminator in FIG. 3 is (1, X). FIG. 6 is a flowchart (part 2) for explaining a provisional discrimination process when the RLL mode of the provisional discriminator in FIG. 3 is (1, X). FIG. 6 is a flowchart (part 1) for explaining a provisional discrimination process when the RLL mode of the provisional discriminator in FIG. 3 is (2, X). FIG. 6 is a flowchart (part 2) for explaining a provisional discrimination process when the RLL mode of the provisional discriminator in FIG. 3 is (2, X). It is a figure (the 1) which shows the example of a waveform before the waveform equalization by this invention and after a waveform equalization. FIG. 6 is a diagram (part 2) illustrating a waveform example before and after waveform equalization according to the present invention. It is a figure which shows an example of the eye pattern of the output signal of the decoding circuit of the reproducing | regenerating apparatus by this invention. It is a figure which shows the other example of the eye pattern of the output signal of the decoding circuit of the reproducing | regenerating apparatus by this invention. It is a block diagram of 2nd Embodiment of the adaptive equalization circuit of the principal part of this invention apparatus. It is a block diagram of 3rd Embodiment of the adaptive equalization circuit of the principal part of this invention apparatus. It is a block diagram of 4th Embodiment of the adaptive equalization circuit of the principal part of this invention apparatus. It is a block diagram of 5th Embodiment of the adaptive equalization circuit of the principal part of this invention apparatus. FIG. 18 is a block diagram of an embodiment of the error selection circuit in FIG. 17. It is a figure which shows the mode of the sample point in case PR is equalized correctly, and the extracted error component. It is a figure which shows the mode of the sample point in case PR is not correctly equalized, and the error component extracted without having an error selection circuit. It is a figure which shows the mode of the sample point in case PR is equalized correctly, and the error component extracted by the error selection circuit of FIG. It is explanatory drawing of the reference value of the state transition of S2-> S4-> S7-> S5, and the reference value of the state transition of S7-> S5-> S2-> S4. It is a block diagram of one embodiment of a temporary discriminator. 1 is a block diagram of a recording system and a reproducing system according to a first embodiment of a recording / reproducing apparatus of the present invention. FIG. 25 is a block diagram of an example of resampling / DPLL in FIG. 24. FIG. 25 is a block diagram of an example of a run length decoding circuit in FIG. 24. It is a figure which shows an example of the table used with the run length decoding circuit of FIG. FIG. 27 is a diagram illustrating another example of a table used in the run-length decoding circuit in FIG. 26. It is a figure explaining the state from which all the bits after bit slip shifted by bit slip. It is a figure explaining the effect of the present invention when bit slip occurs. It is each block diagram of the recording system of the 2nd Embodiment of the recording / reproducing apparatus of this invention, and a reproducing system. FIG. 32 is a block diagram of an example of a data length recovery circuit in FIG. 31. It is a block diagram of the reproducing | regenerating system of 3rd Embodiment of the recording / reproducing apparatus of this invention. It is a block diagram of the reproducing | regenerating system of 4th Embodiment of the recording / reproducing apparatus of this invention. It is a block diagram of an example of the conventional reproducing | regenerating apparatus.

Explanation of symbols

15 Optical disc 19, 143 Resampling / DPLL
20, 20a, 20b, 20c, 20d, 20e, 144 Adaptive equalization circuit 21, 145 Decoding circuit 21 Transversal filter 22 Multiplier and low-pass filter (LPF)
23 Tap delay circuit 24, 100 Temporary discrimination circuit 26, 27 Zero detector 31 Zero cross detector / phase comparator 33, 37 Voltage controlled oscillator (VCO)
35 Phase comparator 51 Temporary discriminator 52 Subtractor 55 Error selection circuit 131 Parity generation circuit for ECC 133, 152 Run-length encoding circuit 146 Synchronization signal detection circuit 147, 158 Run-length decoding circuit 156 Data length recovery circuit 161, 162 PLL Circuit 553 Selection circuit 554, 571 Switch circuit 555, 572 0 generator 1473, 1563 Data length recovery unit 1474, 1564 Count circuit 1475, 1565 Error determination circuit 1476, 1566 Reference data length generator 1477 Run length decoder

Claims (7)

In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
Zero detecting means for detecting a zero cross point from the post-waveform equalized reproduction signal output from the transversal filter and outputting zero point information;
A first delay circuit that sequentially delays the zero point information extracted from the zero detecting means in synchronization with a system clock by one clock at a time and outputs at least four consecutive zero point information;
The waveform-equalized reproduction signal output from the transversal filter is sequentially sampled one clock at a time in synchronization with the system clock, and at least the values of four consecutive sampling points of the waveform-equalized reproduction signal are output. A second delay circuit that
A PR mode signal indicating a type of the partial response equalization; an RLL mode signal indicating a type of a run length limit code of the reproduction signal; a plurality of pieces of the 0-point information from the first delay circuit; And receiving a plurality of sampling point values from the delay circuit as input, state transitions determined by the PR mode signal and the RLL mode signal, a pattern of the plurality of 0-point information, and a target among the plurality of sampling points. Based on the polarity of the value of the sampling point to be calculated, when calculating the temporary discrimination value of the reproduced signal after waveform equalization, the median value in the at least four consecutive 0 point information does not indicate a zero cross point, If the value of 0 point information both before and after the median value indicates a zero cross point, three consecutive bits differing by 1 bit clock period. The sum of the first Euclidean distances obtained by calculating and adding the Euclidean distance corresponding to the reference value series of three consecutive state transitions with respect to the sampling sequence of the reproduced signal after waveform equalization, and similarly having the opposite polarity Corresponding to the reference value series of three consecutive state transitions, the Euclidean distance is calculated and compared with the total sum of the second Euclidean distances, and used to calculate the sum of the Euclidean distances having the smaller value. In addition, the largest reference value in the reference value series is calculated as the temporary determination value, and a difference value between the temporary determination value and the value of the target sampling point output from the second delay circuit is calculated as an error signal. Temporary determination means for outputting as
And a coefficient generation means for variably controlling the tap coefficient of the transversal filter so that the error signal is minimized based on the output error signal of the temporary determination means. In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
Zero detecting means for detecting a zero cross point from the post-waveform equalized reproduction signal output from the transversal filter and outputting zero point information;
A first delay circuit that sequentially delays the zero point information extracted from the zero detecting means in synchronization with a system clock by one clock at a time and outputs at least four consecutive zero point information;
The waveform-equalized reproduction signal output from the transversal filter is sequentially sampled one clock at a time in synchronization with the system clock, and at least the values of four consecutive sampling points of the waveform-equalized reproduction signal are output. A second delay circuit that
A PR mode signal indicating a type of the partial response equalization; an RLL mode signal indicating a type of a run length limit code of the reproduction signal; a plurality of pieces of the 0-point information from the first delay circuit; A plurality of sampling point values from the delay circuit, and the median value in the at least four consecutive zero point information does not indicate a zero cross point, and both zero points before and after the median value When the information value indicates a zero cross point, or the median value in the at least four consecutive zero point information does not indicate a zero cross point, and only the zero point information value after the median value is zero cross Or the median value in the at least four consecutive zero point information indicates a zero cross point, When the value of 0 point information other than the median value does not indicate a zero cross point, the state transition determined by the PR mode signal and the RLL mode signal, the plurality of 0 point information patterns, and the plurality of sampling points Based on the polarity of the value of the sampling point adjacent to the target sampling point, a temporary discrimination value of the reproduced signal after waveform equalization is calculated, and the temporary discrimination value and the target output from the second delay circuit Temporary determination means for outputting a difference value from the sampling point value as an error signal;
And a coefficient generation means for variably controlling the tap coefficient of the transversal filter so that the error signal is minimized based on the output error signal of the temporary determination means.   When the polarity of the waveform equalized reproduction signal output from the transversal filter is inverted, the zero detection means uses, as the 0 point information, a sample point closer to 0 out of two neighboring sample points. 3. The reproducing apparatus according to claim 1, wherein the reproducing apparatus is an output zero detector. Encoding means for generating and encoding parity from input digital information;
Run length limited code generating means for generating a run length limited code by converting n bits (where m <n) for every m bits of the encoded signal output from the encoding means;
Recording means for recording the run length restriction code on a recording medium;
Reproducing means for reproducing the run-length limited code from the recording medium;
A / D conversion means for converting the reproduced run length limited code into a digital reproduction signal;
Phase locked loop means for extracting a phase error from the digital reproduction signal, generating a bit clock by controlling a resampling frequency, and resampling and outputting the digital reproduction signal;
Waveform equalization processing is performed on the digital reproduction signal using a transversal filter on the basis of 0 point information for detecting whether or not the digital reproduction signal is resampled and output from the phase-locked loop means. Adaptive equalization means to perform;
Decoding means for maximum likelihood decoding the reproduction signal output from the adaptive equalization means and outputting digital reproduction data together with likelihood information;
The digital reproduction data is converted into the m bits for every n bits by run length limited decoding corresponding to the run length limited code generation means, and the likelihood information for each input n bits is converted into the m bits for each m bits. Run length decoding means for converting into likelihood information;
Error correction means for performing error correction on the digital reproduction data and likelihood information for each n bits output from the run-length decoding means using parity corresponding to the encoding means. Playback device. In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
A / D conversion means for converting the run length limited code reproduced from the recording medium into a digital reproduction signal including a synchronization signal having a fixed period;
The digital reproduction signal is resampled at a desired bit rate to generate resampling data, a bit clock is generated, a phase error is extracted to control a resampling frequency, and a zero cross point of the digital reproduction signal is generated. Resampling calculation phase locked loop means for detecting whether or not and outputting 0 point information;
Adaptive equalization means for performing waveform equalization processing on the resampling data output from the resampling calculation phase-locked loop means based on the 0-point information using a transversal filter;
Decoding means for maximum likelihood decoding the reproduction signal output from the adaptive equalization means and outputting digital reproduction data together with likelihood information;
Synchronization signal detecting means for extracting the synchronization signal from the digital reproduction data;
A data length error determination unit that counts the interval between two extracted adjacent synchronization signals and outputs data length error information indicating whether the counted synchronization signal interval is equal to a reference data length;
When the absolute value of the phase error supplied from the phase locked loop means exceeds a predetermined threshold value, or the maximum value of the phase error is extracted, slip point information having the position information is detected, and the data length Based on the error information, when it is determined that the length is not a regular length, by adjusting the data length at the position based on the slip point information with respect to the digital reproduction data and the likelihood information, A data length recovery means for recovering the data length;
The digital reproduction data output from the data length recovery means is converted into m bits (where n> m) every n bits by run-length limited decoding, and likelihood information for each input n bits is converted into the above-described likelihood information. and a run-length decoding means for converting the likelihood information into m-bit likelihood information. In a playback device that plays back a run-length limited code recorded on a recording medium, decodes the playback signal after performing partial response equalization using a transversal filter,
A / D conversion means for converting the run length limited code reproduced from the recording medium into a digital reproduction signal including a synchronization signal having a fixed period based on a predetermined clock;
A phase locked loop means for extracting a phase error from the digital reproduction signal and controlling the resampling frequency to generate and output the predetermined clock;
The digital reproduction signal output from the phase-locked loop means is subjected to waveform equalization processing using a transversal filter based on 0 point information obtained by detecting whether the digital reproduction signal is a zero cross point or not. Adaptive equalization means to perform;
Decoding means for maximum likelihood decoding the reproduction signal output from the adaptive equalization means and outputting digital reproduction data together with likelihood information;
Synchronization signal detecting means for extracting the synchronization signal from the digital reproduction data;
A data length error determination unit that counts the interval between two extracted adjacent synchronization signals and outputs data length error information indicating whether the counted synchronization signal interval is equal to a reference data length;
When the absolute value of the phase error supplied from the phase locked loop means exceeds a predetermined threshold value, or the maximum value of the phase error is extracted, slip point information having the position information is detected, and the data length Based on the error information, when it is determined that the length is not a regular length, by adjusting the data length at the position based on the slip point information with respect to the digital reproduction data and the likelihood information, A data length recovery means for recovering the data length;
The digital reproduction data output from the data length recovery means is converted into m bits (where n> m) every n bits by run-length limited decoding, and likelihood information for each input n bits is converted into the above-described likelihood information. and a run-length decoding means for converting the likelihood information into m-bit likelihood information.   The adaptive equalization means includes, in addition to the transversal filter, the first and second delay circuits according to claim 1, the temporary determination means, and the coefficient generation means. Item 7. The playback device according to Item 5 or 6.

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