JP3060884B2 - Automatic equalization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ternary (0, +1,-)
The present invention relates to an automatic equalization circuit of PR (partial response) 4 detection method for detecting 1), and more particularly to an automatic equalization circuit suitable for adaptively equalizing a reproduced waveform of a digital VTR, for example.

[0002]

2. Description of the Related Art FIG. 9 shows an eye pattern after equalization by the PR4 detection method.
It converges to either 0 or -1. However, since the waveform is deviated from the levels of +1, 0, and -1 due to noise and frequency characteristic deviation, the equalizer is optimally calculated by adaptively calculating the amount of correction of the tap coefficient of the equalizer. Maintaining is done.

FIG. 10 shows the principle of a conventional adaptive equalizer for equalizing a binary signal in an analog system.
W. Lucky, The Bell System Technical Journal, Vol. 4
5,) Feb., 1966, pp. 255-268. The input signal (INPUT) is supplied to delay units (T) 21-1 and 21-2 and coefficient units 22 _-1 , 22 ₀ , and 2 of tap coefficients C _-1 , C ₀ , and C _+1.
Waveform interference is reduced by 2 _+1, then the output sampling circuit 23, through a slice circuit 24 as equalized data a _n.

Further, a tap coefficient C_-1, C₀ , C₊₁Adapt
Equalization data a_n Is a D / A converter 25,
Delay unit 21-4 and multiplier 26_-1Feedback
You. And the equalization error e_n Out of the A / D converter 25
Force a_n And the output y of the sampling circuit 23_n Difference (e_n =
y_n -A_n ) Is calculated by the subtractor 30 and the delay unit 21
-3 through the multiplier 26_-1, 26₀ , 26₊₁Applied to
You. Also, the equalization data a n is the delay device 21-4, 21-4
Respectively through the multipliers 26₀ , 26₊₁Is applied to
In such a configuration, the multiplier 26_-1, 26₀ , 26₊₁By
And the restored data sequence {a}_n ｝ And equalization error ｛e_n }of
By multiplication

[0005]

(Equation 1)

Is calculated. Here, k is the number of sampling clocks of 1 or more, and j = -1, 0, +1. Then, the filters 27 _-1 , 27 ₀ , 27 ₊₁ , the slice circuits 28 _-1 , 2
8 ₀ , 28 ₊₁ and sampling circuits 29 ₋₁ , 29 ₀ , 2
If the sign of the multiplication result of the multipliers 26 ₋₁ , 26 ₀ , 26 ₊₁ is positive via 9 _{+ 1} , the coefficient C _i is decreased by Δ, and if negative, the tap coefficient C _i is increased by Δ. This process is repeated many times to obtain a desired tap coefficient _Cj . In recent years, such calculations are generally performed by digital calculations.

[0007]

However, when the above-mentioned conventional equalizer is processed by digital operation,
As the bit rate increases, there is a problem that high-speed digital operation must be performed and the cost increases. Also,
Since the PR4 detection method detects ternary values (0, +1, -1), the use of analog multipliers as the multipliers 26 _-1 , 26 ₀ , 26 ₊₁ complicates the adjustment.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a PR4 detection type automatic equalizing circuit having a simple configuration.

[0009]

According to the present invention, in order to achieve the above object, an equivalent error amount is detected by an analog comparison circuit and taken out as a binary decision signal, and a restored data sequence of 0, +1, -1 is obtained. A simple logic circuit calculates the multiplication of a binary discrimination signal and the equivalent error amount to output two logic outputs, and controls the tap coefficient of the equalizer based on the average value of the analogs of the two logic outputs. I am trying to do it.

That is, according to the present invention, three values (0, +
An equalizer for equalizing a ternary (0, +1, -1) analog signal with a variable tap coefficient in an automatic equalization circuit of a partial response 4-detection method for detecting (1, -1); A first discriminating circuit for discriminating 0, +1, -1 of the signal equalized by the equalizer, and comparing the signal equalized by the equalizer with 0, +1, -1 to obtain a binary Three second determination circuits for outputting a determination signal;
, One of the binary determination signals determined by the determination circuit is selected, the signal is multiplied by the time-series signal determined by the first determination circuit, and the multiplication result is output as two logic outputs. An automatic equalization circuit is provided, comprising: a multiplication circuit; and tap coefficient control means for controlling a tap coefficient of the equalizer based on an average value of two logic outputs output by the multiplication means. You.

According to the present invention, ternary values (0, +1,-
In an automatic equalization circuit of a partial response 4 detection method for detecting 1), an equalizer for equalizing a ternary (0, +1, -1) analog signal with a variable tap coefficient, and an equalizer using the equalizer A first discriminating circuit for discriminating 0, +1 and -1 of the equalized signal, and a signal equalized by the equalizer and 0
, A second discriminating circuit that outputs a binary discriminating signal, a detecting circuit that takes out the larger of the signal equalized by the equalizer and its inverted signal, and a signal that is taken out by the detecting circuit. And +1, and a third discriminating circuit for outputting a binary discriminating signal and one of the binary discriminating signals discriminated by the second and third discriminating circuits are selected. A multiplying circuit that multiplies the time-series signal determined by the first determining circuit and outputs the result of the multiplication as two logic outputs; and a multiplying circuit based on an average value of the two logic outputs output by the multiplying means. And tap coefficient control means for controlling a tap coefficient of the equalizer.

[0012]

According to the present invention, the equivalent error amount is detected by an analog comparison circuit and taken out as a binary discrimination signal.
The multiplication of the restored data sequence of -1 and the binary decision signal of the equivalent error is calculated by a simple logic circuit and output as two logic outputs. Based on the average value of the analogs of the two logic outputs, the equalizer is used. Since the tap coefficients are controlled, the configuration can be made inexpensively even when the bit rate is high. Further, since the multiplication logic of the detection result of the restored data sequence and the equivalent error amount is multiplication of 0, +1, and -1, it can be realized with a small number of gates, and complicated adjustment is not required.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. Figure 1 is a block diagram showing an embodiment of an automatic equalization circuit according to the present invention, FIG. 2 is a block diagram showing in detail the data extraction / equalization error detection block of FIG. 1, FIG. 3 is the equalization error e _k and FIG. 4 is an explanatory diagram showing the relationship between the data a _kj and e _k · a _kj after equalization, and FIG. 4 is an explanatory diagram showing the operation of the selector in FIG.

In FIG. 1, magnetic information recorded on a magnetic tape T is reproduced by a reproducing head 1 into an analog electric signal. The analog electric signal is amplified by a head amplifier 2 and then transmitted to a three-tap transversal filter 3. Applied. This filter 3 includes delay units DL ₁ and DL ₂
When the tap coefficients C _-1, C _0, C ₊₁ coefficient unit 3 _-1, 3 _0,
3 ₊₁ and an adder 4, and each input signal at the current sampling point, before and after the current sampling point is set to a tap coefficient C
_-1, to reduce waveform interference by weighting by C _0, C _+1. The output signal of the filter 3 is so-called "1 + D" process by the adder 5 and the delay circuit DL _3, the signal y after equalization
_n is applied to the comparators C1 to C5.

The comparators C1 to C5 also have reference values v _{1 to} v ₅ as examples, respectively.

[0016]

## EQU2 ## v ₁ = + 0.5 v ₂ = −0.5 v ₃ = + 1 v ₄ = 0 v ₅ = −1

Is applied. Comparators C1, C
2 each equalizer output y _n and the reference value v ₁ (= + 0.
5), by comparing v ₂ (= −0.5), the signal y
It is determined whether _n is 1, 0, or −1, and a determination signal a
^+, A ^- to output. in this case,

[0018]

## EQU3 ## For ^{_{y n = 1, a + =}} 1, a - = 0 For ^{_{y n = 0, a + =}} 0, a - = For ^{_{0 y n = -1, a +}} = 0, a ^- = 1

## EQU1 ## Further, the signals a ⁺ and a ^- are PL
The clock cloc is applied to the L circuit 6 and is applied by the PLL circuit 6.
k is generated.

Further, in order to detect an equalization error,
The equalizer output yn has a reference value v_Three (= 1)
It is determined whether it is larger or smaller (the determination signal e₊₁) Also, Compare
Data C4 is equalizer output y_n Is the reference value v_Four Greater than (= 0)
Is smaller or smaller (determination signal e₀ ), The comparator C5 is an equalizer
Output y_n Is the reference value v_Five Judge whether it is larger or smaller than (= -1)
(Judgment signal e_-1). And data extraction / equalization error
As shown in detail in FIG.
Each output a of the data C1 to C5⁺ , A^- , E₊₁, E 0, e_-1
And data based on the clock clock from the PLL circuit 6.
Ta_n Out of the ideal equalized waveform
And detects six types of tap coefficient correction signals CT₊₁, CT
₀ , CT_-1, CN₊₁, CN₀ , CN_-1Is output.

Then, this signal (CT₊₁, CN₊₁),
(CT₀ , CN₀ ), (CT_-1, CN -₁) Each analog
The addition value is calculated by the addition circuit 8₊₁, 8₀ , 8_-1Calculated by
And averaged, and based on the respective average values, the buffer 9
₊₁, 9₀ , 9_-1Through the tap coefficient C₊₁, C
₀ , C_-1Is adapted.

Next, referring to FIG. 2, data extraction / etc.
The conversion error detection block 7 will be described in detail. First,
Output a of comparator C1⁺ Is a DFF (flip-flop)
) 701 (output AP)₊₁), DFF702 (same AP)₀ )
And DFF703 (AP_-1) Through the OR gate
704 and the output a of the comparator C2. -
Is DFF711 (the same AN₊₁), DFF712 (same AN
₀ ) And DFF713 (the same AN_-1OR)
Port 704. And the OR gate 704
The output signal is the output data a of this equalization circuit._n Output as
It is.

The outputs AP ₊₁ , AP ₀ , AP _-1 and DFFs 711-713 of the DFFs 701-703, respectively.
Each output of the AN _+1, AN _0, AN _-1 is applied to the selector 750. Further, the output e _{+ 1 of the} comparator C3 is DF
The outputs e _{0 of the} comparator C4 are output from the DFFs 731 and 732 (E ₀ ) via F721 and 722 (E ₊₁ ).
Via the output e _-1 of the comparator C5 is DFF74
_1, 742 (the same E ₋₁ ) is applied to the selector 750. Selector 750 determines AP ₊₁ , AP
₀ , AP _-1 , AN ₊₁ , AN ₀ , AN _-1 and E ₊₁ , E ₀ , E
_-1 are multiplied, and six types of signals (CT
₊₁ , CN ₊₁ ), (CT ₀ , CN ₀ ), (CT _-1 , C
N _-1 ).

[0024] The selector 750 is configured to calculate e _k · a _k- j by data strings {a _n} and equalization error {e _n}. Here, the PR4 detection method uses three values (0,
+ 1, and detects -1), the equalizer output y _n

[0025]

Equation 4] y _n> 0.5, -0.5> a in the case of _{y n n = 1 -0.5 <a} n = 0 in the case of y _n <0.5

The correspondence is as follows. Therefore, y _n be the data a _n is "1" because both cases when the positive and negative are present, it must be calculated e _k · a _kj to distinguish between the two.

Since only the sign needs to be considered for e _k, it can be considered as +1 if 1 and -1 if 0. Therefore, e _k · a _kj can be represented by as shown in FIG. 3 and takes three values of 1, 0, and −1. This is 2
When corresponding to the analog addition of two logic outputs CT and CN,

[0028]

When e _k · a _kj = 1 CT = CN = 1, (CT + CN) / 2 = 1 When e _k · a _kj = 0 CT = 1, CN = 0, (CT + CN) / 2 = 1 / 2 e _k · a _kj = If CT = CN = 0 -1, a (CT + CN) / 2 = 0.

For example, e_k ・ A_k Will be described. Equalization
Error e_k As shown in FIG.₊₁, E 0, E_-1Using
Data a_k As AP₀ , AN₀ , The data AP
₀ , AN₀ The combination of

[0030]

(1) AP ₀ = 1 (2) AP ₀ = AN ₀ = 0 (3) AN ₀ = 1

(1) When AP ₀ = 1 Since the equalizer output y ₀ should have been near “+1”, E _{+ 1} is selected as the error signal. In this case, if y ₀ is larger than the desired level (larger as the PP value), then E ₊₁ = + 1. At this time, it is shown in FIG.

[0032]

E _k = 1, a _kj = 1, y _kj > 0.5

In response to the above, CT ₀ = CN ₀ = 1 is output. Conversely, if y ₀ is less than the desired level, E ₊₁ = 0
In this case, as shown in FIG.

[0034]

## _EQU00008 ## Corresponding to e _k = -1, a _kj = 1, y _kj > 0.5, and outputs CT ₀ = CN ₀ = 0.

[0035]

(2) When AP ₀ = AN ₀ = 0 Since y ₀ = 0 as described above, CT = 1 and CN =
Set to 0. This e _k = -1 shown in FIG. 3, corresponds to _{a kj = 0 e k = 1} , a kj = 0. (3) When AN ₀ = 1 Since the equalizer output y ₀ should have been near “−1”, E− ₁ is selected as the error signal. In this case, if y ₀ is larger than “−1” (that is, smaller than the PP value), E ₋₁ = 1, and at this time, CT ₀ = CN ₀ =
0 is output (corresponding to e _k = 1, a _kj = 1, y _kj <0.5 shown in FIG. 3). Conversely, y ₀ is smaller than “−1” (that is, P−
If the P value is large), CT ₀ = 1 and CN ₀ = 0
(E _k = -1, a _kj = 1, y _kj <0.5 shown in FIG. 3). Therefore, if the PP _value of y ₀ is larger than ± 1, CT ₀ = CN ₀ = 1 is output, while if the PP _value of y ₀ is smaller than ± 1, CT ₀ = CN _0. = 0 is output, and the tap coefficient C ₀ is adaptively controlled based on the analog added value of CT ₀ and CN ₀ .

[0036]

Next, the case of e _k · a _{k + 1} will be described. First, as e _k , (1) if AP ₀ = 1, then E _{+ 1} ; (2) if AP ₀ = AN ₀ = 0. E ₀ (3) If AN ₀ = 1, use E ₋₁ . Also, AP ₊₁ and AN ₊₁ are used as a _{k +1} . In this case, CT ₊₁ and CN ₊₁ are (1) AP ₊₁ = 1, _ek = 1, CT ₊₁ = CN ₊₁ = 1 (2) AP ₊₁ = 1, _ek = 0, CT ₊₁ = CN ₊₁ = 0 (3) AN ₊₁ = 1, _ek = 1, CT ₊₁ = CN ₊₁ = 0 (4 ) AN ₊₁ = 1, _ek = 0, CT ₊₁ = CN ₊₁ = 1 (5) AP ₊₁ = AN ₊₁ = 0, _ek = 0,1, CT ₊₁ =
1, CN ₊₁ = 0.

Next, the case of e _k · a _k−1 will be described. Except that AP ₋₁ and AN ₋₁ are used as a _k−1 ,
CT _-1 and CN _-1 are output as in the case of _k · a _{k + 1} .
To summarize the above processing, the CT and CN selected by the selector 750 and the long time-averaged, the tap coefficients C ₊₁ with the results, the C _0, C _-1 is adapted.

[0038]

In the embodiment shown in FIG. 1, when the inverted signal is represented by (/), (1) (/) (CT ₀ + CN ₀ ) is larger than 1/2 → C ₀
(2) (/) (CT ₀ + CN ₀ ) is smaller than 1/2 → C ₀
(3) (/) (CT ₊₁ + CN ₊₁ ) is larger than 1/2 → C ₊₁
(4) (/) (CT ₊₁ + CN ₊₁ ) is smaller than 1/2 → C ₊₁
(5) (/) (CT _-1 + CN _-1 ) is larger than 1/2 → C _-1
(6) (/) (CT _-1 + CN _-1 ) is smaller than 1/2 → C ₊₁
Is controlled so as to reduce the optimal tap coefficient C ₊₁ ,
C ₀ and C ₋₁ are obtained.

Next, a second embodiment will be described with reference to FIGS. FIG. 5 is a block diagram showing only the tap coefficient adaptation circuit of the second embodiment, FIG. 6 is a circuit diagram showing the MAX circuit of FIG. 5 in detail, and FIG.
FIG. 8 is a block diagram showing the equalization error detection block in detail, and FIG. 8 is an explanatory diagram showing the operation of the selector of FIG.

As shown in FIG. 5, in this second embodiment,
The comparator C5 shown in FIG. 1 is omitted. And
Instead rotation signal from the equalizer output y _n by the amplifier 11 to y _n and the inverted signal (/) y _n are obtained, then the forward signal y _n and the inverted signal by the MAX circuit 12 as shown in detail in FIG. 6 (/) of y _n, the larger the signal | y _n | is obtained, the signal | y _n | is v by the comparator C4
₃ = + 1 is compared. Here, this signal | y _n |
Since the eye pattern shown in FIG. 9 is turned from the 0 level in the positive direction, both the deviation from +1 and the deviation from -1 are detected by the comparator C4 (the determination signal e _{(+1, -1)).} ), So that it is substantially equivalent to the circuit shown in FIG.

In the data extraction / equalization error detection block 7a shown in detail in FIG. 7, first, the output a ^{+ of the} comparator C1 is changed to a DFF (flip-flop) 701 (output AP), as in the first embodiment shown in FIG. ₊₁ ), DFF702
(AP ₀ ) and DFF 703 (AP _-1 ).
Is applied to the R gate 704, also the output of the comparator C2 a _- is DFF711 (same AN _+1), DFF712
(AN ₀ ) and DFF 713 (AN _-1 ).
Is applied to the R gate 704, the output signal of the OR gate 704 is output as output data a _n of the equalizer.

The outputs AP ₊₁ , AP ₀ , AP _-1 and DFFs 711-713 of these DFFs 701-703, respectively.
Each output AN ₊₁ of, AN _0, AN _-1, but is applied to the selector 750. In the second embodiment, the output e _{0 of the} comparator C3 is output via the DFFs 731 and 732 (the same E ₀ ), and the output e _{(+1, -1) of the} comparator C4 is output from the DFF 731 and 732.
The signal is applied to the selector 750a via the FFs 751 and 752 (the same E _{(+1, -1)} ).

In such a configuration, the selector 750a
Multiplication as shown in FIG. 8 is performed. Differences from the first embodiment
Just to explain, e_k ・ A_kj Is calculated as AN₀ = 1 or
Is AP₀ = 1 when E_{(+ 1, -1)} , But E
_{(+ 1, -1)} Are opposite in polarity. Note that in FIG.
Signal e obtained by inverting the output of the_-1And its forward rotation signal e
+₁Is the same as the operation of the first embodiment.

[0044]

As described above, according to the present invention, the equivalent error amount is detected by the analog comparison circuit and extracted as a binary discrimination signal, and the restored data sequence of 0, +1, -1 and the equivalent error amount are obtained. By calculating the multiplication of the binary determination result by a simple logic circuit and outputting as two logic outputs, and controlling the tap coefficients of the equalizer based on the average value of the analogs of the two logic outputs, PR with a simple structure
It is possible to realize a four-detection automatic equalizing circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an automatic equalization circuit according to the present invention.

FIG. 2 is a block diagram showing a data extraction / equalization error detection block of FIG. 1 in detail.

FIG. 3 shows an equalization error e _k and data a _kj and e _k after equalization.
It is explanatory drawing which shows the relationship of _akj .

FIG. 4 is an explanatory diagram showing an operation of the selector of FIG. 2;

FIG. 5 is a block diagram illustrating a tap coefficient adaptation circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing a MAX circuit of FIG. 5 in detail;

FIG. 7 is a block diagram showing a data extraction / equalization error detection block of FIG. 6 in detail.

FIG. 8 is an explanatory diagram showing an operation of the selector of FIG. 7;

FIG. 9 is an explanatory diagram showing an eye pattern after equalization by the PR4 detection method.

FIG. 10 is a block diagram illustrating an example of a conventional automatic equalization circuit.

[Explanation of symbols]

C _-1 , C ₀ , C ₊₁ Tap coefficient 3 Transversal filter (coefficient units 3 _-1 , 3 ₀ , 3
_+1, constituting the equalizer with the adder 5 and the delay circuit _{DL 1 ~DL 3) 3 -1,} 3 0, 3 +1 coefficient multiplier 4,5 adder DL ₁ through DL ₃ delayer C1, C2 comparator (first determination circuit) C3-C5 comparator (second determination circuit) 7, 7a data extracted / equalization error detection block (multiplier circuit) 8 _+1, 8 _0, 8 _-1 adder circuit (buffer 9 ₊₁ , 9 ₀ , 9
Constituting the tap coefficient control means with the tap coefficient control means with _-1) 9 _+1, 9 _0, 9 _-1 constitute a detection circuit with a buffer 11 amplifier (MAX circuit 12) 12 MAX circuit C3 comparator (second determination Circuit) C4 comparator (third discriminating circuit)

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 25/00 H04B 3/00 H03H 21/00

Claims (2)

(57) [Claims] An automatic equalization circuit of a partial response 4-detection method for detecting a ternary (0, +1, -1), wherein an analog signal of a ternary (0, +1, -1) is equalized by a variable tap coefficient. An equalizer to be equalized; a first determination circuit for determining 0, +1, -1 of the signal equalized by the equalizer; and a signal equalized by the equalizer to 0, +1,- 1 and each of the three second signals for outputting a binary discrimination signal.
Multiplying each of the binary judgment signals judged by the three second judgment circuits by the time-series signal judged by the first judgment circuit, and outputs the multiplication result to two logic outputs And a tap coefficient control means for controlling a tap coefficient of the equalizer based on an average value of two logic outputs outputted by the multiplication means. circuit. 2. An automatic equalization circuit of a partial response 4-detection method for detecting a ternary (0, +1, -1), wherein an analog signal of a ternary (0, +1, -1) is equalized by a variable tap coefficient. An equalizer to be equalized, a first determination circuit for determining 0, +1, -1 of the signal equalized by the equalizer, and comparing the signal equalized by the equalizer with 0, A second discrimination circuit that outputs a binary discrimination signal, a detection circuit that takes out the larger of the signal equalized by the equalizer and its inverted signal, and a signal that is taken out by the detection circuit and compares +1 And
A third determination circuit that outputs a binary determination signal, each of the binary determination signals determined by the second and third determination circuits, and a time-series signal determined by the first determination circuit And a tap coefficient control means for controlling a tap coefficient of the equalizer based on an average value of the two logic outputs outputted by the multiplication means. An automatic equalizing circuit, comprising: