JP3428355B2 - Waveform equalization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizing circuit suitable for a digital information signal recording / reproducing apparatus, in which the coefficient convergence is delayed due to the characteristics of the reproduced signal or the judgment error increases so that the coefficient The present invention relates to a waveform equalization circuit that prevents divergence.

[0002]

2. Description of the Related Art The basic structure of a transversal type filter which has been used as a waveform equalization circuit has been that an estimation control unit automatically controls the tap coefficient of a delay element having a delay between taps equal to a signal period. Met. Since the above filter is a non-recursive type, it is basically stable.

There is a magnetic recording / reproducing apparatus for recording / reproducing a digital information signal by the partial response method, which uses a waveform equalizing circuit composed of the above-mentioned transversal filter. At this time, in the above filter, in order to suppress intersymbol interference of the reproduced digital information signal, the filter is adapted using an error component of the signal amplitude compared with the estimated value (three values) obtained by the tentative determination. The output of is converted into a binary digital data sequence obtained by a Viterbi decoding circuit or a determination circuit (not shown), and then processed such as error correction.

In the above-mentioned transversal filter, temporary discrimination means for discriminating the reproduced digital information signal, error calculation means for outputting an amplitude error based on the temporary discrimination result, and signal value output by the transversal filter. Holding selection means for holding and selecting, and an update for updating the tap coefficient of the transversal filter based on the result of multiplication of the amplitude error output by the temporary discrimination means and the signal value output by the holding selection means. Means for obtaining a reliable information signal without converging the reproduced digital information signal to an erroneous value, whereby the coefficient convergence slows down or the judgment error increases in accordance with the characteristics of the reproduced signal. The present applicant has proposed a waveform equalization circuit (Japanese Patent Application No. 8-307411) that prevents the coefficient from diverging due to

As shown in FIG. 3, the above-mentioned waveform equalization circuit uses a transversal type filter. For example, for each output obtained by inputting a digital information signal through a plurality of delay circuits, , Predetermined tap coefficients are multiplied and added and synthesized. At this time, for example, of the plurality of delay circuits 11 to 14 constituting the above filter, the place where the energy of the signal waveform is the highest is taken as the center and the delayed outputs before and after that are multiplied by a predetermined coefficient, respectively, and an adder is added.
Add and synthesize at 20. Since the waveforms multiplied by the predetermined coefficient are weighted and combined in this manner, the influence of intersymbol interference generated in the digital information signal waveform during transmission is suppressed.

In the case of the filter of FIG. 3, when the output of the delay circuit 12 is the center, the tap coefficient supplied to the multipliers 15 to 19 is the largest supplied to the multiplier 17, and the multipliers before and after the tap coefficient are the largest. The coefficients supplied to 16 and 18 are a little smaller than that, and the coefficients supplied to the multipliers 15 and 19 are set to be smaller, so that intersymbol interference before and after the signal waveform of the center is suppressed.

[0007]

However, among the output signals of the plurality of delay circuits 11 to 14 on the filter circuit,
Since which signal is the center is not defined,
There is a problem that the output of the adder 20 diverges due to the shift of the center of the signal waveform due to the characteristics of the signal supplied to this filter or the influence of random noise.

FIG. 4A shows LPFs 36-40 of the above filter.
Shows that the values of the tap coefficients generated in each of the transitions in a predetermined sample period (for example, a random noise is input within a predetermined period and then a digital information signal via a magnetic recording / reproducing system is input as a reproducing signal). . Figure 4 (B)
Shows the transition of the tap coefficient in the steady state when the reproduction signal is input. Further, FIG. 4C shows a sample of the output signal when the waveform equalization is performed by the tap coefficient that transits as shown in FIG. 4B (that is, in the steady state). In addition, in FIG. 4, in order to relatively represent the change in the tap coefficient,
Output each of LPF38 and two predetermined LPFs from 0 to 128
Expressed with a sample, the other two LPF outputs are 192 (-6
4) to 256 (0) samples. The horizontal axis of each figure shows the time history of sampling, and is referred to as the sampling period here.

As shown in FIG. 4B, while the tap coefficient at the center does not become so large after the reproduction signal is input, the other tap coefficients increase at random and the waveform equalization processing converges. The state which cannot be shown is shown. For this reason, the figure (C) shows that the value of the reproduction signal (the above-mentioned three values (“−1”, “0”, “1”, etc.)) is not detected.

At this time, the low-pass filters (LPF) 36 to 40 for generating the tap coefficients supplied to the multipliers 15 to 19 are provided with limiters of a predetermined level to forcibly multiply the multipliers 15 and 16 or the multiplier 18. It is conceivable to suppress the coefficient supplied to each of the signals 19 and 19 to prevent the output signal from diverging due to the deviation of the center of the signal waveform. But in that case, LPF36
Since the coefficient value of ~ 40 is limited, there is a problem that the range that can be corrected is limited. That is, for example, it becomes difficult to converge to a correct information signal value for a signal having various fluctuation components such as a reproduced digital information signal of a digital VTR, or it takes a long time to converge, and the operation is performed. There is an inconvenience that it is not stable.

[0011]

Therefore, the present invention provides the following configurations (1) to (3) in order to solve the above-mentioned problems. That is, (1) In the first invention, the delayed output of the transmitted digital information signal is weighted and added by multiplication by a plurality of tap coefficients that are adaptively controlled, respectively. In a waveform equalization circuit using a transversal filter that suppresses interference,
There is provided a waveform equalization circuit characterized by comprising a calculation means for calculating a control signal for controlling another tap coefficient based on a predetermined tap coefficient among the plurality of tap coefficients. .

(2) In the second invention, the delayed output of the transmitted digital information signal is weighted and added by multiplication by a plurality of tap coefficients adaptively controlled, respectively, to add the sign of the digital information signal. In a waveform equalization circuit using a transversal filter (A) that suppresses inter-interference, a temporary discrimination circuit (B that temporarily discriminates the most probable digital information from the output of the transversal filter (A) by maximum likelihood detection (B ), An error calculation circuit (C) that outputs a value corresponding to an amplitude error based on this, a holding selection circuit (D) that holds and selects the digital information signal and its delay signal, respectively, and the error calculation circuit ( The amplitude error output from (C) is multiplied by the signal value output from the holding selection circuit (D) means, and the tap coefficient of the transversal filter is updated based on the result. Update means (31-40)
And a calculation circuit (41) for calculating a control signal for controlling another tap coefficient based on a predetermined tap coefficient among the plurality of tap coefficients described above. Is provided.

(3) A third invention provides the arithmetic circuit (41).
Is characterized in that, with respect to the value of the predetermined tap coefficient, a limiter value of another tap coefficient is calculated at a rate set according to the characteristics of the information signal to be waveform equalized or the characteristics of the signal processing circuit. The waveform equalizing circuit according to (1) or (2) above is provided.

[0014]

1 is a block diagram for explaining a waveform equalizing circuit of the present invention, and FIG. 2 is a diagram for explaining the operation of the waveform equalizing circuit. An embodiment of the present invention will be described below with reference to the drawings. Further, the same components as those described above are designated by the same reference numerals, and the description thereof will be omitted.

The waveform equalization circuit of the present invention discriminates the value of a likely digital information signal by using the above-mentioned maximum likelihood detection algorithm and performs waveform equalization. As shown in FIG. 1, for example, as described above, the magnetic head H
Supplies the reproduction signal obtained by scanning the magnetic tape T to the waveform equalizing circuit A of the present invention through the preamplifier 1, the filter 2, the A / D converter 3, the DC removing circuit 4 and the like.

The waveform equalizing circuit A of the present invention comprises delay circuits 11 to 14 for sequentially delaying the supplied reproduction signal by a predetermined amount, and a delay circuit.
A holding selection circuit D for holding the respective delayed outputs of 11 to 14, a reproduction signal and the respective delayed outputs of the delay circuits 11 to 14 to a multiplier 15
To adder 20 for adding through, and a provisional determination circuit B for determining a digital signal value from the output of the adder 20, a provisional determination circuit B
The error calculation circuit C that outputs the amplitude error between the expected value and the actual signal based on the tentative discrimination result from the above, and the signal value held by the above-mentioned hold selection circuit D and the amplitude error from the error calculation circuit C are multiplied. The outputs of the multipliers 31 to 35 and the multipliers 31 to 35 are integrated to output low-frequency components, and the LPFs 36 to 40 and LPF 38 to be supplied to the multipliers 15 to 19 are LP based on the outputs.
It is composed of a calculation circuit 41 for calculating limiter values set in F36, 37, 39, and 40, respectively.

The waveform equalizing circuit A is the arithmetic circuit described above for the transversal type filter shown in FIG.
41 will be added. Although not shown here, a delay element for absorbing the delay caused in the amplitude error due to the signal processing is provided between the reproduction signal and its delayed output and the holding selection circuit D as described above.

The adder 20 supplies the output information signal to the provisional discrimination circuit B together with a transmission line (not shown). The transmission line (not shown) is composed of a digital signal processing circuit, etc., the output of this transversal filter is judged to be a digital signal, the judged digital signal is subjected to error correction, deshuffling, etc. Information such as video and audio included in the digital information signal is restored.

On the other hand, the transversal filter output from the adder 20 is supplied to the provisional discrimination circuit B. The temporary discrimination circuit B as the temporary discrimination means compares the supplied information signal with the threshold value determined by the past sampling value,
Any one of "1", "0", and "-1" is provisionally determined. Then, a switching control signal is generated based on the result of the tentative determination and is supplied to the error calculation circuit C. The error calculation circuit C is composed of, for example, a three-system level determination circuit, a subtractor, and a latch circuit, which are not shown individually. Either the output of the latch circuit or the output of the subtractor is switched and output based on the control signal.

By the way, the provisional discrimination circuit B uses the output signal of the adder 20, for example, a multi-valued digital information signal ("-
1 "," 0 "," 1 ") are discriminated, and a switching signal corresponding to them is supplied to the error calculation circuit C and a control signal is supplied to the hold selection circuit D, respectively. The error calculation circuit C calculates and holds the amplitude error of the value of the digital information signal described above with respect to the signal from the adder 20 from the ideal value. Then, the error signals held based on the switching signal from the temporary discrimination circuit B are supplied to the multipliers 31 to 35, respectively.

The temporary discrimination circuit B described above is, for example,
As described in Japanese Patent Application No. 8-307411 proposed by the present applicant, the most probable digital information signal value is tentatively discriminated by discrimination applying an algorithm of maximum likelihood detection, and the discriminated value is obtained. A switching signal is supplied to the error calculation circuit C so as to output a corresponding error signal.

As described above, in the level judgment circuit constituting the error calculation circuit C, ideal signal level values of "1", "0", "-1" of the digital information signal to be reproduced are set. Therefore, this level and the level of the supplied signal are subjected to subtraction processing by a subtracter (not shown). The obtained difference is used as the value of the error level and is latched by the above-mentioned latch circuit in accordance with the timing of a predetermined sampling clock. The output of the latch circuit is supplied to a changeover switch (not shown), and is switched and output based on the changeover signal from the temporary discrimination circuit B.

On the other hand, the reproduction signal supplied to the waveform equalization circuit A is supplied to the hold selection circuit D via the delay circuits 11-14. Although not shown here, the hold selection circuit D is composed of a plurality of systems of latch circuits and changeover switches.
For example, the reproduction signal is supplied to the latch circuit and the changeover switch, and the operation thereof is controlled by the above-mentioned temporary discrimination circuit B, respectively. The latch circuit that constitutes the hold selection circuit D is output in synchronization with the output of the latch circuit of the error calculation circuit C.
When the error signal is passed through in the error calculation circuit C, the signal similarly supplied to the hold selection circuit D is output through.

For example, when a digital information signal is passed through a partial response type magnetic recording / reproducing system, a value "1" or "-1" is not continuously detected in the reproduced signal due to intersymbol interference. This is because the digital information signal is obtained through the transmission characteristic of (1-D) ² , and if this property is used, for example, when the value of “1” or “−1” is continuous, it is most reliable. "1" or "-"
When the value of "1" is detected, the other value can be regarded as noise, so that the amplitude error of the signal made noise at that time can be output through.

The reproduction signal and delay circuits 11 to 14 described above are provided.
As described above, it is assumed that the output signal from is supplied to the hold selection circuit D via a delay element (not shown) in order to absorb the delay error with the amplitude error caused by the signal delay.

When the error level value of the digital information signal is output from the error calculation circuit C, the signal held by the latch circuit that latches the signal value of the corresponding waveform based on the control signal from the temporary discrimination circuit B. Is output, and at the same time, the changeover switch supplies the signal to the multipliers 31 to 35. The multipliers 31 to 35 multiply the signal from the hold selection circuit D by the error level value from the error calculation circuit C, and the result is LPF36.
Supply ~ 40. The LPFs 36 to 40 integrate the supplied signals and output low frequency components, which are fed back to the multipliers 15 to 19 as tap coefficients.

The LPF 38 supplies the output coefficient value to the arithmetic circuit 41. The arithmetic circuit 41 supplies signals for controlling the tap coefficients before and after the tap coefficient from the LPF 38 to the LPF 36, 37, 39, 40, respectively. For example, in the arithmetic circuit 41, if the LPF that obtains a coefficient that maximizes the energy of the signal waveform is the LPF 38, the absolute value of the tap coefficient obtained by the LPFs 36, 37, 39, 40 is the LPF 38 based on the value of this LPF. Outputs a control signal that is set to a value that does not exceed the absolute value of the coefficient.

For example, the coefficients output from the LPFs 36, 37, 39, 40 are set at a predetermined ratio (1/2, to the absolute value of the output of the LPF 38).
2/3, 3/5, ..., etc. are arbitrarily set in consideration of the characteristics of the signal to be equalized, the characteristics of the signal processing circuit, etc.). The coefficient limiter range of each LPF is not set to a fixed value, so that the LP can be adjusted according to the tap coefficient of the center signal waveform.
Since the coefficients of F36, 37, 39, 40 are controlled, the tap coefficient is always required so as to suppress the intersymbol interference component of the signal waveform of the center.

As shown in FIG. 2, when random noise is input to the waveform equalizing circuit and then a reproduction signal is supplied, a predetermined center tap coefficient (in this case, the tap coefficient output from the LPF 38) rises first. Therefore, it can be seen that each tap coefficient has converged. Therefore, as shown in (C) of FIG.
It can be seen that digital information of the value has been obtained. Incidentally, FIG.
(A) and (B) are the same as in FIG.
The value of the tap coefficient generated in each of 36 to 40 was changed in a predetermined sample period (for example, a random noise is input within a predetermined period and then a digital information signal via a magnetic recording / reproducing system is input as a reproducing signal). Figure 2 shows the situation
FIG. 2C shows a sample of the output signal when the tap coefficient converges in the steady state as shown in FIG. 2B and the waveform equalization is performed by the tap coefficient. Further, in FIG. 2, similarly to FIG. 4,
In order to express the change of the tap coefficient relatively, the output of each of the LPF 38 and the predetermined two LPFs is represented by 0 to 128 samples, and the outputs of the other two LPFs are represented by 192 (-64) to 256 (0) samples. It represents.

The multipliers 15 to 19 reproduce the reproduction digital weighted by the tap coefficient updated by the operation of the multiplication result of the error level value and the signal value output from the hold selection circuit D and the delayed output of the reproduction digital information signal. Since the information signal can be obtained, the information signal output from the adder 20 is equalized into a more reliable waveform. That is, FIG. 2 (C)
As shown in, the above-mentioned ternary digital information signals ("1", "0", "-1") were detected at different levels.

In this way, in the present waveform equalizing circuit A, the discriminating means B discriminates the value of the reproduced digital information signal and detects how much the value has an error with respect to the predetermined level, and the detection result By multiplying the value output by the holding / selecting circuit D, it is possible to discriminate the value of the likely digital information signal and the noise and perform waveform equalization of the reproduced digital information signal.

Here, the timing at which the amplitude error is output changes depending on the input signal, but since the LPFs 36 to 40 carry out a sufficiently long integration process, there is no problem even if the data is decided in clock units. Also, it is difficult to determine everything completely in the initial stage of the convergence process,
By making many stochastic correct decisions, the coefficient data of the waveform equalization converges toward the correct values, so that it is possible to prevent the divergence of the data.

In this way, by discriminating the reproduced digital information signal from the recording / reproducing apparatus such as the digital VTR, the reproduced digital information signal is likely to converge the waveform equalization quickly and to widen the convergence range. The effect is that you can do it. Further, since the present waveform equalization circuit can be composed almost entirely of digital circuits, there is almost no variation in characteristics and there is an effect that stable operation can be secured.

In the above-mentioned waveform equalizing circuit, the tap coefficient from the LPF 38 is used as the center to control the tap coefficients of the LPFs before and after the center, so that the characteristics of the LPFs 36 to 40 are L.
Although it has been described that the center of PF38 is symmetrical, depending on the characteristics of the information signal for which waveform equalization should be performed, this center may be set to LP.
Of course, each tap coefficient may be controlled so as to be asymmetric from F38.

In the above-mentioned waveform equalization circuit, it has been described that the tap coefficient of the waveform equalization circuit provided with the temporary discrimination circuit using the maximum likelihood detection algorithm is controlled.
Needless to say, the above-described tap coefficient control may be performed in a conventional transversal filter that makes this provisional determination by comparison with a predetermined threshold value.

It is needless to say that the waveform equalization circuit may be used in combination with the above-described prefilter including the equalizer for adjustment to perform more accurate waveform equalization. . At that time, as mentioned above,
Of course, the tap coefficient of this pre-filter may be automatically determined using the tap coefficient of the present waveform equalization circuit.

The waveform equalizing circuit is premised on waveform equalization of a signal reproduced in a recording / reproducing apparatus for recording / reproducing a digital information signal such as a digital VTR. The medium is not limited as long as it uses the above transmission path, and it goes without saying that it may be used for a recording / reproducing device of a digital disk, a communication modem, a signal transmitting / receiving device such as a ghost canceller, and the like.

Of course, the waveform equalization circuit may be used in combination with, for example, the Viterbi decoding circuit described above to obtain a more reliable reproduced digital information signal.

There is a waveform equalizing circuit using a transversal type filter that uses a zero-forcing algorithm, which is the same as that of the above-described embodiment. The output is not operated as the input signal (by the way, the least square error algorithm is used in the present embodiment), and the tap coefficient of the input signal is controlled only by the output signal. The configuration for calculating the output of the waveform equalization circuit with the input signal for the equalization circuit can be omitted.
Since the value logic operation is used, the configuration can be simplified. Therefore, for example, the determination means B described above is used for this zero =
It is needless to say that the forcing waveform equalizing circuit may be used to realize a waveform equalizing circuit having a simpler configuration.

However, this zero = forcing waveform equalization circuit has a convergence condition, and tap coefficient control is performed only from the output signal, so that a reproduction digital information signal from a digital VTR or the like has a large jitter. On the other hand, the signal value may diverge. Therefore, it can be said to be useful in communication devices such as digital information signal transmitting / receiving devices.

In this waveform equalizing circuit, the signal operation of the transversal filter such as the multiplier for updating the tap coefficient based on the error level of the reproduced digital information signal is
Since the conventional configuration can be used, the arithmetic control of the entire waveform equalization circuit is not more complicated than the conventional one.

The transversal type filter described in the embodiments of the present invention constitutes a negative feedback loop, and an inverter for inverting the output from the error calculation circuit C, though not shown here. It goes without saying that it is provided with a reversing means such as.

[0043]

According to the present invention, the tentative discriminating means for discriminating the reproduced digital information signal, the error calculating means for outputting the amplitude error based on the tentative discriminating result, and the signal value output by the transversal type filter are provided. Holding selection means for holding and selecting, and an update for updating the tap coefficient of the transversal filter based on the result of multiplication of the amplitude error output by the temporary discrimination means and the signal value output by the holding selection means. By means of adaptively controlling each tap coefficient on the basis of a predetermined tap coefficient, the updating means can suppress intersymbol interference with respect to the signal waveform serving as the center, and achieve stable convergence. There is an effect that a transversal filter that operates can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a waveform equalization circuit of the present invention.

FIG. 2 is a diagram for explaining the operation of the present waveform equalization circuit.

FIG. 3 is a block diagram for explaining a conventional transversal filter.

FIG. 4 is a diagram for explaining the operation of a conventional transversal filter.

[Explanation of symbols]

A ... Waveform equalization circuit, B ... Temporary discrimination means (temporary discrimination circuit), C
... holding selection means (holding selection circuit), 31-40, updating means (multipliers 31-35, LPF36-40), 41 ... arithmetic means (arithmetic circuit).

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-9-245436 (JP, A) JP-A-9-320198 (JP, A) JP-A-8-46553 (JP, A) JP-A-7- 302467 (JP, A) JP-A-9-97476 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11B 20/10 H03H 21/00 H04B 3/06 H03H 15/00

Claims (3)

(57) [Claims] 1. A transversal device for suppressing intersymbol interference of a digital information signal by weighting and adding delayed outputs of the transmitted digital information signal by multiplication by a plurality of tap coefficients adaptively controlled, respectively. In a waveform equalization circuit using a type filter, a calculation means for calculating a control signal for controlling another tap coefficient based on a predetermined tap coefficient among the plurality of tap coefficients is provided. Waveform equalizer circuit. 2. A transversal for suppressing intersymbol interference of the digital information signal by weighting and adding the delayed outputs of the transmitted digital information signal by multiplication by a plurality of tap coefficients adaptively controlled, respectively. In a waveform equalization circuit using a type filter, a tentative discriminating means for tentatively discriminating the most probable digital information from the output of the transversal type filter by maximum likelihood detection, and an error for outputting a value according to an amplitude error based on the tentative discriminating means. The calculation means, the holding selection means for holding and selecting the digital information signal and the delayed signal thereof, the amplitude error output from the error calculation means and the signal value output from the holding selection means are multiplied, and the result is obtained. Updating means for updating the tap coefficient of the transversal filter based on the above; Within a few, waveform equalizing circuit, characterized in that it includes a calculation Dedan for calculating a control signal for controlling the other tap coefficients based on the predetermined tap coefficients. 3. The limiter value of another tap coefficient at a rate set according to the characteristics of the information signal to be waveform equalized or the characteristics of the signal processing circuit with respect to the value of the predetermined tap coefficient. The waveform equalization circuit according to claim 1 or 2, wherein