JP3428359B2 - Waveform equalization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizing circuit suitable for a digital information signal recording / reproducing apparatus, in which the coefficient convergence is delayed depending on the characteristics of the reproduced signal.
The present invention relates to a waveform equalization circuit that prevents a coefficient from diverging due to an increase in decision errors.

[0002]

2. Description of the Related Art A transversal filter has been used as a waveform equalizing circuit for a transmitted digital information signal. The basic configuration of this filter is such that the estimation control unit automatically controls the tap coefficient of a delay element having a delay between taps equal to the signal period. Since the above filter is a non-recursive type, it is basically stable.

In the above-mentioned transversal filter, temporary discrimination means for discriminating the reproduced digital information signal, error calculation means for outputting an amplitude error based on the temporary discrimination result, and signal value output by the transversal filter. Holding selection means for holding and selecting, and an update for updating the tap coefficient of the transversal filter based on the result of multiplication of the amplitude error output by the temporary discrimination means and the signal value output by the holding selection means. Means for obtaining a reliable information signal without converging the reproduced digital information signal to an erroneous value, whereby the coefficient convergence slows down or the judgment error increases in accordance with the characteristics of the reproduced signal. The present applicant has proposed a waveform equalization circuit (Japanese Patent Application No. 8-307411) that prevents the coefficient from diverging due to

By the way, as a device for recording / reproducing a digital information signal, for example, there is a digital VTR to which the structure of a helical scan type VTR is applied. As is well known, in a helical scan type VTR, a continuous signal to be recorded is divided into a plurality of channels and recorded while forming a predetermined track pattern on a magnetic tape. Switching signals are output to reproduce continuous signals. In a VTR that obtains a reproduction signal from a plurality of magnetic heads mounted on a rotary drum around which a magnetic tape is wound in this manner, a reproduction signal dropout,
Alternatively, a noise bar or the like may occur during high-speed playback of the VTR, and the playback signal level may drop to increase noise.

When an information signal is reproduced by such a digital VTR, the waveform equalization of the reproduced signal may not be performed well due to the dropout of the reproduced signal and the generation of noise bars during high-speed reproduction.

[0006]

When the level of the reproduced signal drops and noise increases, the S / N ratio of the signal deteriorates. Therefore, if the waveform equalization circuit performs the waveform equalization process, However, there is a problem that the noise of the reproduced signal is further increased.

Further, at this time, the processing operation of waveform equalization of the reproduced signal is not stable, the coefficient of the waveform equalization is diverged, and the erroneous detection of the digital information of the reproduced signal is induced, which is great for the reproduction of the digital data. There was the problem of becoming an obstacle.
Therefore, the emergence of a waveform equalization circuit that is not affected by changes in the level of reproduced signals and S / N has been desired.

[0008]

In order to solve the above-mentioned problems, the present invention has the following waveforms (1) to (3).
To provide a digitalization circuit .

(1) According to a first aspect of the present invention, the delayed output of the transmitted digital information signal is weighted and added by multiplication by a plurality of tap coefficients which are each adaptively controlled, and this digital output is added. In a waveform equalization circuit using a transversal filter that suppresses intersymbol interference of information signals, a temporary discrimination means (temporary discrimination circuit) for temporarily discriminating the most probable digital information from the output of the transversal filter by maximum likelihood detection. ) (B),
Error calculation means (calculation error circuit) (C) for outputting a value according to the amplitude error based on this, and holding selection means (hold selection circuit) (D) for holding and selecting the digital information signal and its delayed signal, respectively. And the amplitude error output from the error calculation circuit (C) and the signal value output from the hold selection circuit (D),
Updating means (switching circuits 21 to 26, multiplier 31) for updating the tap coefficient of the transversal filter based on the result.
〜35, LPF36〜40) and updating means (21〜26,31)
40 to 40) provide a waveform equalization circuit characterized by interrupting the update of the tap coefficient based on a threshold value set at a predetermined ratio and holding the coefficient at that time.

(2) A second invention is the updating means (21
26, 31 to 40) update the tap coefficient if the level of the transmitted digital information signal is larger than the threshold value, and interrupt the update of the tap coefficient when the level becomes smaller than the threshold value. There is provided a waveform equalization circuit according to the above (1), which holds the coefficient at the time.

(3) The third invention is characterized in that the digital information signal is a digital information signal obtained by alternately reproducing data of a plurality of channels divided and recorded on a tape-shaped recording medium. (1) or the waveform equalization circuit described in (2) above is provided.

[0012]

1 is a block diagram for explaining a waveform equalizing circuit of the present invention, FIG. 2 is a block diagram for explaining a detecting means which is an essential part of the present invention, and FIG. 3 is a diagram of the waveform equalizing circuit of the present invention. FIG. 4 is a diagram illustrating an embodiment, FIG. 4 is a diagram illustrating a switching circuit according to another embodiment of the present invention, and FIG. 5 is a diagram illustrating an LPF according to another embodiment of the present invention. An embodiment of the present invention will be described below with reference to the drawings. Further, the same components as those described above are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 1, a magnetic head H mounted on a rotary drum (not shown) (for example, magnetic heads having at least different azimuth angles are mounted on the drum at positions opposite to each other by 180 °). A preamplifier 1 that amplifies a signal obtained by scanning the magnetic tape T, a detection circuit 6 that detects the level of the output signal 1a of the preamplifier 1, and an AGC circuit 2 that automatically adjusts the gain of the output signal 1a of the preamplifier 1. , A filter 3 for removing the noise component of the output signal of the AGC circuit 2, an A / D for sampling the output signal of the filter 3 and converting it into a digital signal
Waveform for equalizing the waveform of the output signal 5a of the DC removing circuit 5 based on the detection result 6a of the converter 4, the DC removing circuit 5 for setting the DC level of the output signal of the A / D converter 4, and the detecting circuit 6 And an analog circuit A.

A plurality of the magnetic heads H described above are mounted on a rotating drum, and continuous reproduction signals are obtained by switching and outputting the signals reproduced by the individual heads according to the rotation of the drum. is there.

In the detection circuit 6 described above, for example, when the rotary head scans across different azimuth tracks on the magnetic tape during the special reproduction of the VTR, the level of the reproduction signal obtained from the head fluctuates. Alternatively, when the reproduction signal level fluctuates due to reproduction signal dropout or the like, this is detected. In addition, the detection circuit 6
2 is a detection circuit 6 for detecting the peak envelope of the reproduction signal 1a amplified by the preamplifier 1 as shown in FIG.
1. A setting circuit 62 that sets a threshold value according to the detection result of the detection circuit 61, and a comparator that compares the level of the threshold value set by the setting circuit 62 with the reproduction signal 1a from the preamplifier 1.
And a detection circuit 6 for detecting the comparison result of the comparator 63.
Is supplied to the above-mentioned waveform equalizing circuit A as the detection result 6a.

When the detection circuit 61 detects the peak level of the reproduction signal 1a, the setting circuit 62 sets, for example, a half level of the peak level as a threshold value.
The set threshold value is supplied to the comparator 63, and the level of the reproduction signal 1a from the preamplifier 1 is compared with this threshold value. That is, for example, in this case, when the reproduction signal becomes equal to or lower than 1/2 level with respect to the peak level, the comparator 63 outputs a pulsed signal as a detection result.
The threshold value is not limited to the half level of the peak level, and it goes without saying that it may be adaptively set within a range in which the reproduction signal and the noise can be distinguished and detected.

The waveform equalizing circuit A has the following structure as shown in FIG.
A delay circuit 11 for sequentially delaying the supplied reproduction signal 5a by a predetermined amount.
.About.14, a holding selection circuit D for holding the respective delayed outputs of the delay circuits 11 to 14, an adder 20 for adding the respective delayed outputs of the reproduction signal 5a and the delay circuits 11 to 14 via the multipliers 15 to 19, A temporary discrimination circuit B for discriminating a digital signal value from the output of the adder 20, an error calculation circuit C for outputting an amplitude error between an expected value and an actual signal based on the temporary discrimination result from the temporary discrimination circuit B,
The output of the error calculation circuit C and the signal of a predetermined "0" level are switched and output based on the detection result 6a from the detection circuit 6 described above, which is held by the switching circuit 21, the switching circuit 21 and the holding selection circuit D described above. It is composed of multipliers 31 to 35 for multiplying with signal values, and LPFs 36 to 40 for integrating the outputs of the multipliers 31 to 35 to output low frequency components and supplying them to the above multipliers 15 to 19. The calculators 15 to 19 output the LPFs 36 to 40 and the delay circuit 11
The result of multiplication with the outputs of ˜14 is supplied to the adder 20. Incidentally, L
The output of PF36-40 is also called a tap coefficient.

Although not shown here, in the waveform equalization circuit A, the reproduced signal, its delayed output, and the hold selection circuit D are used.
A delay element for absorbing a delay caused by an amplitude error due to signal processing is provided between and.

The adder 20 uses the output information signal as a reproduced digital signal together with a transmission line (not shown) and the temporary discrimination circuit B.
Supply to. A transmission line (not shown) is composed of a digital signal processing circuit, etc., and performs binary determination of the digital signal from the output of the waveform equalization circuit A, performs error correction of the determined digital signal, reproduction processing such as deshuffling, Information such as video and audio included in the reproduced digital information signal is restored.

On the other hand, the output from the adder 20 is the temporary discrimination circuit B.
Is supplied to. The provisional determination circuit B as the provisional determination means compares the supplied information signal with a threshold value determined by the past sampling value, and provisionally determines that it is any one of "+1", "0", and "-1". . Then, a switching control signal is generated based on the result of the tentative determination and is supplied to the error calculation circuit C. The error calculation circuit C is composed of, for example, a three-system level determination circuit, a subtractor, and a latch circuit, which are not shown here. Either the output of the latch circuit or the output of the subtractor is switched and output based on the control signal.

Here, the tentative discrimination circuit B uses the output signal of the adder 20, for example, a multi-valued digital information signal ("-
1 "," 0 "," 1 ") are discriminated, and a switching signal corresponding to them is supplied to the error calculation circuit C and a control signal is supplied to the hold selection circuit D, respectively. The error calculation circuit C calculates and holds the amplitude error of the value of the digital information signal described above with respect to the signal from the adder 20 from the ideal value. Then, the error signals held based on the switching signal from the temporary discrimination circuit B are supplied to the multipliers 31 to 35, respectively.

The provisional discrimination circuit B is a digital information signal most likely to be obtained by discrimination applying the maximum likelihood detection algorithm as described in, for example, Japanese Patent Application No. 8-307411 proposed by the present applicant. The value of is temporarily determined and a switching signal is supplied to the error calculation circuit C so as to output an error signal according to the determined value.

For example, when the digital information signal passes through the magnetic recording / reproducing system of the partial response system, the value "1" or "-1" is not continuously detected in the reproduced signal due to intersymbol interference. This is because the digital information signal is obtained via the transmission characteristic of (1-D) ² , and according to this property, when the value of “1” or “−1” is continuous, it is most likely “ When the value of "1" or "-1" is detected, the other value can be regarded as noise. Therefore, the amplitude error of the signal made noise can be output through.

Here, in the level judgment circuit which constitutes the above-mentioned error calculation circuit C, ideal signal level values of "1", "0" and "-1" of the digital information signal to be reproduced are set respectively. Therefore, this level and the level of the signal supplied from the adder 20 are subjected to subtraction processing by a subtracter (not shown). The obtained difference is used as an error level (amplitude error) value and latched by a latch circuit (not shown) in accordance with a predetermined sampling clock timing. The output of the latch circuit is supplied to a changeover switch (not shown), and is switched and output based on the changeover signal from the temporary discrimination circuit B.

On the other hand, the reproduction signal supplied to the waveform equalizing circuit A is supplied to the hold selection circuit D via the delay circuits 11-14. Although not shown here, the hold selection circuit D is composed of a plurality of systems of latch circuits and changeover switches. For example, the reproduction signal is supplied to the latch circuit and the changeover switch, and the operation thereof is controlled by the above-mentioned temporary discrimination circuit B, respectively. The latch circuit that constitutes the hold selection circuit D is output in synchronization with the output of the latch circuit of the error calculation circuit C.
When the error signal is passed through in the error calculation circuit C, the signal similarly supplied to the hold selection circuit D is output through.

The reproduced signal 5a and the delay circuits 11 to
As described above, the output signal from 14 is supplied to the holding selection circuit D via a delay element (not shown) in order to absorb the delay error with the amplitude error caused by the signal delay.

When the error level value of the digital information signal is output from the error calculation circuit C, the signal held by the latch circuit which latches the signal value of the corresponding waveform based on the control signal from the temporary discrimination circuit B. Is output, and at the same time, the changeover switch supplies the signal to the changeover circuit 21.

The switching circuit 21 is provided with an a-side terminal to which the error signal from the error calculation circuit C is supplied according to the detection result 6a of the detection circuit 6 and a digital information signal to be reproduced as described above. And the b-side terminal to which a signal having an ideal level of "0" is supplied is switched and connected to each of the supplied signals to the multipliers 31 to 35. That is,
When the reproduction signal level becomes 1/2 or less of the peak level, a pulse signal is output from the detection circuit 6 as the detection result 6a, and on the basis of this, the b-side terminal of the switching circuit 21 is switched and connected, and the "0" level Signal is output.

At this time, the multipliers 31-35 multiply the signal of the digital information signal having the ideal level of "0" by the signal from the hold selection circuit D, and the result is LPF36-.
Supply to 40. The LPFs 36 to 40 integrate the supplied signals and output low frequency components, which are fed back to the multipliers 15 to 19 as tap coefficients.

Since the outputs of the multipliers 31 to 35 described above are obtained by multiplying the signal from the hold selection circuit D by the "0" level of the digital information signal, the outputs of the LPFs 36 to 40 do not change at all. That is, the tap coefficient output from the LPF does not change from the coefficient value immediately before the reproduction signal becomes 1/2 or less of the peak level. Therefore, even if the level of the reproduced signal drops extremely to 1/2 of the peak level, the tap coefficient for waveform equalization does not change following this, and the waveform equalization circuit tries to follow the noise level. It is possible to prevent a malfunction.

The reproduction signal level is 1 / the peak level.
When the number exceeds 2, the switching circuit 21 switches and connects the a-side terminal, so that the error signal from the error calculation circuit C is supplied to the multipliers 31 to 35 and the normal operation is resumed.

For example, as shown in FIG. 4, instead of the switching circuit 21 described above, for example, multipliers 31 to 35 and an LPF are used.
It goes without saying that the switching circuits 22 to 26 may be provided between 36 and 40, respectively. Whether to use the switching circuit 21 or the switching circuits 22 to 26 may be selected based on the characteristics of the system when the above-described waveform equalizing circuit is configured and design items.

Further, instead of the switching circuits 21, 22 to 26 described above, for example, LPFs 36 to 40 may be constructed as shown in FIG. In the figure, the LPF36 is described as an example.
It goes without saying that 37 to 40 are similarly configured. LPF36
Is composed of an adder 51 for adding the multiplication result from the multiplier 35 and the main LPF output, a limiter 52 for controlling the level of the output of the adder 51, and a latch circuit 53 for latching the output of the limiter 52.

In normal operation, the LPF 36 has a multiplier
A tap coefficient is obtained by integrating the multiplication result from 35 and is supplied to the multiplier 15. The timing of the signal to be supplied to the adder 51 is adjusted by the latch circuit 53. As described above, when the level of the reproduction signal becomes lower than the threshold value, the detection circuit 6 outputs the pulsed signal 6a as the detection result.

The latch circuit 53 detects the detection result from the detection circuit 6.
The output of the limiter 52 is latched based on 6a and the tap coefficient is held. That is, when the detection circuit 6 detects that the level of the reproduction signal 1a becomes equal to or lower than a predetermined threshold value, the signal value held in the latch circuit 53 is supplied to the multipliers 15 to 19 as tap coefficients.

In this way, when the reproduction signal level becomes smaller than the predetermined threshold value due to dropout or special reproduction, the detection circuit 6 detects it and the value of the tap coefficient is held accordingly. It is possible to prevent the waveform equalization operation from following the level of the reproduction signal 1a and causing a malfunction.

Since the present waveform equalization circuit can be constructed almost entirely of digital circuits, there is almost no variation in characteristics, and stable operation can be ensured. Further, it is needless to say that the waveform equalization circuit may be used in combination with a prefilter including the above-described equalizer for adjustment to perform more accurate waveform equalization. At that time, of course, as described above, the tap coefficient of the pre-filter may be automatically determined using the tap coefficient of the present waveform equalization circuit.

The waveform equalizing circuit is a recording / reproducing device for recording / reproducing a digital information signal on a magnetic tape wound on a rotating drum by a magnetic head mounted on the rotating drum like a digital VTR. Although it is premised that the waveform of the signal reproduced by the apparatus is equalized, if the level of the supplied digital information signal is unstable, the waveform equalization is not limited to the information signal from the digital VTR. Of course, it is also possible to prevent malfunction of the waveform equalization circuit due to the circuit being used to follow a rapid level change of the information signal.

In this waveform equalizing circuit, the signal calculation of the transversal type filter such as the multiplier for updating the tap coefficient based on the error level of the reproduced digital information signal is performed as follows.
Since the conventional configuration can be used, the arithmetic control of the entire waveform equalization circuit is not more complicated than the conventional one.

[0040]

According to the present invention, even if the level of the digital information signal is unstable, the tap coefficient of the information signal at a predetermined level can be held, so that the level of the information signal changes abruptly. There is an effect that it is possible to prevent the waveform equalization circuit from following and cause a malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a waveform equalization circuit of the present invention.

FIG. 2 is a block diagram illustrating a detection unit that is a main part of the present invention.

FIG. 3 is a diagram illustrating an embodiment of the present waveform equalization circuit.

FIG. 4 is a diagram illustrating a switching circuit according to another embodiment of the present invention.

FIG. 5 is a diagram illustrating an LPF according to another embodiment of the present invention.

[Explanation of symbols]

A ... Waveform equalization circuit, B ... Temporary discrimination circuit (temporary discrimination means), C
... Hold selection circuit (hold selection means) 21 to 26, 31 to
40 ... Updating means (switching circuits 21 to 26, multipliers 31 to 35, LP
F36-40).

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 H03H 21/00 H04B 3/06 H03H 15/00

Claims (3)

(57) [Claims] 1. The inter-code interference of the digital information signal is added to the transmitted digital information signal by weighting and adding the delayed output by multiplication by a plurality of tap coefficients adaptively controlled. In a waveform equalization circuit using a transversal filter for suppressing, a temporary discrimination means for temporarily discriminating the most probable digital information from the output of the transversal filter by maximum likelihood detection, and a value corresponding to an amplitude error based on this Error holding means for holding and selecting the digital information signal and its delayed signal, and an amplitude error output from the error calculating means and a signal value output from the hold selecting means. , Update means for updating the tap coefficient of the transversal filter based on the result, Updating means interrupts the updating of the tap coefficients on the basis of the threshold set at a prescribed ratio, waveform equalizing circuit, characterized in that for holding the coefficients of the time. 2. The updating means updates the tap coefficient if the level of the transmitted digital information signal is larger than the threshold value, and interrupts the update of the tap coefficient when the level becomes smaller than the threshold value, The waveform equalizing circuit according to claim 1, wherein the coefficient at that time is held. Wherein the digital information signal, according to claim 1 or 2, wherein the waveform, characterized in that a digital information signal obtained by reproducing the data of a plurality of channels divided recorded on the tape-shaped recording medium alternately Equalization circuit.