KR0147121B1 - Equalizer - Google Patents

Abstract

The present invention relates to an equalization circuit for effectively eliminating signal-to-signal interference by performing signal equalization, determination, and mode control separately from coefficient operations.

The present invention has the following advantages by separately performing equalization, determination, and mode control of signal and counting operations.

First, more coefficients can be updated with the same training sequence, allowing the MSE to use the minimum coefficient. In other words, a smaller number of training sequences is sufficient to obtain coefficients with the same MSE.

Second, when the burst error occurs on the channel while operating in the D.D mode, and the MSE suddenly increases, the training mode can be operated again with the value stored in the received training string storage memory.

Third, when the MSE needs to operate in the training mode because the cursor is large, but the training sequence cannot be found, an effective coefficient update can be performed by operating in the training mode using the training sequence of the previous track stored in the received training sequence storage memory.

Description

Equalization circuit

1 is a block diagram showing a filter coefficient calculating circuit using a rhythm, knowing a typical Least Mean Square error (LMS).

2 is a block diagram showing an embodiment of a general signal reproduction circuit.

3 is a detailed block diagram of the crystal feedback equalizer of FIG.

4 is a view showing an example of using the training train according to FIG.

5 is an overall block diagram of an equalization circuit according to the present invention.

6 is a detailed block diagram of FIG.

7 is a view showing an example of using the training train according to FIG.

* Explanation of symbols for main parts of the drawings

100: analog to digital converter 200: clock generator

500: Equalizer 600: Receive training string storage memory

700: equalization, determination and mode control unit 701,801: forward filter

702,802: Feedback filter 703,803: Subtractor

704: Decision unit 705,805: Training train storage memory

706,806: Multiplexer 707,807: Subtractor

708: mode control unit 800: coefficient calculating unit

808 coefficient operator 804 two-level slicer

The present invention relates to an equalization circuit for eliminating inter-signal interference, and more particularly, to an equalization circuit for effectively eliminating inter-signal interference by performing signal equalization, determination, and mode control separately from coefficient operations.

In general, magnetic tape channels have some kind of differential channel characteristics. Recording a digital signal on an ideal differential channel results in spike-like impulses when transitioning from the signal, i.e., from signal '0' to '1' or from signal '1' to '0' due to the derivative do.

However, in the actual channel, it has a Lorentz pulse shape having a constant value width due to transition slope, rotary transformer (R / T), continuity of magnetization, etc. of the recording signal itself.

At this time, the half width, which is a pulse width (PW) at a half amplitude of the pulse amplitude, is defined as a characteristic of a pulse and expressed as PW50.

As the signal becomes denser, the signal bit period becomes smaller than the PW50, and thus, inter-signal interference occurs as a more serious problem.

A representative cause of the reproduction signal error in the magnetic tape channel is distortion due to inter-signal interference.

This inter-signal interference has a serious effect on the reproduction signal error because it is closely related to the original signal, unlike the random nature of the noise.

Equalizers are used to remove such inter-signal interference. Unnecessary attempts to reduce inter-signal interference cause an increase in noise, and thus, an effective equalizer is required.

In addition, when the channel characteristics change due to various factors, such as mechanical incompleteness or a change in tape characteristics, such as a magnetic tape channel, an adaptive equalizer that can be proportionally followed is required.

At this time, the signal used to effectively remove the inter-signal interference is a training sequence. When recording a signal on a tape, a portion is allocated and recorded, and then when the signal is reproduced, the characteristics of the interference between the signals are determined based on the training sequence. It will eliminate the interference.

Here, the usable training sequence may include sine waves (Sinx / x), chirps, and pseudo random signals, which are signals having all frequency components.

In addition, the most important operation for removing interference between signals is to obtain filter coefficients. The method of obtaining filter coefficients includes least mean square error (LMS), zero-forcing (ZF), and frequency division. There are a variety of methods, including the Frequency-Division (FD) algorithm.

In this case, the LMS algorithm is the most basic algorithm of the adaptive filter, and the filter continuously adjusts the coefficient of the filter in a direction in which the mean square error between the desired signal and the output of the adaptive filter is minimum.

FIG. 1 is a block diagram of a general filter coefficient calculating circuit using an LMS algorithm with simple calculation and a good convergence characteristic, and is a finite impulse response (FIR) for filtering a reproduction signal x (n) in which interference between signals occurs. Filter 101, an Infinite Impulse Response (IIR) filter 102 for filtering the output signal y (n) from which the inter-signal interference has been removed, the output of the FIR filter 101 and the IIR 102 The filter output y (n) is determined by using a subtractor 103 which obtains the output difference of the filter and removes the interference between signals, and the output of the subtractor 103 using a 2 level slicer or the like. The decision unit 104 for feeding back the determined filter output y (n) to the IIR filter 102, and the output y (n) of the decision unit 104 in the training sequence d (n) without interference between signals of the receiver. Subtracter 105 to obtain the error e (n) and the error e (n) of the subtractor 105. Counting the error value is iteratively modify the orientation coefficient of the FIR filter 101 and IIR filter 102 in the reduced consists of a section 106.

Here, the FIR filter 101 is a filter representing an output by a linear combination of input data and its past values. The FIR filter 101 shows an impact response having a finite length in the time axis, and the IIR filter 102 outputs the input data. And a filter that appears as a linear combination of past values of the past and past values of the output, whose impact response is infinite in length in view of the time axis.

When the reproduction signal x (n) having the inter-signal interference in the above-described FIG. 1 passes through the FIR filter 101 and the IIR filter 102 and the difference between the two filters 101 and 102 is obtained by the subtractor 103, the inter-signal interference occurs. The canceled signal is obtained. When the signal from which the inter-signal interference is removed in the subtractor 103 passes through the determining unit 104 such as a two-level slicer, the filter output y (n) is obtained.

On the other hand, the subtractor 105 obtains an error e (n) between the training string d (n) and the filter output y (n) without interference between signals, which the receiver has, and outputs it to the coefficient corrector 106, and the number of coefficients. The step 106 obtains a coefficient in a direction in which the error value decreases and repeatedly modifies the coefficients of the FIR filter 101 and the IIR filter 102.

In terms of this, the filter output y (n) is

At this time, the difference between the training string d (n) and the filter output y (n) in the receiver is as follows, and is obtained by the subtractor 105 and outputted to the coefficient corrector 106.

e (n) = d (n) -y (n)

The coefficient corrector 106 modifies the coefficient ak (n) of the FIR filter 101 and the coefficient bk (n) of the IIR filter 102 as follows.

a _k (n + 1) = a _k (n) + 2μe (n) x (nk), 0≤k≤L

b _k (n + 1) = b _k (n) +2 μe (n) y (nk), 1 ≦ _k ≦ M

Where μ is a constant for stably modifying the filter coefficients, and a _k (n) and b _k (n) are L taps FIR filters a _k (n) and M IIR filters, respectively, in the nth time sample. b is the k-th tap coefficient of _k (n).

FIG. 2 is a general block diagram showing an embodiment of a signal reproducing circuit, in which an analog / digital converter (A) for converting a reproducing signal Vin into digital is shown.

DC), a clock generator 200 which generates a clock synchronized with the input reproduction signal Vin and provides it to the ADC 100, and interference between signals present in the digitally converted reproduction signal Xin. It consists of an equalizer 300 to remove the.

At this time, the equalizer 300 has various forms, and FIG. 3 is a detailed block diagram of the crystal feedback equalizer of the various forms of equalizer.

Referring to FIG. 3, inter-symbol interference between precursor signals

A forward filter 301 for removing the ISI part, a post filter (302) for removing the Postcursor ISI part (Backward or Feedback), and a feedback filter at the output of the previous filter 301. the signal and the cross-cuts the signal from the reproduced signal to output interference removed signal f ₁ (n), a subtracter 303 for outputting, the interference between signals from the subtractor 303 to remove the (302), f ₁ (n ) Is a two-level signal so that the determination unit 304 is a two-level slicer that determines the final data compared to the reference level, and the training sequence storage memory 305 stores the training sequence without interference between signals reproduced on the tape channel. And a multiplexer 306 that selects and outputs the output of the determination unit 304 or the training sequence storage memory 305 according to the mode signal s and feeds it back to the feedback filter 302 to obtain an error. Compute the output of the subtractor 303 and the output of the multiplexer 306 to the error e (n A subtractor 307 for calculating the coefficient and the coefficient calculator 308 for updating the coefficients of the previous filter 301 and the feedback filter 302 so that the new coefficient is calculated so that the error e (n) obtained by the subtractor 307 is minimized. ) And a mode control unit 309 which determines an operation mode according to the error e (n) and outputs a mode selection signal s to the multiplexer 306.

At this time, the pre-filter 301 and the feedback filter 302 is composed of a FIR filter.

In addition, the coefficient calculator 308 uses an LMS algorithm that satisfies a Mean Square Error (MSE) standard rather than a ZF Criterion to improve the performance of the decision feedback equalizer, and the mode controller 309. Is a training mode for fast convergence of the MSE at the beginning of equalization, and operates in Decision Direct (DD) mode when the MSE becomes small.

In FIG. 3 configured as above, the pre-filter 301 removes the precursor ISI portion of the reproduction signal, and the feedback filter 302 removes the post-cursor ISI portion of the reproduction signal.

The subtractor 303 subtracts the output of the feedback filter 302 from the output of the previous filter 301 to obtain an output signal f ₁ (n) from which the inter-signal interference has been removed from the reproduction signal. Output to (307).

In this case, since the output signal f ₁ (n) from which the inter-signal interference is removed from the reproduced signal is a two-level signal, the determination unit 304 restores the desired signal using the two-level slicer.

At this time, the mode control unit 309 operates in the training mode to quickly converge the MSE at the beginning of the equalization, and operates in the D.D mode when the MSE becomes small.

Here, the training mode is to obtain the error signal e (n) as the difference between the training sequence stored in the training sequence storage memory 306 and the output signal f ₁ (n) from which the interference between the signals is removed, and the DD mode is the error signal e ( n) is obtained as the difference between the value finally determined by the determination unit 304 and the output signal f ₁ (n) from which the interference between signals is removed.

Therefore, the multiplexer 306 selects the training sequence stored in the training sequence storage memory 305 under the control of the mode controller 309 at the beginning of equalization, and when the MSE becomes small, the multiplexer 306 determines the determination unit ( The value determined in 304 is selected and fed back to the feedback filter 302 and output to the subtractor 307 to obtain the error e (n).

At this time, the training string storage memory 305 is a portion for storing the same data as the signal recorded in a predetermined area of the tape on the reproduction side.

The subtractor 307 calculates an error signal e (n) by calculating a difference between the determined value outputted through the multiplexer 306 or the training string and the signal f ₁ (n) from which the interference between the signals is removed, and then calculating the coefficient operator ( 308 and the mode control unit 309.

The coefficient calculating unit 308 calculates a new coefficient to update the coefficients of the previous filter 301 and the feedback filter 302 so that the error signal e (n) generated in the training sequence mode or the D.D mode is minimized.

The mode control unit 309 calculates the MSE with the error signal e (n), and if the value is more than one, determines the training mode and the value less than the DD mode, and selects the selected operation mode of the multiplexer 306. Output to stage (s).

In general, when the equalization and determination of the signal and the coefficient update are performed at the same time, the data is continuously input and the data is loaded on all taps, and the error e (n) is calculated.

In this case, the new coefficient to be updated must be calculated with the same e (n), so that at least the calculation time of the number of taps is required.

In other words, updating all the tap coefficients of the filter once requires the number of taps of data.

Therefore, as shown in FIG. 4, (n × N) data are required to update n coefficients for a filter having N total taps, and in particular, to see the effect of updating the number of n th training columns N (n + 1). The Nth dummy sections are needed, and (n + 1) x N areas are needed as a whole.

However, if there are too many training trains for coefficient updating in this way, it becomes undesirable as a technique for high density recording.

In particular, when a burst error occurs on the channel after the conversion from the training mode to the D.D mode, the newly updated coefficients converge in the wrong direction and the data error affects the rear end of the burst.

That is, the equalization circuit for obtaining filter coefficients as shown in FIG. 3 has various problems as follows while the calculation equation is simple.

First, it takes too much training trains to make MSE stable. In practice, a recording channel such as a magnetic tape channel has a limitation in that a large number of training sequences cannot be stored because of a limited recording area.

Second, as data update and signal equalization and determination are performed simultaneously, when data is transmitted immediately after the training sequence as shown in FIG. 4, the actual coefficient update cannot be calculated in real time. You should leave as much space as). In other words, the area capable of recording the training sequence becomes smaller.

Third, unlike the general communication channel, the magnetic tape channel is unstable in every track, so there may be cases where the training sequence cannot be continuously found when the signal is reproduced from the tape. At this time, due to system instability, the MSE must have a large value and operate in training mode, but since the training sequence cannot be found, effective coefficient updating becomes difficult and affects several tracks.

Fourth, even when a burst error occurs due to the incompleteness of the tape itself, it is necessary to immediately switch to training mode and update coefficients, but cannot operate in training mode because it does not have information of past training strings.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to perform signal equalization, determination, and mode control separately from coefficient operation, so that even if the data region starts while updating the coefficients in the training sequence, The equalization and deciding portion processes the data and the coefficient calculating portion continuously performs coefficient updating to provide an equalization circuit which reduces the number of training strings.

Another object of the present invention is to have a memory in front of the coefficient calculating unit and to store the training sequence in the provided memory and update the coefficient by reading the memory value, so that the input data does not continuously enter and is read whenever necessary after the coefficient update. Therefore, the present invention provides an equalization circuit that enables efficient use of training trains.

Features of the equalization circuit according to the present invention for achieving the above object, an ADC for converting a reproduction signal into a digital signal, a clock generator for generating a clock registered to the input reproduction signal to provide to the ADC, and Equalization and mode determination means for equalizing the reproduced signal output from the ADC to remove inter-signal interference and determining final output data and operation mode, and coefficient calculation for performing coefficient update according to the operation mode determined by the equalization and mode determination means. Means and, if the operation mode determined by the equalization and mode determination means is a training mode, once the reproduction signal output from the ADC is stored and supplied to the coefficient calculating means, and in the DD mode, the coefficient is immediately stored without storing the reproduction signal. It is comprised by the receiving training train storage means supplied to a calculation means.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a simple block diagram of an equalization circuit according to the present invention, and FIG. 6 is a detailed block diagram for generating an ADC 100 for converting a reproduction signal Vin into a digital signal Xin and a clock synchronized with an input reproduction signal Vin. And a clock generator 200 provided to the ADC 100 and an equalizer 500 for removing interference between signals present in the digitally reproduced reproduction signal Xin.

At this time, the equalizer 500 equalizes the received training sequence storage memory 600 storing the reproduction signal Xin before the interference between signals is removed, and the input signal Xin, and then outputs the signal Vout and the operation mode (training mode or Equalization, determination, and mode control unit 700 for determining the DD mode), and a coefficient operation unit 800 for performing only coefficient updating according to an operation mode.

In this case, the received training sequence storage memory 600 stores the reproduction signal Xin in the memory 600 once in the training mode, and then supplies the reproduction signal Xin to the coefficient operation unit 800, and supplies the reproduction signal Xin in the DD mode to the memory 600. It is supplied directly to the coefficient calculating unit 800 without storing in the.

The equalization, determination, and mode control unit 700 includes a pre-filter 701 for removing the precursor ISI portion, a feedback filter 702 for removing the post-cursor ISI portion, and an output of the pre-filter 701. A subtractor 703 that outputs a signal f ₂ (n) from which the inter-signal interference is removed from the reproduced signal Xin by subtracting the output of the feedback filter 702, and a signal f from which the inter-signal interference is removed from the subtractor 703 A determination section 704 for determining ₂ (n) as the final data, and a training sequence storage memory 705 for storing a certain amount of training sequence (the recording side records this training sequence at a certain interval) for operating in the training mode. And a multiplexer 706 that selects an output of the determination unit 704 or the training sequence storage memory 705 according to a mode selection signal s, feeds it back to the feedback filter 702, and outputs the same to find an error. And the difference between the output of the subtractor 703 and the output of the multiplexer 706. A subtractor 707 for calculating an error e (n) and an MSE with the error e (n) to determine an operation mode (training mode or DD mode), and the multiplexer 706 and the received training train storage memory ( 600 and a mode control unit 708 for outputting a mode selection signal s to the coefficient calculating unit 800.

In addition, the coefficient calculating unit 800 is the pre-filter 801, feedback filter 802, subtractor 803, training train storage memory 805, multiplexer 806, subtractor 807 is equalized, determined and mode The same as the configuration of the control unit 700, the new coefficients are calculated so that the error e ₂ (n) obtained by the subtractor 807 is minimized, and the pre-filter 701 and the post-filter of the equalization, determination and mode control unit 700. 702 and the calculation calculator 808 for updating all the filters 801 of the coefficient calculating unit 800 and the coefficient c of the feedback filter 802 with an error e ₁ (n) obtained from the subtractor 707, in operation mode. It is provided in place of the mode control unit 708 for determining the number, and in the coefficient operation unit 800, it is sufficient to use a simple two-level slicer 804 for data determination, and in the equalization, determination, and mode control unit 700, the determination unit 704. ) Are used to improve performance.

In this case, the coefficient operator 808 uses an LMS algorithm that satisfies the MSE standard to improve the performance of the decision feedback equalizer, and the mode controller 708 enters a training mode to quickly converge the MSE at the beginning of equalization. When the MSE becomes small, the mode is determined as the DD mode and the mode selection signal s corresponding thereto is output to the reception training sequence storage memory 600 and the multiplexers 706 and 806.

The present invention configured as described above allows the equalization, determination and mode control unit 700 and the coefficient operation unit 800 to operate separately, even if the data region starts while updating the coefficients in the training sequence. Therefore, the equalization, determination, and mode control unit 700 of the signal processes the data, and the coefficient operation unit 800 continuously performs the coefficient update.

In addition, in order to use the training train more efficiently, the reception training train storage memory 600 is provided in front of the coefficient calculating unit 800, and once the training train is stored in the memory 600, the memory value is read and counted. When the update is performed, input data is not kept coming in, but is read whenever necessary after updating the coefficients, thus enabling efficient use of the training sequence.

If a training sequence cannot be found in a track, and the MSE is large, the training sequence may be updated using the training sequence stored in the memory 600.

That is, the pre-filter 701 of the equalization, determination, and mode control unit 700 removes the precursor ISI portion of the reproduction signal Xin, and the feedback filter 702 removes the postcursor ISI portion of the reproduction signal Xin, and then subtracts 703. The output difference f ₂ (n) obtained by removing the interference between the signals is obtained by obtaining the output difference between the feedback filters 701 and 702.

At this time, since the signal f ₂ (n) from which the inter-signal interference is removed is a two-level signal, the determination unit 704 determines the output signal Vout using a two-level slicer, which is the simplest form. In addition, the decision unit 704 may use a complex detector such as a fixed delay tree search (FDTS) to increase the reliability of the determined data.

Here, the coefficients of the previous filter 701 and the feedback filter 702 are updated at the output c of the coefficient calculator 808 of the coefficient calculating unit 800.

In addition, the mode determining unit 708 receives a training mode selection signal s for fast convergence of the MSE at the beginning of equalization, and a DD mode selection signal s when the MSE becomes small. And output to multiplexers 706 and 806.

Accordingly, the multiplexer 706 selects and outputs the training sequence stored in the training sequence storage memory 705 when the training mode selection signal s is input, and determines the determination sequence 704 when the DD mode selection signal s is input. Selective output of the value.

Therefore, the subtractor 707 has a difference between the training sequence stored in the training sequence storage memory 705 and the output signal f ₂ (n) from which the interference between the signals has been removed, or the value finally determined by the determination unit 704 and the interference between the signals. The error signal e ₁ (n) is obtained as a difference from the removed output signal f ₂ (n) and output to the mode control unit 708.

The mode control unit 708 calculates the MSE with the error signal e ₁ (n), and if the value is greater than or equal to a training mode, and if the value is less than or equal to the DD mode, then the multiplexer 706, the multiplexer 806 of the coefficient calculating unit 800 and the received training string storage memory 600 are output.

As described above, the equalization, determination, and mode control unit 700 continuously processes the data, calculates the MSE with the error signal e ₁ (n), and then determines the operation mode.

Meanwhile, when the operation mode selection signal s provided from the mode controller 708 indicates a training mode, the reception training sequence storage memory 600 stores the reproduction signal Xin in the memory 600 once, and then calculates the coefficient operation unit ( If the DD mode is shown, the reproduction signal Xin is supplied directly to all the filters 801 of the coefficient calculating unit 800 without storing the reproduction signal Xin in the memory 600.

At this time, the coefficient calculating unit 800, like the equalization, determination, and mode control unit 700, removes the interference between signals in the subtractor 803 by the difference between the output of the pre-filter 801 and the output of the feedback filter 802, The signal f ₃ (n) from which the inter-signal interference is removed is outputted to the subtractor 807 for obtaining the error e 2 (n), and at the same time, the output data is determined by the two-level slicer 804.

Accordingly, the multiplexer 806 stores the value or training sequence determined by the two-level slicer 804 according to the operation mode selection signal s output from the mode control unit 708 of the equalization, determination, and mode control unit 700. The training sequence stored in the memory 805 is selected and output to the post filter 802 and the subtractor 807.

The subtractor 807 is a difference between the training sequence stored in the training sequence storage memory 805 and the output signal f ₃ (n) from which the interference has been eliminated, or the value finally determined by the two-level slicer 804 and the interference between the signals. The error signal e ₂ (n) is obtained as a difference from the removed output signal f ₃ (n) and output to the coefficient calculator 808.

The coefficient calculator 808 updates the new coefficients by the LMS algorithm which minimizes the MSE with the error signal e ₂ (n) generated in the training sequence mode or the DD mode, and the value is equalized, determined, and controlled by the mode controller 700. ) Is inputted to the feedback filters 801 and 802 before the feedback filters 701 and 702 and the coefficient calculating unit 800 to update the coefficients.

FIG. 7 shows how the training train is used differently than the conventional method as shown in FIG. For example, if the same amount of training sequence as the conventional method, that is, (n + 1) × N training sequences, is applied to the present invention, the coefficient calculating unit 800 first transmits the training sequence to the received training sequence storage memory 600. After storing, N data is read from the memory 600 whenever necessary, and then a coefficient is updated once. The second update reads the N data after one bit is delayed to update the coefficient.

If the coefficient is updated repeatedly until all (n + 1) × N data are used in this manner, the number of times of updating the coefficient can be repeated (n + 1) × N− (N + 1) times.

Therefore, compared with the conventional n times, a much larger number of coefficient updates can be performed with the same number of training sequences. In other words, a much smaller number of training sequences is sufficient for the same number of coefficient updates.

As described above, the decision feedback equalization circuit for removing the inter-signal interference according to the present invention has the following advantages by separately using the equalization, determination, and mode control unit and coefficient calculation unit of the signal.

First, more coefficients can be updated with the same training sequence, allowing the MSE to use the minimum coefficient. In other words, a smaller number of training trains are sufficient to obtain coefficients with the same MSE.

Second, when the burst error occurs on the channel while operating in the D.D mode, and the MSE suddenly increases, the training mode can be operated again with the value stored in the received training string storage memory.

Fifth, when the MSE needs to operate in the training mode because the cursor is large, but the training sequence cannot be found, the coefficient coefficient can be effectively updated by operating in the training mode using the training sequence of the previous track stored in the received training sequence storage memory. Therefore, it is possible to adapt to changes in the channel environment more effectively than the conventional method.

Claims (5)

An analog / digital converter for converting a reproduction signal into a digital signal, a clock generator for generating a clock synchronized with the input reproduction signal, and providing the analog / digital converter to the analog / digital converter, and equalizing the reproduction signal output from the analog / digital converter Equalization, determination and mode control means for eliminating interference between signals and determining final output data and operation mode, coefficient calculating means for performing coefficient update according to the operation mode determined by the equalization, determination and mode control means, and the equalization If the operation mode determined by the determination and mode control means is a training mode, the reproduction signal outputted from the analog / digital converter is stored once and then supplied to the coefficient calculating means. If the determination direct mode (DD) mode, the reproduction signal is not stored. And receiving training string storage means for supplying directly to the coefficient calculating means. St. equalization circuit. 2. The apparatus of claim 1, wherein the equalization, determination, and mode control means comprises: a forward filter for removing an interference portion between the precursor signals among the reproduction signals output from the analog / digital converter, and an output from the analog / digital converter. A post-filter which removes the interference part between the post-cursor signals among the reproduction signals, a subtractor which obtains an output difference between the pre-filter and the feedback filter, and outputs a signal from which the inter-signal interference is removed from the reproduction signal; A two-level slicer that determines the final data by comparing the interference-free signal with a reference level, a training sequence storage memory storing the training sequence promised to be recorded on the tape channel, and a mode selection signal. Mode indicates the output of the training row storage memory, and indicates decision direct (DD) mode. A multiplexer that selects a feedback force and feeds it back to the post-filter to output an error, a subtractor that calculates an error signal by calculating an output of the subtractor and an output of the multiplexer, and a mean squared error with the error signal. And a mode controller configured to determine a training mode or a decision direct (DD) mode after calculating an error (MSE), and output a mode selection signal to the multiplexer, a received training sequence storage memory, and a coefficient calculating unit. 3. The method of claim 2, wherein the mode control unit is a training mode to quickly converge the mean squared error (MSE) at the beginning of equalization, and determines that the mode control unit determines the decision direct (DD) mode when the mean squared error (MSE) decreases. An equalization circuit characterized by the above-mentioned. 2. The apparatus of claim 1, wherein the coefficient calculating means comprises: a pre-filter for removing an interference portion between the precursor signals among the reproduction signals output through the reception training sequence storage memory, and a post of the reproduction signals output through the reception training sequence storage memory. A feedback filter for removing an interference portion between cursor signals, a subtractor for outputting a signal from which the inter-signal interference is removed from a reproduction signal by obtaining an output difference between the pre-filter and the feedback filter, and a signal from which the inter-signal interference is removed from the subtractor A two-level slicer for determining final data compared to a reference level, a training sequence storage memory for storing training sequences without interference between signals reproduced on a tape channel, and a training sequence storage if a mode selection signal indicates a training mode If the output of the memory is selected and the crystal direct (DD) mode is displayed, the output of the two-level slicer is selected and the A multiplexer for feeding back to the filter and calculating an error, a subtractor for calculating an error by calculating an output of the subtractor and an output of the multiplexer, and calculating new coefficients to minimize the error obtained in the subtractor An equalizing circuit comprising: a coefficient calculator for updating the coefficients of the feedback filter before all the feedback filters; 5. The method of claim 4, wherein the coefficient calculator comprises: a least mean square error (LM) to minimize the mean square error (MSE) with the calculated error signal S) An equalization circuit characterized by the use of an algorithm.