KR100257730B1 - Adaptive equalizer for dvcr - Google Patents

Abstract

PURPOSE: An adaptive equalizer of a digital VCR(Video Cassette Recorder) is provided to update a weight by using a filter output prior to many sampling clocks, so as to supply the adaptive equalizer for making a real time equalization of digital regenerative signals capable of being performed. CONSTITUTION: A feedforward filter(200) filters a digital regenerative signal and outputs a regenerative signal having a (1-D) delay characteristic. A delaying unit(210) delays a filter output from the feedforward filter(200) for a constant time. A level decider(220) decides a 3-level by inputting the delayed filter output, and delays the 3-level for a constant time. An error detector(230) calculates a difference between a delayed 3-level signal outputted from the level decider(220) and the delayed filter output outputted from the delaying unit(210) to generate an error signal. A weight update unit(240) updates a weight according to the error signal, the delayed digital regenerative signal, a previous delayed weight and an inputted scaling factor. The second delaying unit(250) delays the updated weight for a constant time, and outputs the weight to the feedforward filter(200).

Description

ADAPTIVE EQUALIZER FOR A DIGITAL VCR

The present invention relates to an adaptive equalizer for reproducing a self-recorded signal of a digital VCR, and in particular, real-time equalization of a digital reproduction signal is achieved by filtering by weight updating using a filter output before a plurality of sampling clocks. An adaptive equalizer is made possible.

With the development of computer, communication, broadcasting, home appliances, etc., the quality of information provided to general users is becoming more and more advanced, and such information can be characterized by multimedia, visualization, stereoscopic, and independence. In particular, digital media use technology is the basis for this trend and has a great impact on the progress toward the information society.

As the information age flows, the demand for high speed transmission and storage of large data is rapidly increasing. The storage of digital data has mainly used a magnetic recording method and is widely used because it provides a lot of data storage capacity at a low price.

Currently, a magnetic recording device that is widely used is an analog method using RLL (Run Length Limited) and Peak Detection.

The equalization process of the conventional PR4 channel will be described with reference to FIG. 1.

The input code string of the magnetic recording / reproducing apparatus is recorded after passing through a precoder 100 composed of a 2-bit delayer 102 and a MOD2 adder 101. That is, the magnetic channel 110, the equalizer 111, and the reproducing encoder 112, 1 / (1-D ² ) to adjust the characteristics before passing through the regenerator having the characteristics of (1-D ² ) during reproduction It is precoded to have a delay characteristic of.

The regeneration process consists of a delay characteristic of (1-D ² ), so that it can be decomposed into (1-D) and (1 + D). Here, (1-D) is replaced with the differential characteristic by the magnetic channel 110 and the equalizer 111 of the reproduction system, and (1 + D) is the 1-bit delay 121 and the adder 122. It consists of a playback encoder 112 composed of.

Therefore, the reproduction process allows the reproduction signal to have a delay characteristic by (1-D ² ) consisting of (1-D) and (1 + D), and the recording signal is 1/1 in the precoder 100 for accurate reproduction. It is precoded to have a delay characteristic of (1-D ² ).

The magnetic recording signal precoded and recorded on the magnetic recording tape is reproduced by the head provided in the magnetic channel 110, reproduced and amplified through the rotary transformer, and has a (1-D) delay characteristic through the equalizer 111. Since it is input to the reproduction encoder 112 and has a (1 + D) delay characteristic, it has a delay characteristic of (1-D ² ) during reproduction.

The ternary waveforms (1, 0, -1) passing through the reproduction encoder 112 of (1 + D) are identified as binary waveforms (1, 0) by the data detector 113 to enable reproduction of the recording signal. . That is, the data detector 113 generates three levels of reproduction signals output from the reproduction encoder 112 at two levels. In other words, the data detector 113 corresponds to one level of the playback signal output from the playback encoder 112 to one level, to correspond to the 0 level playback signal to 0 level, and to a -1 level playback signal. Is equalized with one level of reproduction signal to generate equalization signals of 0 and 1 levels.

In such a PR4 detection method, the high frequency component emphasized in the equalization circuit can be suppressed by the (1 + D) circuit which is the reproducing encoder 112.

In the magnetic recording / reproduction channel, the reproduction signal is a differential form of the recording signal, so the step response h (t) that determines the characteristics of the magnetic recording channel is modeled by a Lorentzian function of Equation 1 below.

Here, PW ₅₀ is the width of the pulse corresponding to 50% of the maximum output value of h (t) and this value is determined according to the recording density.

However, the conventional analog magnetic recording and reproducing apparatus of the PR4 channel has a simple system implementation and effective timing recovery. However, as the recording density increases, the intersymbol interference (ISI) deepens, making it difficult to detect. That is, the recording density for recording the magnetic recording signal on the magnetic recording tape becomes gradually higher, which makes it difficult to detect data during analog magnetic recording and reproduction of the aforementioned PR4 channel.

Therefore, in recent years, Partial Response Maximum Likelihood (PRML) technology has been introduced to reduce these effects. The PRML technology can easily remove interference when detecting data by generating and transmitting artificial interference.

The configuration and operation of the digital VLC equalizer to which the PRML technique is applied will be described below with reference to FIG. 2.

As shown in FIG. 2, the conventional digital VAL equalizer includes a weight updater 135 and a weight updater configured to update a weight by inputting a digital reproduction signal converted into a digital signal by the A / D converter 150. Delay 136, which delays the weight updated in step 135, and provides the weight update unit 135 to the weight update unit 135, from the A / D converter 150 according to the weight output from the delay unit 136. A feedforward filter 132 for feedforward filtering the output digital reproduction signal and outputting a reproduction signal, and a level for determining a three-level signal by inputting the reproduction signal output from the feedforward filter 132. The unit 133 and the level determiner 133 determine the level and compare the reproduction signal of the next clock output from the feedforward filter 132. The error detection unit 134 detects a signal and outputs the weight update unit 135 to the weight update unit 135 so as to update the weight.

On the other hand, the reproduction signal output from the feed forward filter 132 is input to the clock generation unit consisting of the timing recovery unit 140, the D / A converter 141, and the VCO 142 is used for timing recovery. The recovered clock is input to the A / D converter 150.

The operation of the conventional equalizer configured as described above will be described.

The A / D converter 150 receives an analog reproduction signal as an input and accurately digitizes and restores timing to supply a digital signal to the equalizer 130. In this case, the timing restoration is performed by the timing restoration unit 140, the D / A converter 141, and the VCO 142.

The signal digitized by timing recovery in the A / D converter 150 is input to the equalizer 130 to equalize the PR4 characteristic.

The digital reproduction signal output from the A / D converter 150 is output after the feedforward filter is filtered by the feedforward filter 132, and the filter output signal y (k (k) is output from the feedforward filter 132. )) Is a sum of values obtained by multiplying the filter coefficients after the input digital reproduction signal x (k) is delayed at a sampling time interval, as shown in Equation 2 below.

Equation (2) can be briefly expressed internally of the vector as shown in Equation (3).

y (k) = X ^t W = W ^t X

In Equation 3 above, t is a transpose of a vector or matrix, and w and x (k), which are N-dimensional column vectors, are defined by Equation 4 below.

W = [w _0, w _1, w _2, ... , w _n-1 ] ^t

X (k) = [(k), x (k-1),... , x (k-n + 1)] ^t

The output of the equalizer 130, that is, the output y (k) of the feedforward filter 132 is determined by the level determiner 133 as a three-level signal d (k) and the error detector 134. ) Is entered.

That is, in order to update and determine the weight w shown in the above equation, the output y (k) of the feedforward filter 132 is input to the level determiner 133.

The three level signal d (k) whose level is determined by the level determiner 133 is the feedforward filter to a subsequent sampling clock by a sampling time interval in the error detector 134, as shown in Equation 5 below. An output signal of 132 and its difference is calculated and output as an error signal e (k).

Where w _nw is the updated new weight value and w _old is the previous weight value.

The error signal e (k) output from the error detector 134 is input to the weight updater 135 and used for weight update as shown in Equation 5 above.

That is, the weight updater 135 outputs the digital reproduction signal x (k) output from the A / D converter 150 and the delayed previous weight w _old output from the delay unit 136. And update the weight according to the error signal e (k) output from the error detector 134 and output the updated weight to the feedforward filter 132 through the delayer 136 to update the updated weight w _nw . Output for use.

Meanwhile, the data y (k) adaptively equalized and output from the equalizer 130 may be input to a Viterbi detector, which is a data detector, so as to effectively search for a desired signal.

However, the feedforward filtering of the reproduced digital data is performed by a sampling clock of 41.85 MHz. Therefore, to equalize and output the input code string in real time, the weight should be determined by updating the weight within 23.89ns.

However, it is difficult for the conventional equalizer to determine the level from the output of the feedforward filter 132 and to detect an error within 23.89 ns in real time, so that the equalization is not accurately performed. There was a problem that became large.

In order to solve the above problem, an object of the present invention is to provide an adaptive equalizer for enabling real-time equalization of a digital reproduction signal by performing a weight update using a filter output before a plurality of sampling clocks.

In order to achieve the above object, the present invention filters a digital reproduction signal input and outputs a feedforward filter means for outputting a reproduction signal having a delay characteristic of (1-D), and a filter output output from the feedforward filter means. A delay means for delaying for a time, a level determining means for determining a three level as an input of the filter output delayed by the delay means and delaying for a predetermined time, a delayed three-level signal output from the level determining means and an output from the delay means; Error detection means for generating an error signal by calculating a difference of the delayed filter output, an error signal output from the error detection means, a delayed digital reproduction signal output from the feedforward filter means, a delayed previous weight, and an input Update weight to update weight based on scaling factor And second delay means for delaying the updated weight outputted from the weight updating means and outputting the updated weight to the feedforward filter means.

1 is a structural diagram of a PR4 channel used for general magnetic recording and reproduction;

2 is a block diagram of a conventional DVC equalizer

3 is a block diagram of an adaptive equalizer according to the present invention

Explanation of symbols on the main parts of the drawings

200: feedforward filter 201: shift register

202: matrix product and adder 210, 250: delay unit

211, 212, 222, 232: Delay 220: Level determination unit

221: level determiner 230: error detection unit

231: subtractor 240: weight update unit

241 matrix multiplier 242 matrix adder

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the adaptive equalizer according to the present invention includes a feedforward filter 200, delay units 210 and 250, a level determiner 220, an error detector 230, and a weight updater 240. It is composed.

The feedforward filter 200 filters the input digital reproduction signal x and outputs a reproduction signal y (k) having a delay characteristic of (1-D), and inputs the digital reproduction signal x. The shift register 201 shifts and delays a sampling clock input according to the determined number of taps, and the updated weight delayed by the delay unit 250 to a plurality of delayed digital reproduction signals output from the shift register 201. and a matrix product and adder 202 for multiplying (w) and adding them to output a reproduction signal having a delay characteristic of (1-D).

The delay unit 210 delays the filter output y (k) output from the matrix product and the adder 202 of the feedforward filter 200 for a predetermined time according to an input sampling clock. A delayer for delaying the filter output y (k) output from the matrix product of the feedforward filter 200 and the adder 202 by one clock according to the input sampling clock and outputting the delayed signal to the level determiner 220. And the error detection unit 230 by delaying the one-clock delayed filter output y (k-1) output from the delay unit 211 until the operation of the level determining unit 220 is completed. It consists of a delay 212 for outputting.

The level determiner 220 determines three levels by inputting the delayed filter output y (k-1) output from the delay unit 212 of the delay unit 210 and delays the predetermined time. A level determiner 221 for determining a three level by inputting the filter output y (k-1) delayed by one clock in the unit 211, and a three level signal outputted from the level determiner 221 to delay the The delay unit 222 outputs the error detection unit 230.

The error detector 230 is a delayed three-level signal output from the delay unit 222 of the level determining unit 220 and a delayed filter output (y) output from the delay unit 212 of the delay unit 210. Is calculated by generating the difference between the delayed filter output y (k-2) and the delayed three-level signal d ( k-2)) to delay the subtractor 231 for calculating the difference and outputting the error signal e (k-2), and the error signal e (k-2) output from the subtractor 231. And a delay unit 232 output to the weight update unit 240.

The weight updater 240 outputs an error signal e output from the error detector 230, a delayed digital reproduction signal / x output from the feedforward filter 200, and a previous weight w delayed. And the delayed error signal e (k-3) output from the delay unit 232 of the error detector 230 by updating the weight according to the input scaling factor μ. A matrix multiplier 241 for matrix multiplying the delayed digital reproduction signal (/ x) outputted from 201, and the scaling factor (μ) input thereto as an input, and the matrix multiplier The matrix adder 242 outputs the updated weight w to the delay unit 250 by adding the outputs of the matrix 241 to the delay unit 250.

The delay unit 250 delays the updated weight w outputted from the matrix adder 242 of the weight updater 240 for a predetermined time and adds the matrix product and adder 202 of the feedforward filter 200. )

The operation of the adaptive equalizer according to the present invention configured as described above will be described in detail.

First, the input digital reproduction signal x is output after the feedforward filtering is performed by the feedforward filter 200. That is, the digital reproduction signal x is shifted in the shift register 201, and a plurality of digital reproduction signals x are inputted to the matrix product and adder 202 according to the number of taps, so that the reproduction signal y (k) has a delay characteristic of (1-D). Will be printed).

The signal output from the feedforward filter 200 must be leveled to update the weight of the adaptive equalizer. In this case, the signal y (k) output from the matrix product and adder 202 is delayed in accordance with the sampling clock in the delay unit 211, and the signal delayed in the delay unit 211 and output is delayed. Equation 4 has the following values.

W = [w _0, w _1, w _2, ... , w _n-1 ] ^t

X (k) = [(k), x (k-1),... , x (k-n + 1)] ^t

The signal y (k-1) delayed by the delay unit 211 is determined to be three levels by the level determiner 221 of the level determiner 220. Here, the signal d (k-1) determined to be three levels is output as a delayed three level signal d (k-2) after being delayed by the delay unit 222 according to the sampling clock.

Meanwhile, the delayed signal y (k-1) output from the delay unit 211 to detect an error signal is delayed again by the delay unit 212 while the level determining unit 220 determines the level. The signal is output as a second delayed signal y (k-2). The delay in the delay unit 212 is for detecting an error signal.

The error detector 230 outputs a delayed three-level signal output from the delay unit 222 of the level determiner 220 and a second delayed feedforward output from the delay unit 212 of the delay unit 210. The error signal e is generated by calculating the difference of the output y (k-2) of the filter.

That is, in the subtractor 231, the filter output from the delayer 212 in the delayed three-level signal d (k-2) output from the delayer 222 as shown in Equation 6 below. The output signal y (k-2) is subtracted to detect the error signal e (k-2).

e (k-2) = d (k-2) -y (k-2)

As described above, the error signal e (k-2) output from the subtractor 231 is delayed according to the sampling clock by the delayer 232 and then input to the weight updater 240 to update the weight. do.

That is, in the matrix multiplier 241 of the weight update unit 240, the delayed error signal e (k-3) output from the delay unit 232 of the error detector 230 and the shift register 201. A matrix multiplication process is performed on the delayed digital reproduction signal (/ x), which is a vector output from, and the input scaling factor (μ). The output of the matrix multiplier 241 is output as the updated weight w by adding the matrix of the delayed previous weight w. In this way, the weight update process may be expressed by Equation 7 below.

W _nw = W _old + μe (k-3) X (k-3)

Here, X is a shifted digital reproduction signal output from the shift register 201 as a vector value.

Equation 6 and Equation 7 are performed by the error detector 230 and the weight updater 240, and the updated weight w _nw output from the weight updater 240 is delayed again. It is used as a coefficient in feedforward filtering of a digital reproduction signal input next after being delayed in the device 250.

That is, the updated weight is input to the matrix product and adder 202 of the feedforward filter 200 and used as a coefficient. At this time, the inputted digital reproduction signal is a digital reproduction signal of a state after three or more sampling clocks have already passed, and a filter coefficient for filtering the currently input digital reproduction signal is determined using the digital reproduction signal before the three sampling clocks.

As described above, the digital reproduction signal currently input according to the updated weight is filtered using the reproduction signal prior to the three sampling clocks so as to have a delay characteristic of (1-D).

Therefore, since the weight does not need to be updated within 23.89 ns, filtering with a sampling clock of 41.85 MHz is possible during feedforward filtering.

As described above, the adaptive equalizer according to the present invention updates the weight using the filter output before the plurality of sampling clocks, thereby enabling real-time equalization of the digital reproduction signal by the sampling clock of 41.85 MHz.

Claims (7)

Feedforward filter means for filtering an input digital reproduction signal and outputting a reproduction signal having a delay characteristic of (1-D); Delay means for delaying the filter output from the feedforward filter means for a predetermined time; Level determination means for determining three levels as input to the delayed filter output from the delay means and delaying for a predetermined time; Error detection means for generating an error signal by calculating a difference between the delayed three-level signal output from the level determining means and the delayed filter output output from the delay means; Weight updating means for updating the weight according to an error signal output from the error detecting means, a delayed digital reproduction signal output from the feedforward filter means, a delayed previous weight, and an input scaling factor; And And a second delay means for delaying the updated weight outputted from the weight update means for a predetermined time and outputting the delayed weight to the feedforward filter means. The method of claim 1, wherein the feedforward filter means A shift register for shifting and delaying the input digital reproduction signal to the input sampling clock according to the determined number of taps; And The multiplied delayed digital reproduction signals output from the shift register are multiplied by the updated weight delayed by the second delay means and added to the matrix multiplication and addition unit for outputting a reproduction signal having a delay characteristic of (1-D). Adaptive equalizer of a digital BC. The method of claim 1, wherein the delay means And a delay of the filter output from the feedforward filter means for a predetermined time according to the input sampling clock. The method of claim 3, wherein the delay means A first delayer for delaying the filter output output from the feedforward filter means by one clock according to an input sampling clock and outputting the delayed clock to the level determining means; And And a second delayer for delaying the output of the one-clock delayed filter output output from the first delayer until the operation of the level determining means is completed and outputting the delayed filter output to the error detecting means. The method of claim 4, wherein the level determining means A level determiner configured to determine three levels as inputs of the filter output delayed by one clock from the first delay unit; And And a third delayer for delaying the three-level signal outputted from the level determiner and outputting the delayed three-level signal to the error detecting means. The method of claim 5, wherein the error detecting means A subtractor configured to calculate an difference between the delayed filter output and the delayed three-level signal output from the second delayer and the third delayer and output an error signal; And And a fourth delayer for delaying an error signal output from the subtractor and outputting the delayed error signal to the weight update means. 7. The method of claim 2 and 6, wherein the weight update means is A matrix multiplier for matrix multiplying the delayed error signal output from the fourth delayer, the delayed digital reproduction signal output from the shift register, and the scaling factor input thereto; And And a matrix adder for metrically adding the outputs of the matrix multiplier according to the delayed previous weights and outputting the updated weights to the second delay means.

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