GB2331899A

GB2331899A - Adaptive equaliser for a digital VCR

Info

Publication number: GB2331899A
Application number: GB9819476A
Authority: GB
Inventors: Myung-Hwan Jung
Original assignee: Daewoo Electronics Co Ltd
Current assignee: WiniaDaewoo Co Ltd
Priority date: 1997-11-29
Filing date: 1998-09-07
Publication date: 1999-06-02
Also published as: JPH11176099A; KR19990043645A; KR100257730B1; GB9819476D0

Abstract

A method and apparatus capable of performing real time equalization in a digital VCR system is provided. The apparatus comprises a feedforward filter, delays, a signal level decision block, an error detection block, and a weight update block. The method for equalizing a digital data stream {x(k)} based on a weight vector W old having N components and a previously equalized data signal y(k-3). k being index representing a sequence of data, includes the steps: (a) deciding a level of the previously equalized data signal y(k-3) to thereby provide a decision signal d(k-3) having one of predetermined values; (b) deciding an error signal e(k-3) by subtracting the previously equalized data signal y(k-3) from the decision signal d(k-3); (c) generating data vectors X(k) and X(k-3) both having N components from the digital data stream, wherein X(k)=[x(k), x(k-1), ..., x(k-N+1)] and X(k-3)=[x(k-3), x(k-4), ..., x(k-N-2)]; (d) providing an equalized data signal y(k) based on the weight vector W old and the data vector X(k); let generating an updated weight vector W new based on the weight vector W old , the error signal e(k-3) and the data vector X(k-3); (f) increasing k by 1 and setting W new as W old ; and (g) repeating the steps (a) to (f) for the rest of the digital data stream (x(k)}.

Description

2331899 METHOD AND APPARATUS CAPABLE OF PROVIDING AN ADAPTIVE EQUALIZATION

IN A DIGITAL VCR SYSTEM The present invention relates to an equalization method and apparatus f or use in a digital VCR system; and, more particularly, to a method and apparatus capable of providing a real-time adaptive equalization in a digital VCR system.

A conventional digital VCR system may be divided into two parts: a recording part which records digital data on a magnetic recording medium; and a reproducing part which detects the data recorded on the magnetic recording medium by a magnetic reproducing channel, wherein the digital data may be video data, audio data or the like. During data recording and reproducing processes, there may occur intersymbol interference (ISI) of the data. To ameliorate this problem, the conventional digital VCR system employs a partial response method, e.g., a Partial Response class-IV (PR class-IV) technique. The basic idea of the partial response scheme is to introduce some correlated interferences into the data stream to be recorded in a controlled manner rather than trying to eliminate the interferences therefrom completely. By introducing the controlled amount of ISI into the data being recorded, the interference at the reproducing part can j be effectively reduced.

Referring to Fig. 1, there is shown a schematic block diagram for a conventional digital VCR system adopting the PR class-IV technique. The digital VCR system comprises a precoder 100, a magnetic recording/ reproducing channel 110, an equalizer 120, a reproducing encoder 130, and a data detector 1 40.

In the recording process, an -input data signal having binary data values is fed to the precoder 100. The precoder may be made of a 2-bit delay and a modulo-2 adder. In the precoder 100, the input data signal is precoded to get a transfer function of, e.g., 1/ (1-D 2). Then, with the transfer function of 1/(l-D 2) ' the recorded data signal is recorded in the magnetic recording/ reproducing channel 110. The transfer function of 1/(l-D2) is a characteristic of a recording part in the PR class-IV method.

In the reproducing process, the recorded data signal is read from the magnetic recording/reproducing channel 110 and equalized by the equalizer 120, wherein the equalized data signal is a data stream, each data value being one of ternary values of -1, 0 and 1.

After the equalization procedure is completed, the equalized data signal is transmitted from the equalizer 120 to the reproducing encoder 130. The transfer function of the magnetic recording/reproducing channel 110 to the equalizer is (1-D), wherein (1-D) corresponds to a differential is characteristic of reproduction process.

At the reproducing encoder 130, a data value in the equalized data signal is added to its previous data value. The reproducing encoder 130 may be made of an adder and a 1bit delay as well known in the art, to thereby implement a transfer function of (1+D). Therefore, the transfer functions of (1-D) and (1+D) are implemented through the magnetic recording/reproducing channel 110 to the reproducing encoder 130.

The encoded data signal from the reproducing encoder 130 is transmitted to the data detector 140. The data detector 140 reproduces the input data signal by converting the ternary data values in the encoded data signal into binary values, i.e., 0 and 1. That is, 1 and -1 in the encoded data signal is set to 1; and 0 in the encoded data signal is set to 0.

The conventional digital VCR described above is structurally simple. Since, however, the ISI of the data increases with the recording density of the data, it would become difficult to precisely detect recorded data as the recording density increases.

Recently, a PRML(Partial Response Maximum Likelihood) scheme has been introduced in order to improve the aforementioned shortening of the digital VCR shown in Fig. 1. The PRML method according to the prior art will be described with reference to Fig. 2.

Referring to Fig. 2, there is shown a block diagram of 3 is a conventional digital VCR system adopting the PRM technique. The conventional VCR system comprises an A/D convertor 200, an equalizer 220, a Viterbi decoder 240 and a sampling clock generation block 260. The equalizer 220 includes a feedforward filter 222, a delay 224, a weight update control block 226, a signal level decider 228 and an error detector 230. The- sampling clock generation block 260 includes a timing recovery block 262, a digital- toanalog (D/A) convertor 264 and a voltage-controlled oscillator(VCO) 266.

The A/D convertor 200 converts an analog reproduced data signal into a digital data signal x(k), wherein the analog reproduced data signal is obtained from a recording medium, e.g., a magnetic tape, by a head assembly (not shown) included, e.g., in the magnetic recording/ reproducing channel shown in Fig. 1. The A/D conversion is carried out in response to a sampling clock inputted from the sampling clock generation block 260, wherein the sampling clock generation block 260 recovers a sampling clock timing to thereby generate a new sampling clock based on the recovered sampling clock timing. The digital data signal x(k) is transmitted from the A/D convertor 200 to the feedforward filter 222 and the weight update control block 226.

The feedforward filter 222 filters the digital data signal x(k) to generate an equalized data signal y(k), wherein the equalized data signal y(k) is a summation of the product of the digital data signal x(k-i) and its corresponding weight - 4 value w, provided from the delay 224, i being 0 to (N-1) with N being a positive integer greater than 1. This relationship can be represented as:

N- 1 y(k) =E w,,x(k-i) i=o (Eq.

Eq. I may be simply expressed as an inner product of vectors as follows:

y (k) =X (k) ': W= W'-X (k) The weight vector W and the data vector X (k), both being N dimensional column vectors, can be defined as:

(Eq. 2).

W = 1 W 1 WI f W21 "' 0 WN-11 ' (Eq. 3) X (k) = [x (k), x (k-1) x (k-N+1) The weight vector W(k) and the data vector X(k) can be in the form of N dimensional row vectors. Then y(k) may be expressed as y(k)=X-WI=W-Xl.

The equalized data signal y(k) is transmitted to the error detector 230, the signal level decider 228 and the Viterbi decoder 240.

The signal level decider 228 determines to which one of is the ternary values, e.g., -1, 0 and 1, the equalized data signal y(k) corresponds, thereby generating a decision signal d(k). The error detector 230, responsive to the decision signal d(k) and the equalized data signal y(k), generates an error signal e (k) by computing the di f f erence between d (k) and y(k) as follows:

1 i 1 e (k) = d (k) -y (k) (Eq. 4).

The error signal e(k) is transmitted from the error detector 230 to the weight update control block 226 and the sampling clock generation block 260. The weight update control block 226 receives the error signal e (k), the digital data signal x(k) and a delayed weight vector W from the oLd delay 224 to thereby generate a new weight vector Wnew as follows:

W Wold + pi-e(k) -X (k) is (Eg. 5) wherein g is a scaling factor for controlling the convergence of data, fed from, e.g., a main control unit (not shown). Thereafter, the weight update control block 226 transmits the new weight vector Wnew to the feedforward filter 222 via the delay 224, the new weight vector Wnew being used to calculate y(k+l) at the subsequent sampling clock period.

The timing recovery block 262 recovers the new sampling clock timing based on the equalized data signal y(k) and the error signal e(k). The adjusted sampling clock timing is processed by the D/A 264 and the WO 266 to provide the A/D convertor 200 with the sampling clock signal.

The Viterbi decoder 240 processes the equalized data signal y(k) based on a conventional Viterbi decoding algorithm to thereby provide a detected data signal.

As described above, updating the weight vector W requires y (k), d (k) and e (k), implying that all the processes according 6 - to Eqs. 1 and 4-5 should be carried out sequentially within one sampling clock period. For example, if the sampling clock is 41.85 Mhz, the computation of y(k) to Wnew should be sequentially performed within 23.89 ns, requiring very high speed devices in the equalizer 220.

It is, therefore, an object of. the present invention to provide a method and apparatus capable of performing a realtime equalization in a digital VCR system.

In accordance with the present invention, there is provided a method for equalizing a digital data stream {x (k)} based on a weight vector W otd having N components and a previously equalized data signal y(k-3), k being index representing a sequence of data, comprising the steps of:

(a) deciding a level of the previously equalized data signal y(k-3) to thereby provide a decision signal d(k-3) having one of predetermined values; (b) deciding an error signal e(k-3) by subtracting the previously equalized data signal y(k-3) from the decision signal d(k-3); (c) generating data vectors X(k) and X(k-3) both having N components f rom the digital data stream, wherein X (k) = [x (k) 1 x (k- 1),..., x (k- N+1) 1 and X (k-3) = [x (k-3), x (k-4), ---, x (k-N-2) 1; (d) providing an equalized data signal y(k) based on the weight vector Wold and the data vector X(k); 7 (e) generating an updated weight vector Wnew based on the weight vector W Idl the error signal e(k-3) and the data vector X(k-3); (f) increasing k by 1 and setting Wnew as W old; and (g) repeating the steps (a) to (f) for the rest of the digital data stream {x(k)}.

In accordance with the present invention, there is provided an apparatus having an. equalizer for equalizing a digital data stream, comprising: a first delay for storing an updated weight vector Wnew and providing a previously stored weight vector as a weight vector W old; a weight vector having N components; a feedforward filter, responsive to the digital data stream, for generating a first and a second data vectors X(k) and X(k-3) both having N components and providing an equalized data signal y(k) based on the first data vector XW and the weight vector W old 1 X (k) and X (k3) being [x (k), x (k1) ' ---, x (k-N+1) 1 and [x (k-3), x (k-4),... , x (k-N- 2)], respectively; a second delay for storing the equalized data signal y(k) and providing an equalized data signal y(k-1) previously stored therein; a third delay for storing the equalized data signal y(k1) and providing an equalized data signal y(k-2) previously stored therein; a signal level decision block for converting the equalized data signal y(k-1) into a decision signal d(k-1) and providing a previously converted decision signal d(k-2), a decision signal having one of predetermined values; an error detection block for 8 1 r_ detecting an error signal e(k-2) by obtaining the difference between the decision signal d(k-2) and the equalized data signal y(k-2) and providing a previously detected error signal e(k-3); and a weight update block for providing the updated weight vector Wmw based on a scaling factor M, the weight vector W old' the error signal e(k-3) and the data vector X(k3).

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:

Fig. 1 shows a schematic block diagram of a conventional digital VCR system for explaining a Partial Response class-IV method; Fig. 2 illustrates a conventional equalizer for use in a digital VCR adopting the PRML technique; and Fig. 3 presents an adaptive equalizer in accordance with the present invention for use in a digital VCR.

Referring to Fig. 3, there is shown an adaptive equalizer 300 in accordance with the present invention, comprising a feedforward filter 310, delays 320, 340 and 370, a signal level decision block 330, an error detection block 350 and a - 9 weight update block 360. The feedforward filter 310 filters a digital data stream {x(k) fed thereto from theA/D convertor 200 shown in Fig. 2 to output an equalized data stream {y(k)}, n being an index representing the order of the digital data signal. The feedforward filter 310 includes a shift register 312 and a matrix product & sum block 314. The shift reri:ster 312 shifts the digital data stream {x(k)} according to a number of predetermined taps thereof based on the sampling clock fed from the sampling clock generation block 260 shown in Fig. 2; and provides data vectors X(k) and X(k-3) to the matrix product & sum block 314 and the weight update block 360, respectively. The respective data vectors X(k) and X(k-3) have N components and can be defined as X(k)=[x(k), x(k-1), ---, x(k-N+1)l and X(k-3)=[x(k-3), x(k-4), x(k-N-2)l X(k) = [x(k),x(k-1),.-.,x(k-N+1) X(k-3) = [x(k-3),x(k-4),--.,x(k-N-2)l (Eq. 6).

The matrix product & sum block 314 generates the equalized data signal y(k) by manipulating a weight vector W oLd fed from the delay 370 and the data vector XW according to Eq. 1 or 2, wherein W old also has N components as defined, e.g., in Eq. 3. And then, the equalized data signal y(k) is transmitted to the delay 320, the Viterbi decoder 240 and the sampling clock generation block 260 shown in Fig. 2. In the delay 320, the equalized data signal y(k) is delayed by one sampling clock period and an equalized data signal y(k-1) is - 10 provided to the signal level decision block 330 and the delay 340. The delay 340 stores the equalized data signal y(k-1) and transmits an equalized data signal y(k-2) to the error detection block 350.

The signal level decision block 330 includes a level decider 332 and a delay 334. After receiving the equalized data signal y(k-1), the level decider 332 determines to which one of predetermined values, e.g.., ternary values of -1, 0 and 1, the equalized data signal y(k-1) corresponds, thereby generating a 3-level decision signal d(k-1) in a similar manner as in the signal level decider 228 shown in Fig. 2.

The 3-level decision signal d(k-1) is transmitted to the delay 334, which stores the decision signal d(k-1) and provides a decision signal d(k-2) to the error detection block 350.

The error detection block 350 receives the decision signal d(k-2) from the signal level decision block 330 and the equalized data signal y(k-2) from the delay 340. The error detection block 350 includes a subtracter 352 and a delay 354.

After receiving the decision signal d(k-2) having a value of, e.g., -1, 0, or 1, and the equalized data signal y(k-2), the subtracter 352 generates an error signal e(k-2) by computing the difference between the received signals. The error signal e(k-2) is defined as:

e(k-2) = d(k-2)-y(k-2) (Eq. 7).

The error signal e(k-2) from the subtracter 352is transmitted to the delay 354. The delay 354 delays the error 11 - signal e (k-2) by one sampling, clock period and generates a delayed error signal e(k-3) to the weight update block 360 and the sampling clock generation block 260.

The weight update block 360 includes a matrix product block 362 and a matrix sum block 364. The matrix product block 362 receives the error signal e(k-3) from the error detectiorl block 350, a scaling factor p from, e.g., a main control unit (not shown) and the data vector X(k-3) from the shift register 312. Thereafter, the matrix product block 362 performs the multiplication of the received signals and the scaling factor. The matrix sum block 364, responsive to the old weight vector W oLd from the delay 370 and the multiplication result from the matrix product block 362, calculates a new weight vector Wnew The new weight vector Wnew can be defined as:

Wnew = W.1d+11.e(k3).X(k-3) (Eq. 8).

The new weight value Wnew 'S transmitted f rom the weight update block 360 to the delay 370 and is delayed therein by one sampling clock period. The delayed Wnew is provided to the matrix product & sum block 314 and the matrix sum block 364 as an old weight vector W oLd at the subsequent sampling clock.

In accordance with the present invention, the new weight vector Wnew 'S obtained based on the error signal e(k-3), allowing each of the steps of computing y(k), d(k-1), e(k-2) and Wnew to be carried out one sampling clock period.

While the present invention has been described with - 12 respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

13 - cl I M-R 1. A method for equalizing a digital data stream {x(k)} based on a weight vector W otd having N components and a previously equalized data signal y(k-3), k being index representing a sequence of data, comprising the steps of:

(a) -deciding a level of the previously equalized data signal y(k-3) to thereby provide a decision signal d(k-3) having one of predetermined values; (b) deciding an error signal e(k-3) by subtracting the previously equalized data signal y(k-3) from the decision signal d(k-3); (c) generating data vectors X(k) and X(k-3) both having N components f rom the digital data stream, wherein X (k) = [x (k) x(k-1), -, x(k-N+1) 1 and X(k-3) = [x(k-3), x(k-4), ---, x(k-N-2)l (d) providing an equalized data signal y(k) based on the weight vector W oLd and the data vector X(k); (e) generating an updated weight vector Wnew based on the weight vector W,,,, the error signal e (k-3) and the data vector X(k-3); (f) increasing k by 1 and setting Wnew as Wold; and (g) repeating the steps (a) to (f) for the rest of the digital data stream {x(k)}.

2. The method according to claim predetermined values are ternary values.

14 wherein the 3. The method according to claim 2, wherein the ternary values are -1, 0 and 1.

4. The method according to claim 3, wherein the equalized data signal y(k) is defined as:

M-1 y(k) =E.wix(k-i) 1=0 wherein w, is a component of the weight vector W old 5. The method according to claim 4, wherein a scaling factor g is employed in generating the updated weight vector Wnew.

6. The method according to claim 5, wherein the updated weight vector Wnew is defined as:

Wnew = Wold+;'l-e(k3).X(k-3).

7. An apparatus having an equalizer for equalizing a digital data stream, comprising: a first delay for storing an updated weight vector Wnew and providing a previously stored weight vector as a weight vector W old; a weight vector having N components; means, responsive to the digital data stream, for generating a first and a second data vectors X(k) and X(k-3) both having N components and providing an equalized data - is is signal y(k) based on the first data vector X (k) and the weight vector Wotd' X(k) and X(k3) being [x(k), x(k-1), -, x(k-N+1)l and [x(k-3), x(k- 4),..., x(k-N-2)1, respectively; a second delay for storing the equalized data signal y(k) and providing an equalized data signal y(kl) previously stored therein; a third delay for storing the equalized data signal y(k 1) and providing an equalized data-signal y(k-2) previously stored therein; means for converting the equalized data signal y(k-1) into a decision signal d(k-1) and providing a previously converted decision signal d(k-2), a decision signal having one of predetermined values; means for detecting an error signal e(k-2) by obtaining the difference between the decision signal d(k-2) and the equalized data signal y(k-2) and providing a previously detected error signal e(k-3); and means for providing the updated weight vector Wnew based on a scaling factor g, the weight vector W old' the error signal e(k-3) and the data vector X(k3).

8. The apparatus according to claim 7, wherein the generating means includes: a shift register for providing the data vectors X(k) and X(k3); and means for obtaining the equalized data signal y(k) based - 16 on the data vector X(k) and the weight vector W old 9. The apparatus according to claim 8, wherein the converting means includes:

means for deciding a level of the equalized data signal y(k-1) to provide the decision signal d(k-1); and a f durth delay f or storing the decision signal d (k- 1) and providing the previously stored decision signal d(k-2).

10. The apparatus according to claim 9, wherein the detecting means includes:

a subtracter for subtracting the equalized data signal y(k-2) from the decision signal d(k-2) to provide the error signal e(k-2); and a fifth delay for storing the error signal e(k-2) and providing the previously stored error signal e(k-3).

11. The apparatus according to claim 10, wherein the providing means includes: multiplying means for generating the multiplication result of the scaling factor g, the error signal e(k-3) and the data vector X (k-3); and summation means for finding the updated weight vector Wnew based on the weight vector Wold and the multiplication result.

12. The apparatus according to claim 11, wherein the 17 - predetermined values are ternary values.

13. The apparatus according to claim 12, wherein the apparatus is a digital video cassette recorder.

14. A method for equalizing a digital data stream substantially as herein described with reference to or as shown in Figure 3 of accompanying drawings.

15. An apparatus for equalizing a digital data stream constructed and arranged substantially as herein described with reference to or as shown in Figure 3 of accompanying drawings.

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