JPH10275423A - Waveform equalizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase in the error rate of the channel signals of digital data by holding the tap coefficient corresponding to individual magnetic head in accordance with the head switching against the signals of the respective channel reproduced by magnetic heads having different characteristics and coducting a waveform equalizing operation with the tap coefficient of the corresponding channel signals. SOLUTION: Latch pulses are generated based on DFF signals and supplied to a latch circuit 43 and a switch 44. When the signal value is updated in the circuit 43, the switch 4 is switched to a (b) terminal side and an LPF integrates the multiplication result of a multiplier and outputs the signals. The LPF executes a converging operation by the signal value, which is held till the circuit 43 is updated, as the initial value of a tap coefficient. In other words, the initial value of the tap coefficient of the waveform equlization is switched for each channel signals which are reproduced based on the period of the DFF signals and the waveform equalization operation is converged toward the converging value of the tap coefficient in accordance with the characteristics of plural reproduced signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalization circuit suitable for a digital information signal recording / reproducing apparatus.
The present invention relates to a waveform equalization circuit that prevents a coefficient from diverging due to an increase in determination errors.

[0002]

2. Description of the Related Art Transversal filters have been used as circuits for equalizing the waveform of a transmitted digital information signal. The basic configuration of this filter is such that the tap coefficient of the delay element having a delay between taps equal to the signal period is automatically controlled by the estimation control unit. The filter has a characteristic that it is basically stable because it is a non-recursive type.

In the above-mentioned transversal filter, provisional decision means for discriminating a reproduced digital information signal, error calculation means for outputting an amplitude error based on the result of the provisional decision, and signal value outputted from the transversal filter are provided. A holding selecting means for holding and selecting the update, multiplying the amplitude error output from the temporary determining means by the signal value output from the holding selecting means, and updating the tap coefficient of the transversal filter based on the result. Means to obtain a reliable information signal without the reproduced digital information signal converging to an erroneous value, whereby the convergence of the coefficient is delayed or the number of decision errors increases according to the characteristics of the reproduced signal. The applicant has proposed a waveform equalizing circuit (Japanese Patent Application No. 8-307411) for preventing the coefficient from diverging due to the above.

By the way, for example, a helical scan type V
When a reproduction signal is obtained from a plurality of magnetic heads mounted on a rotating drum on which a magnetic tape is wound like a TR, the characteristics of the reproduction signal vary depending on the characteristics of the individual magnetic head. The VTR performs various kinds of signal processing at the time of reproduction, corrects variations in characteristics of the reproduction signal reproduced by each head, and reproduces the reproduction signal as a continuous signal.

When the reproduced signal is a digital signal, it is considered that a signal reproduced by each magnetic head having a variation in characteristics is subjected to waveform equalization by the transversal filter. For example, when performing waveform equalization of digital signals reproduced by magnetic heads having different azimuth angles from each other, the level of the reproduced digital signals may differ according to the characteristics of each head. To make the waveform equalization operation converge.

[0006]

For example, a magnetic head having different azimuth angles is mounted on a rotating drum at a position opposite to each other by 180 °, and a digital information signal recorded from a magnetic tape wound on the rotating head is mounted. , The tap coefficients for converging waveform equalization vary as shown in FIG. Here, the DFF signal is a signal corresponding to the rotation period of the rotating drum. When "H", one magnetic head reproduces a signal (channel A: CH-A), and when "L", the other magnetic head reproduces the signal. Play the signal (channel B: CH-B).

At this time, since the tap coefficient to be converged to equalize the waveform of the reproduced signal differs depending on the characteristics of the reproduced signal, that is, the characteristics of each magnetic head, FIG.
As shown in (1), there is a problem that the convergence takes time and the operation of waveform equalization is not stable. In particular, as shown in FIG. 4 (i) (where signals of respective channels are started to be reproduced by magnetic heads having different characteristics), it takes time to converge the coefficient of waveform equalization, and the error rate of the digital data in this part Is increased. For example, the portion (i) in FIG. 4 described above corresponds to the head of data in terms of a track on a magnetic tape, and corresponds to a position where various subcodes, identification information, and the like are recorded in some systems. An increase in the error rate of a portion becomes a major obstacle to detection of subcodes and identification information.

On the other hand, it is conceivable to suppress the error rate by shortening the convergence time of the tap coefficient by increasing the response of the waveform equalization filter. However, if the response of the filter is too fast, noise can be reduced. There is a problem that noise is increased by performing equalization processing.

[0009]

Accordingly, the present invention provides the following configurations (1) and (2) to solve the above-mentioned problems. (1) A first aspect of the present invention is to provide a digital information signal in which delayed outputs of a digital information signal in which data of a plurality of channels are transmitted alternately are weighted and multiplied by a plurality of tap coefficients which are adaptively controlled. In a waveform equalization circuit using a transversal type filter for suppressing intersymbol interference of an information signal, it is most probable from the output of the transversal type filter by the maximum likelihood detection using the correlation of the signal component of the digital information signal. A temporary discriminating means (temporary discriminating circuit) B for temporarily discriminating digital information; an error calculating means (error calculating circuit) C for outputting a value corresponding to an amplitude error based on a temporary discrimination result of the temporary discriminating circuit B; Holding selection means (holding selection circuit) D for holding and selecting the information signal and its delay signal, respectively;
The amplitude error output from the error calculation circuit C and the holding selection circuit D
Updating means (multipliers 31 to 35, LPFs 36 to 40) for multiplying the signal value output from the multiplying device and updating the tap coefficients of the transversal filter based on the multiplication result. When the signal channel is alternately switched, the updating means (LPFs 36 to 40)
Holds the tap coefficients obtained in accordance with the digital information signal of each channel to be switched, and updates the tap coefficients of the filter to the coefficients corresponding to the channel among the held tap coefficients in accordance with the switching of the channel. There is provided a waveform equalization circuit characterized by the above.

(2) The second invention is characterized in that the digital information signals of the plurality of channels are signals reproduced by a plurality of magnetic heads (H), and the waveform equalization according to the above (1). Provide a circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram for explaining a waveform equalizing circuit according to the present invention, FIG. 2 is a diagram for explaining an LPF which is a main part of the present invention, and FIG. It is a figure explaining the state of convergence of a tap coefficient. Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same components as those described above are denoted by the same reference numerals, and description thereof will be omitted.

For example, as shown in FIG. 1, a magnetic head H (for example,
A magnetic head having at least a mutually different azimuth angle is mounted at a position facing 180 ° on the drum). A signal obtained by scanning the magnetic tape T is obtained by a preamplifier 1, a filter 2, an A / D converter 3, a DC The signal is supplied to the waveform equalizing circuit A of the present invention via the removing circuit 4 and the like.

As shown in FIG. 1, the waveform equalization circuit A
Delay circuits 11 to sequentially delay the supplied reproduction signal by a predetermined amount
14, a holding and selecting circuit D for holding the respective delay outputs of the delay circuits 11 to 14, an adder 20 for adding the reproduction signal and the respective delay outputs of the delay circuits 11 to 14 via multipliers 15 to 19, and an adder 20
Tentative judgment circuit B for judging the digital signal value from the output of
An error calculating circuit C for outputting an amplitude error between the expected value and the actual signal based on the temporary determining result from the temporary determining circuit B;
Multipliers 31-35, which multiply the amplitude error from
LPFs 36 to 40 which integrate the output of 35 to output low frequency components and supply them to the multipliers 15 to 19 described above.
The arithmetic units 15 to 19 supply the multiplication results of the outputs of the LPFs 36 to 40 and the outputs of the delay circuits 11 to 14 to the adder 20.

Although not shown here, in the waveform equalization circuit A, the reproduced signal, its delay output, and the holding selection circuit D
And a delay element for absorbing a delay caused by an amplitude error due to signal processing.

The adder 20 supplies the output information signal to a temporary discriminating circuit B together with a transmission line (not shown). A transmission line (not shown) is composed of a digital signal processing circuit or the like.
Performs value judgment, corrects the error of the determined digital signal,
A reproduction process such as deshuffling is performed to restore information such as video and audio included in the reproduced digital information signal.

On the other hand, the output of the transversal filter from the adder 20 is supplied to a provisional decision circuit B. The provisional determination circuit B as a provisional determination means compares the supplied information signal with a threshold value determined by a past sampling value, and calculates "+
One of “1”, “0”, and “−1” is provisionally determined. Then, a switching control signal is generated based on the result of the provisional determination and supplied to the error calculation circuit C. The error calculation circuit C includes, for example, a three-level level determination circuit (not shown), a subtractor, and a latch circuit. Either the output of the latch circuit or the output of the subtractor is switched and output based on the control signal described above.

By the way, the provisional decision circuit B converts the output signal of the adder 20 into, for example, a multi-valued digital information signal (“-
1 "," 0 ", and" 1 "), and supplies a switching signal corresponding to the determination to the error calculation circuit C and a control signal to the holding selection circuit D, respectively. The error calculation circuit C calculates and holds how much the digital information signal has an amplitude error from an ideal value with respect to the signal from the adder 20. Then, the error signal held based on the switching signal from the temporary determination circuit B is supplied to the multipliers 31 to 35, respectively.

Here, the above-mentioned provisional determination circuit B is, for example,
As described in Japanese Patent Application No. 8-307411 proposed by the present applicant, the value of the most probable digital information signal is provisionally discriminated by a discrimination applying a maximum likelihood detection algorithm, and the discriminated value is determined. The switching signal is supplied to the error calculation circuit C so as to output a corresponding error signal.

As described above, in the level determination circuit constituting the error calculation circuit C, ideal signal level values of "1", "0", and "-1" of the digital information signal to be reproduced are set. This level and the level of the supplied signal are subjected to subtraction processing by a subtracter (not shown). The obtained difference is latched as an error level value by the above-described latch circuit in accordance with the timing of a predetermined sampling clock. The output of the latch circuit is supplied to a changeover switch (not shown), and is switched and output based on a changeover signal from the provisional determination circuit B.

On the other hand, the reproduction signal supplied to the waveform equalization circuit A is supplied to the hold selection circuit D via the delay circuits 11 to 14. Although not shown here, the holding and selecting circuit D includes a plurality of latch circuits and a changeover switch.
For example, the reproduction signal is supplied to a latch circuit and a changeover switch, and the operation is controlled by the above-described provisional determination circuit B, respectively. The latch circuit forming the holding selection circuit D is output in synchronization with the output of the latch circuit of the error calculation circuit C.
When the error signal is passed through the error calculation circuit C, the signal supplied to the holding and selecting circuit D is similarly output through.

For example, when a digital information signal passes through a magnetic recording / reproducing system of a partial response system, a value of "1" or "-1" is not continuously detected in a reproduced signal due to intersymbol interference. This is because the digital information signal is obtained via the transmission characteristic of (1-D) ^2. According to this characteristic, when the value of "1" or "-1" continues, the most likely " When the value of "1" or "-1" is detected, the other value can be regarded as noise, so that the amplitude error of the signal that is regarded as noise at that time can be output through.

The above-described reproduction signal and delay circuits 11 to 14
Is supplied to the holding / selecting circuit D via a delay element (not shown) in order to absorb a delay error from an amplitude error caused by a signal delay as described above.

When the error level value of the digital information signal is output from the error calculation circuit C, the signal held by the latch circuit which latches the signal value of the corresponding waveform based on the control signal from the temporary determination circuit B At the same time, and the changeover switch supplies the signal to the multipliers 31 to 35 at the same time. Multipliers 31 to 35 multiply the signal from holding and selecting circuit D by the error level value from error calculating circuit C, and output the result to LPF 36
Supply to ~ 40. The LPFs 36 to 40 integrate the supplied signals to output low frequency components, and feed back the low frequency components to the multipliers 15 to 19 as tap coefficients.

Now, the configuration of the LPFs 36 to 40, which are main parts of the present invention, will be described. For example, as shown in FIG. 2, the LPF 36 includes an adder 41 that adds the output of the multiplier 35 and the output of the present LPF, a limiter 42 that controls the level of the adder 41, and a latch that latches the output of the limiter 42. Circuit 43, limiter 42
And a latch circuit 45 for latching the output of the switch 44. The LPFs 37 to 40 have the same configuration. here,
A latch pulse generated based on the above-mentioned DFF signal is supplied to the latch circuit 43 and the switch 44, whereby the latch operation and output switching are controlled.

The multiplication result from the multiplier 35 is supplied to a latch circuit 43 and a switch 44 via an adder 41 and a limiter 42, respectively. The switch 44 normally selects the b-side terminal for output, and its output signal is supplied to the multiplier 15 and the adder 41 via the latch circuit 45 as an LPF output. Adder 41
Is integrated by feeding back the LPF output to the multiplication result of the multiplier 35 and adding it to the error signal from the error calculation circuit C. Further, the latch circuit 45 synchronizes the timing of sampling data (in this case, the above-described error signal) integrated based on the system clock of the present waveform equalization circuit formed of a digital circuit, for example.

Next, a latch pulse is generated based on the rise and fall of the DFF signal and supplied to the latch circuit 43 and the switch 44, respectively. Latch circuit
Reference numeral 43 updates the signal value held up to that time based on the latch pulse to the signal value supplied from the limiter 42 and holds the signal value. The switch 44 selects the output of the terminal a based on the latch pulse, and outputs the signal value before the latch circuit 43 updates.

When the signal value is updated in the latch circuit 43, the switch 44 is switched to the terminal b, and the LPF 36 is again switched to the multiplier.
Integrate and output the multiplication result of 35. However, the LPF 36 performs a convergence operation using the signal value held immediately before the update of the latch circuit 43 as the initial value of the tap coefficient. That is, the initial value of the tap coefficient for waveform equalization is switched for each channel signal reproduced based on the cycle of the DFF signal.
As shown in (1), the waveform equalization operation can converge toward the convergence value of the tap coefficient corresponding to the characteristics of the plurality of reproduction signals (each head).

As described above, each channel signal is a reproduction signal from an individual magnetic head H, and the waveform is equalized by switching to the tap coefficient for each channel according to the switching of the channel. Waveform equalization according to the characteristics of the magnetic head can be performed. For this reason,
The convergence operation of the tap coefficients can be performed stably, and the increase in the error rate of digital data can be suppressed. The LPFs 37 to 40 perform the same processing as described above on the multiplication results of the multipliers 31 to 34.

In the multipliers 15 to 19, the multiplication result of the error level value and the signal value output from the holding and selecting circuit D is converted into an LPF 36.
By calculating the tap coefficient obtained by integrating through 40 and the delay output of the reproduced digital information signal, a reproduced digital information signal weighted by the tap coefficient can be obtained. The information signal is equalized to a more likely waveform.

In this way, in the waveform equalizing circuit A, the discriminating means B discriminates the value of the reproduced digital information signal and detects how much the value has an error with respect to a predetermined level. Is multiplied by the value output by the holding and selecting circuit D, the reproduced digital information signal can be waveform-equalized while distinguishing the likely digital information signal value from noise.

Here, the timing at which the amplitude error is output varies depending on the input signal. However, since the LPFs 36 to 40 perform a sufficiently long integration process, there is no problem even if the data is fixed before or after the clock. Also, at the initial stage of the convergence process, it is difficult to completely distinguish everything,
By performing stochastic correct discrimination, coefficient data for waveform equalization converges to a correct value, so that it is possible to prevent divergence of data.

In the present waveform equalization circuit, the convergence of the waveform equalization is made faster by discriminating a likely reproduced digital information signal from a digital information signal reproduced from a recording / reproducing apparatus such as a digital VTR. The effect is that the range can be expanded. Further, since the present waveform equalizing circuit can be constituted almost entirely by digital circuits, there is an effect that there is almost no variation in characteristics and a stable operation can be secured.

It is needless to say that the waveform equalization circuit may be used in combination with a prefilter or the like including the above-described adjustment equalizer to perform more accurate waveform equalization. . And then, as mentioned above,
Of course, the tap coefficients of the pre-filter may be automatically determined using the tap coefficients of the waveform equalization circuit.

The waveform equalizing circuit is a recording / reproducing apparatus for recording / reproducing a digital information signal on / from a magnetic tape wound on a rotating drum by a magnetic head mounted on the rotating drum, such as a digital VTR. It is assumed that waveform equalization of a signal reproduced in the apparatus is performed. However, the above-described method is used if digital information signals reproduced from a plurality of magnetic heads having different characteristics are alternately switched to obtain one continuous signal. Of course, it is not limited to media.

It is needless to say that the present waveform equalization circuit may be used together with, for example, the above-mentioned Viterbi decoding circuit to obtain a more reliable reproduced digital information signal.

In the present waveform equalizing circuit, the signal operation of a transversal filter such as a multiplier for updating tap coefficients based on the error level of the reproduced digital information signal is performed as follows.
Since the conventional configuration can be used, the operation control of the entire waveform equalization circuit is not complicated as compared with the conventional case.

The transversal filter described in the embodiment of the present invention forms a feedback loop of negative feedback. Although not shown, an inverter for inverting an output from the error calculation circuit C is provided. It is needless to say that a reversing means such as the above is provided.

[0038]

According to the present invention, for example, with respect to signals of respective channels reproduced by magnetic heads having different characteristics, tap coefficients corresponding to individual magnetic heads are held in accordance with switching of the heads. Performing the waveform equalization operation using the tap coefficient of the corresponding channel signal has the effect of preventing an increase in the error rate of the channel signal composed of digital data.

Further, according to the present invention, since a waveform equalization circuit having an excessively fast response is not used, noise does not increase due to waveform equalization, so that highly accurate waveform equalization can be performed. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a waveform equalization circuit according to the present invention.

FIG. 2 is a diagram for explaining an LPF that is a main part of the present invention.

FIG. 3 is a diagram for explaining a state of convergence of tap coefficients by the present waveform equalization circuit.

FIG. 4 is a diagram for explaining a state of convergence of tap coefficients by a conventional waveform equalization circuit.

[Explanation of symbols]

A: Waveform equalization circuit, B: Temporary judgment circuit (temporary judgment means), C
... holding selection circuit (holding selection means), 31-40 ... updating means (multipliers 31-35, LPFs 36-40).

Claims (2)

[Claims] 1. A digital information signal having a plurality of channels, wherein the delayed outputs of the digital information signals transmitted alternately are weighted by multiplication by a plurality of tap coefficients, each of which is adaptively controlled. In a waveform equalization circuit using a transversal type filter for suppressing inter-interference, the most probable digital information is output from the output of the transversal type filter by the maximum likelihood detection using the correlation of the signal components of the digital information signal. Temporary determining means for determining, an error calculating means for outputting a value corresponding to an amplitude error based on a temporary determination result of the temporary determining means, holding selecting means for holding and selecting the digital information signal and its delay signal, Multiply the amplitude error output from the error calculation means and the signal value output from the holding selection means, Updating means for updating the tap coefficient of the transversal filter based on the result, wherein when the channels of the digital information signal composed of a plurality of channels are alternately switched, the updating means comprises: Waveform equalization characterized by holding a tap coefficient obtained in accordance with a digital information signal and updating a tap coefficient of the filter to a coefficient corresponding to the channel among the held tap coefficients in accordance with switching of a channel. circuit. 2. The waveform equalizing circuit according to claim 1, wherein the digital information signals of the plurality of channels are signals reproduced by a plurality of magnetic heads.