JPH11167772A - Asynchronous data detecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve equalization performance by controlling the output for a binary data value BD showing a final existence route with a system clock signal CLK and a data output clock signal CLK1 of the same frequency as a prescribed recording frequency PRF and making them the final output data. SOLUTION: An equalization part 400 equalizes an interpolation sample value IS with the CLK, and supplies an equalized sample value ES to a data detection part 600, and an error signal E to a timing reproducing circuit 800. The data detection part 600 data detects for the ES according to the CLK, and supplies the BD obtained by existence route detection to an output control part 700, and further, the data detection part 600 supplies a decision value showing an existence route of the number of prescribed pieces to the timing reproducing circuit 800 as the set <DV> of the decision value. The circuit 800 performs timing reproduction for obtaining a phase error signal PE with the <DV> and E according to the CLK to supply it to an interpolation circuit 300. On the other hand, an output control part 700 output controls for the BD with a hold signal H, the CLK and the CLK1 to output the final output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data detecting device used in a magnetic recording / reproducing system, and more particularly to an asynchronous data detecting device used in the system.

[0002]

2. Description of the Related Art Analog base recording / playback techniques have been used for a long time in conventional magnetic recording / playback systems such as video cassette recorders (VCRs). When reproducing an image recorded in analog form using a conventional magnetic recording / reproducing system, the image quality of the image may be significantly degraded.

For example, when a conventional VCR using an analog recording / reproducing technique operates in a reproducing mode, a signal distorted by noise or jitter is directly transmitted from the VCR. Further, when an editing or other operation is performed, the distortion is accumulated, thereby further deteriorating the image quality of the reproduced video. Therefore, in order to overcome the disadvantages of the analog VCR described above, a VCR using a digital recording / reproducing technique (“Digital VC”) is used.
R ") has been proposed.

In a recording mode in a conventional digital VCR, the encoded and modulated analog video and audio signals are sampled and converted into discrete quantized digital values, which are then typically represented by a digital VCR. Is recorded on a magnetic tape used as a typical data storage medium.

In a reproduction mode of a conventional digital VCR, a change in magnetic flux induced by a read element of a magnetic head is supplied to a preamplifier as an analog signal. The preamplifier pre-amplifies the analog signal to a predetermined level to generate an analog reproduced signal.

Thereafter, an analog / digital (A / D) converter in the digital VCR converts the analog reproduction signal into a digital reproduction signal at a predetermined channel speed. The digital reproduction signal is transmitted to a digital data processing channel of a digital VCR, and data detection and processing are performed.

However, in the process of detecting and transmitting digital data, intersymbol interference (integer) caused by high-speed data transmission through a channel having a limited bandwidth is required.
r-symbol interference; IS
Channel-induced signal distortion such as I) often occurs. This ISI causes a disturbance to the data transmission, thereby causing transmission errors. In the art, partial response maximum likelihood (parti likelihood) is used to correct for such ISI.
al response maximum likel
ihod; PRML) method is known as the most effective method.

For this reason, a conventional digital VCR usually includes a data detecting device provided with an equalizing circuit, and the equalizing circuit converts a digital reproduced signal into an equalized signal (eg,
It has a filter for equalizing to a partial response class 4 (PR4) signal. For example, a discrete-time finite impulse response (FIR) filter receives sample values of a digital reproduction signal and equalizes them to a predetermined spectrum using a so-called PRML method. Here, the discrete time transfer function used in the PRML method is typically (1-D ² ), where D represents a unit time delay operator.

In the PRML method, the output from a noise partial response channel is sampled at a predetermined channel rate and detected by a PRML detector. Normally, the maximum likelihood sequence detection (MLSD; maximum likelihood) of the sampled partial response channel is performed by the Viterbi detector.
ihood sequence detection)
It is used at the time of.

[0010] The Viterbi algorithm, which is well known in the art, is a process of tracing and finding the path with the smallest accumulated metric for each state of the trellis.

More specifically, the Viterbi algorithm calculates and compares the metrics of all routes leading to a specific state, and selects a route having the smallest metric as a survivor path. In this way, all paths that can be the smallest metric path through the trellis are stored in the path memory.

If the path memory is long enough, all existing paths will converge to a single path within the path memory. In this way, the corresponding decision value (Decision v
A single path, which converges all the current existence paths, expressed as the last existing path, is selected as the path having the minimum metric as the final existence path. The input sequence for this minimum metric path is a binary data value (Bi
(nary data value: BD) appears in all outputs of the Viterbi detector.

FIG. 1 is a block diagram of an asynchronous data detector 30 for explaining the structure and function of a conventional data detector used in a magnetic recording / reproducing system.
The asynchronous data detector 30 includes an analog / digital (A / D) converter 31, an interpolator 32, an equalizer 33,
Data detector 34, timing recovery circuit 36, system clock signal (System Clock Signa)
l: CLK) generator 37 is included.

The magnetic recording / reproducing system includes a magnetic head (not shown) having a reading section (not shown).
The data detecting device 30 converts the magnetic flux change induced from the magnetic recording medium by the reading unit of the magnetic head into an analog signal reproduced signal obtained by pre-amplifying the magnetic flux change by a predetermined level.
Detect value data value.

[0015] The digital data is stored at a predetermined recording frequency (Predetermined Recordi).
ng Frequency (PRF), for example, 41.
Note that a predetermined level is recorded on the magnetic recording medium by 85 MHz.

In the data detection device 30, first, an analog reproduction signal is input to the A / D converter 31. The A / D converter 31 samples and converts an analog reproduction signal as a sample value S into digital reproduction data according to the CLK input from the CLK generator 37 (for example, a memory control unit in a magnetic recording / reproducing system). I do. This sample value S is input to the interpolator 32 through the line L2. CLK is the A / D converter 3
1, are input to the equalizer 33, the data detector 34, and the timing recovery circuit 36, respectively.

In the asynchronous data detector 30, C
If S is generated in A / D converter 31 under conditions where the frequency of LK is greater than the PRF, interpolator 32 operates in asynchronous mode, so S is considered as asynchronous data and the frequency of CLK is S is A /
Note that when generated by the D converter 31, the interpolator 32 operates in a synchronous mode, and thus S is considered as synchronous data.

The interpolator 32 outputs a predetermined phase error signal (P) input from the timing recovery circuit 36 in accordance with CLK.
By performing interpolation filtering on S based on E), the interpolation sample value (I
S) is supplied to the equalizer 33.

The interpolator 32 calculates P
Referring to E, when a predetermined holding condition is satisfied,
A hold signal (H) is generated according to CLK. It should be noted that the interpolator 32 generally generates H when the asynchronous data detector 30 operates in the asynchronous mode.

More specifically, in the synchronous mode, the interpolator 32 supplies S as an interpolated sample value (IS) to the equalizer 33 via the line L3 according to CLK. Also,
In the interpolator 32, the IS is set to one data detection time interval (Data-detection Delay Time).
e Interval: DDTI)
The IS pre-stored in that memory is replaced with the IS delayed by 1 DDTI.

In the asynchronous mode, the interpolator 32 first determines S as asynchronous data based on the previously determined PE, thereby taking out the pre-stored IS in its memory as IS according to CLK. , And supplies the IS to the equalizer 33 through the line L3. At the same time, the interpolator 32 refers to the PE obtained in advance,
When the predetermined holding condition is satisfied, H is generated and then supplied to the equalizer 33, the data detector 34, and the timing recovery circuit 36, respectively.

The equalizer 33 performs equalization on IS using a predetermined equalization technique in accordance with the CLK input from the CLK generator 37, and thereby outputs an equalized sample value (EP) through a line L5. ) To the data detector. Thereafter, the equalizer 33 supplies the error signal (E) to the timing recovery circuit 36 via the line L4. here,
E represents an error between a filtering data value obtained by performing finite response filtering on the IS and a level determination value obtained by performing a conventional level determination on the filtering data.

The data detector 34 having a Viterbi detector (not shown) performs MLSD on the ES using the CLK to detect the existence path of the ES, thereby obtaining the line L.
A binary data value (BD) representing the final existence path detected through 6 is supplied to a codec system via line L6 for subsequent processing. At the same time, the data detector 34 determines a predetermined number (for example, 2 or 3) of sets of determined values (<DV
>) As the timing recovery circuit 36 through the line L7.
To supply.

The timing recovery circuit 36 supplies the PE to the interpolator 32 through the line L8 by performing the timing recovery for obtaining the PE based on <DV> using a predetermined PE generation technique.

Here, the operation of the equalizer 33, the data detector 34 and the timing recovery circuit 36 is maintained for one DDTI (for example, one clock time interval of CLK) when H is inputted to each of them. Please note that

However, the above-mentioned conventional asynchronous data detector has the following problems. Specifically, in the conventional asynchronous data detection device, the output frequency of the binary data sequence from the data detector does not match the PRF.

That is, the conventional asynchronous data detector is
A mismatch occurs between the data sequence supply frequency to the codec system and the data processing frequency therein. This results in the accumulation of unwanted data output at the data detector, and consequently degrades the performance of the data detection device.

Further, when a large number of holding signals are generated in the interpolation unit for a short time, there is a disadvantage that the performance of the equalization unit is deteriorated. As described above, the conventional synchronous data detection apparatus has many limitations in suppressing accumulation of unnecessary output data and improving its equalization performance.

[0029]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an asynchronous data detecting apparatus used in a magnetic recording / reproducing system and capable of suppressing accumulation of unnecessary data output.

It is another object of the present invention to provide an asynchronous data detecting device used in a magnetic recording / reproducing system for improving the equalization performance.

[0031]

According to the present invention, there is provided, in accordance with the present invention, a magnetic recording / reproducing system including a magnetic head having a read element, the magnetic recording being performed by the read element of the magnetic head. An asynchronous data detection device for detecting a binary data value from an analog reproduction signal obtained by preamplifying a magnetic flux transition induced by a medium by a predetermined level, wherein digital data is predetermined on the magnetic recording medium. First signal generating means for generating a system clock signal (CLK) recorded at a predetermined level by the recording frequency and having a frequency higher than the predetermined recording frequency (PRF);
A second signal generating means for generating a data output clock signal (CLK1) having a frequency equal to RF;
By converting an analog reproduction signal into digital reproduction data in accordance with K and supplying a sample value S, and performing interpolation filtering on S in accordance with the CLK based on a predetermined phase error signal, When an interpolated sample value (IS) is supplied and a predetermined holding condition is satisfied, an interpolation filter means for generating a holding signal (H) and the IS according to the CLK.
By performing equalization on the equalized sample values (E
S) and filtering data obtained by performing finite response filtering on the IS,
Equalizing means for generating an error signal (E) representing an error between a decision value obtained by performing a level decision on the filtered data, and a maximum likelihood sequence detection (Maximum) for the ES according to the CLK. Likelih
wood Sequence Detection: MLS
D) By performing data detection using the technique to detect the existence path, 2 representing the final existence path obtained therefrom
Data detecting means for generating a value data value (BD) and a predetermined number of determined values representing the existence route obtained as a determined value set (<DV>);
Timing recovery means for performing timing recovery to obtain a phase error signal (PE) based on V> and the E, and supplying the PE to the interpolation filtering means;
Using the H, the CLK and the CLK1, the BD
And output control means for supplying final output data by controlling output of the asynchronous data detection apparatus.

[0032]

Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a block diagram of an asynchronous data detector 100 for use in a magnetic recording / reproducing system, such as a digital video cassette recorder (DVCR), according to a preferred embodiment of the present invention.

The magnetic recording / reproducing system includes a magnetic head (not shown) having a read element (not shown).
The asynchronous data detector 100 converts a binary data value from an analog reproduction signal obtained by pre-amplifying a magnetic flux change induced from a magnetic recording medium (for example, a magnetic tape) by a reading element of a magnetic head by a predetermined level. To detect.
Digital data is stored at a predetermined recording frequency (PR
F) Note that, for example, at 41.85 MHz, a predetermined level is pre-recorded on the magnetic recording medium.

According to a preferred embodiment of the present invention, the asynchronous data detector 100 includes an analog / digital (A
/ D) Converter 200, interpolation unit 300, and equalization unit 400
, A data detection unit 600, an output control unit 700, and a timing reproduction circuit 800.

Further, the asynchronous data detecting device 100
A CLK signal generator 900 (e.g., a memory control unit in the system) for generating a system clock signal (CLK); a CLK1 generator 950 (e.g., a central processing unit (CPU)) for generating a data output clock signal (CLK1). including. Note that the frequency of CLK (eg, 41.85 + α MHz (α> 0)) is greater than the frequency of CLK1, and that the frequency of CLK1 is equal to the PRF.

According to another embodiment of the present invention, the asynchronous data detecting device 100 further includes a weight control unit 500.

CLK is output from the A / D converter 200 and the interpolation unit 3
00, the equalizer 400, the data detector 600, the output controller 700, and the timing recovery circuit 800. C
LK1 is input to the output control unit 700. According to a preferred embodiment of the present invention, CLK1 is also provided to a codec system (not shown) for subsequent processing.

The A / D converter 200 converts the analog reproduction signal into digital reproduction data according to the CLK, and supplies the sample value S to the interpolation unit 300 via the line L10.

The interpolation section 300 performs interpolation filtering on S based on a previously obtained phase error signal input from the timing reproduction circuit 800 through the line L20 in response to CLK, thereby obtaining the interpolated sample value (Interpolated Sample value).
e: IS) to the equalizer 400 via the line L11, and generates a holding signal H when a predetermined holding condition is satisfied.

Here, when H is generated by the interpolation unit 300, H is equalized by the equalizer 400, the weighted controller 500,
Note that the data is supplied to the data detector 600, the output controller 700, and the timing recovery circuit 800.

The equalizing section 400 performs equalization on IS using a predetermined quantization technique based on the CLK, and thereby the equalized sample value E through a line L13.
S to the data detection unit 600 and the line L1
2, the error signal E is supplied to the timing reproduction circuit 800. Here, it should be noted that E represents an error between a filtered data value obtained by performing finite response filtering on IS and a level determined value obtained by performing level determination on the filtered data. .

The data detection unit 600 detects the existence path by performing data detection on the ES using the maximum likelihood sequence detection (MLSD) technique according to the CLK.
The obtained binary data value BD representing the last existence path is supplied to the output control unit 700 via the line L16,
The determined value representing the predetermined number of existence paths obtained therefrom is
It is supplied to the timing reproduction circuit 800 as a set of determined values (<DV>) through the line L15.

The timing recovery circuit 800 performs a timing recovery for obtaining the phase error signal PE based on <DV> and E according to the CLK by using a predetermined PE generation technique, and outputs the PE through a line L20. To the interpolation unit 3
Supply to 00.

The output control unit 700 has H, CLK, CLK1
To output the final output data FD to the codec system.

In detail, FIG. 3 is a detailed block diagram of the output control unit 700 in the asynchronous data detecting device 100 in FIG. 4 (A) to 4 (K)
4A and 4B are waveform diagrams illustrating an output data sequence and a waveform of a clock signal, respectively, used for explaining the operation of the output control unit 700 in FIG. 3.

Hereinafter, the structure and operation of the output control unit 700 will be described in detail with reference to FIGS. FIG. 4 (A),
The numbers shown in FIGS. 4H and 4K indicate the order of data processing (eg, detection, recording, or reading). Here, the larger the number, the later the processing order. FIG.
Each vertical dotted line in (A) to FIG. 4 (K) represents the same time. In FIG. 4A, FIG. 4H and FIG. 4K, a hatched portion indicates an asynchronous data position processed in each asynchronous mode.

The output control unit 700 includes a data delay unit 71
0, a clock signal update channel 720, an output control signal generation channel 730, and a first-in first-out (FIFO) data output control unit 740. Output control signal generation channel 7
Numeral 30 denotes a delay clock signal (DCS) generator 731 and AN
And a D gate 732.

The data delay section 710 is, for example, a shift register which is used to store a BD in one data detection time interval (Data).
-Detection Delay Time Int
erval: DDT1), and supplies the delay BD to the data input terminal of the FIFO data output control unit 740 via the line L71. FIG. 4A is an output data sequence of the delay BD at the position A indicated by the arrow in FIG.

The clock signal update channel 720 updates CLK by using H, and updates the updated clock signal (MCL).
K) is supplied to the recording input end W of the FIFO data output control unit 740 through the line L72. This MCLK frequency is equal to the frequency of FIG. 4B shows the waveform of CLK at the position B indicated by the arrow. As shown in FIG. 4B, there are thirteen clocks CLK in the time interval T.

The output control signal generation channel 730 has a CL
After generating the output control signal (OCS) using K1, the OCS is supplied to the read control terminal R of the FIFO data output control unit 740 through the line L73.

The clock signal update channel 720 is connected to the first
A delay unit 721, a second delay unit 722, an inverter 723,
A third delay unit 724, a first AND gate 725, a fourth delay unit 726, and a second AND gate 727 are provided. In the clock signal update channel 720, H is the first delay unit 7
21.

The first delay unit 721 supplies the first delay H to the second delay unit 722 and the first input terminal of the first AND gate 725 by, for example, delaying H by 1DDTI as a shift register. FIG. 4C is a waveform diagram of the first delay H at a position C indicated by an arrow in FIG. Referring to FIG. 4A and FIG. 4C, the generation timing of H coincides with the generation timing of the asynchronous data indicated by 0 or 10 in FIG.

On the other hand, CLK is input to the inverter 723 and the second input terminal of the second AND gate 727. The inverter 723 inverts the CLK and outputs the inverted CLK to the second
The signal is supplied to the delay unit 722. The second delay unit 722 includes, for example,
As a shift register, the first delay H is delayed according to the inverted CLK, and the second delay H is supplied to the third delay unit 724.

The third delay unit 724 sets the second delay H at a predetermined time interval (ie, about 1 / clock of one CLK time interval).
6) Supply the third delay H to the second input terminal of the first AND gate 725 with a delay of, for example, 4 nanoseconds. Here, the predetermined time interval is shorter than half of one clock time interval of CLK. FIG. 4D is a waveform diagram showing a third delay H at a position D indicated by an arrow.

The first AND gate 725 performs an AND operation on the first delay H and the third delay H,
The update H is supplied to the fourth delay unit 726. FIG. 4E is a waveform diagram of the update H at the position E indicated by the arrow in FIG.

The fourth delay unit 726 delays the update H by a predetermined time interval, and adds the fourth delay H to the second AND gate 7.
27 to a first input terminal. FIG. 4F is a waveform diagram showing a fourth delay H at a position F indicated by an arrow in FIG.

The second AND gate 727 performs an AND operation on the fourth delay H and CLK, and outputs the MCLK through a line L72 to a FIFO data output controller 740.
Is supplied to the recording input terminal. FIG. 4G is a waveform diagram of MCLK at a position G indicated by an arrow.

In the output control signal generation channel 730, CLK1 is input to a first input terminal of an AND gate 732. FIG. 4I shows a position I indicated by an arrow in FIG.
5 is a diagram showing a waveform of CLK1 in FIG. FIG.
As shown in (I), there are eleven clocks CLK1 in the time interval T. Therefore, FIGS. 4B and 4I
, It can be seen that the frequency of CLK is higher than the frequency of CLK1.

After that, the DCS generator 731 supplies the second input terminal of the AND gate 732 with C C for a predetermined delay time interval.
A DCS is provided that indicates to delay the start time of LK1. FIG. 4J is a waveform diagram of the DCS at the position J indicated by the arrow in FIG.

The AND gate 732 is connected to the CLK1 and DCS
Performs an AND operation on to generate OCS, and then
FIFO data output control unit 740 through line L73
To the read control end of the

The FIFO data output control unit 740 has the OCS
IF to delay BD based on MCLK
By performing O data output control, the FD is supplied to the codec system.

More specifically, the FIFO data output controller 7
At 40, the delay BD is used in response to MCLK and then read by the OCS as an FD. FIG.
(H) shows the write data sequence of the delay BD at the position indicated by DATA in FIG. FIG. 4 (K)
3 shows an FD extraction data sequence at the position indicated by R in FIG.

Here, the equalizer 400 and the data detector 60
0, output control unit 700 and timing recovery circuit 800
Is that when H is input to each, the operation is
Note that it is retained during I.

The weighting control section 500 performs weighting control according to the H, so that a predetermined number or more of Hs are determined in advance on the assumption that the H generated by the interpolation section 300 is input. If it is input within the first time interval, a set <IFCS> of the system reset signal SRS and the initial filter coefficient is generated.

Referring to FIG. 5, there is shown a detailed block diagram of weighted control section 500 in asynchronous data detecting apparatus 100 in FIG.

The weighted control section 500 includes an inverter 51
0, a delay reset signal (DRS) generator 540, an accumulation module 530, a comparator 550, and an <IFCS> generator 560. The accumulation module 530 includes an adder 531
And a delay unit 532. <IFCS> generator 560
Is an address generator 561 and a read-only memory (RO)
M) 562.

The inverter 510 inverts H and supplies the inverted H to the adder 531. The DRS generator 540 generates a DRS periodically during a predetermined second time interval, and supplies the generated DRS to the delay unit 532 through a line L51. Also, DR
The S generator 540 generates a DRS when the SRS is input from the comparator 550, and supplies the DRS to the delay unit 532 through the line L51.

The accumulation module 530 performs an accumulation process using the inverted H, and outputs the accumulated value (ACV) to the line L52.
To the comparator 550. Here, when the DRS is input to the delay unit 532, the delay unit 532 is initialized to set the stored pre-determined delay ACV to 0, and as a result, the 0 value is added to the adder 531. Note that it is entered.

More specifically, the adder 531 adds the inversion H and the delay ACV (DACV) obtained in advance from the delay unit 532 to the line L.
The sum is supplied to the delay unit 532 and the comparator 550 through 52 as ACV. In addition, the delay unit 532
For example, as a shift register,
V is delayed by 1 DDTI, and the DACV is added to the adder 53.
Feed to 1.

The comparator 550 compares the ACV input within a predetermined first time interval with a predetermined threshold value THV, and generates an SRS on the line L53 when the ACV is larger than THV. The SRS is input to the DRS generator 540, the interpolator 300, the equalizer 400, the data detector 600, the output controller 700, and the timing recovery circuit 800. Note that, according to the preferred embodiment of the present invention, the predetermined second time interval is longer than the predetermined first time interval.

<IFCS> generating section 560 controls line L5
<IFCS> is generated on the line L14 in response to the SRS input through S3. More specifically, the address generator 561 operates according to the SRS in the <IFC in the ROM 562.
And generates and supplies an address signal representing the address used to access S>. The ROM 562 reads <IFCS> using the address signal and generates it on the line L15.

Here, <IFCS> is the weighted control unit 5
00 is generated by the equalizer 4
Note that after being entered at 00, it is used to update the filter coefficients used there.

Under the condition that this SRS is generated and input by the weighted control unit 500, each of the interpolation units 30
0, equalizer 400, data detector 600, output controller 7
00 and the timing recovery circuit 800 are reset in response to the SRS.

For example, the SRS is connected to the DCS generator 731 and the FIF in the output control unit 700 through the line L75.
When each is input to the O data output control unit 740, DC
The S generator 731 and the FIFO data output controller 740 are reset.

Although the preferred embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.

[0077]

Thus, according to the present invention, the accumulation of unnecessary data output at the output terminal can be suppressed, whereby the equalization performance of the device can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional asynchronous data detector used in a magnetic recording / reproducing system.

FIG. 2 is a block diagram of an asynchronous data detector used in a magnetic recording / reproducing system according to a preferred embodiment of the present invention.

FIG. 3 is a detailed block diagram of an output control unit in the data detection device in FIG.

FIGS. 4A to 4K are waveform diagrams showing an output data sequence and a waveform of a clock signal for explaining the operation of the output control unit in FIG. 3;

FIG. 5 is a detailed block diagram of a weighted control unit in the data detection device in FIG. 2;

[Explanation of symbols]

 Reference Signs List 200 Analog / Digital (A / D) converter 300 Interpolator 400 Equalizer 500 Weighted controller 600 Data detector 700 Output controller 800 Timing recovery circuit 900 System clock generator 950 Output clock generator

Claims (13)

[Claims] 1. A magnetic recording / reproducing system comprising a magnetic head having a read element, wherein the magnetic flux transition induced from a magnetic recording medium by the read element of the magnetic head is pre-amplified by a predetermined level. An asynchronous data detection device for detecting a binary data value from an analog reproduction signal, wherein digital data is recorded at a predetermined level on a magnetic recording medium at a predetermined recording frequency, and wherein the predetermined recording is performed. First signal generating means for generating a system clock signal (CLK) having a frequency higher than the frequency (PRF); second signal generating means for generating a data output clock signal (CLK1) having a frequency equal to the PRF; Converts analog reproduction signal to digital reproduction data according to CLK and supplies sample value S And interpolating filtering on the S according to the CLK based on a predetermined phase error signal to supply an interpolated sample value (IS) and satisfy a predetermined holding condition. Interpolating filter means for generating a holding signal (H); and performing equalization on the IS according to the CLK to supply an equalized sample value (ES) and finite response filtering on the IS. And an equalizing means for generating an error signal (E) representing an error between the filtering data obtained by performing the above and a determination value obtained by performing a level determination on the filtering data; Maximum Likelihood Sequence Detection for ES (MaximumLikelihood Sequence)
Nonce Data (MLSD) technique to detect the existence path, thereby obtaining a binary data value (BD) representing the final existence path obtained therefrom.
And a predetermined number of determined values representing the existence path obtained therefrom as a set of determined values (<DV>). A data detecting means, and a phase error based on the <DV> and the E according to the CLK. Timing recovery means for performing timing recovery to obtain a signal (PE) and supplying the PE to the interpolation filtering means; and the BD using the H, the CLK and the CLK1.
And an output control means for supplying final output data by performing output control on the asynchronous data detection device. 2. The output control means delays the BD by one data detection time interval (DDTI), supplies a delay BD, updates the CLK using the H, and updates a frequency of the CLK. The update clock signal (MC
LK), fourth signal generating means for generating an output control signal (OCS) using the CLK1, and the delay BD based on the OCS and the MCLK.
2. The asynchronous data detecting apparatus according to claim 1, further comprising: FIFO data output control means for performing first-in first-out (FIFO) data output control on the first data to generate the FD. 3. The FIFO data output control means according to claim 2, wherein said delay BD is written to said FIFO data output control means by said MCLK, and then read out from said FIFO data output control means as said FD in response to said OCS. 2. The asynchronous data detection device according to 1. 4. The first signal generating means delays the H by the DDTI to generate a first delay H, and the first inverting means inverts the CLK to generate an inverted CLK. Second delay means for delaying the first delay H in accordance with the inverted CLK to generate a second delay H; and a predetermined time shorter than half of one clock time interval of the CLK. Third delay means for delaying by an interval to generate a third delay H, and first AND operation means for performing an AND operation on the first delay H and the third delay H to generate an update H A fourth delay means for delaying the update H by the predetermined time interval to generate a fourth delay H, and performing an AND operation on the fourth delay H and the inverted CLK to generate the MCLK Second AND operation means for generating Asynchronous data detecting apparatus according to claim 3, wherein the door. 5. The fifth signal generating means, wherein the fourth signal generating means generates a delayed clock signal (DCS) for instructing to delay the start time of the CLK1 by the predetermined time interval; 5. The asynchronous data detection device according to claim 4, further comprising: a third AND operation unit that performs an AND operation on the DCS to generate the OCS. 6. 6. When the H is generated by the interpolation filter means, the H is supplied to the equalization means, the data detection means, the timing reproduction means, and the output control means, and then the equalization is performed. 6. The asynchronous data detecting apparatus according to claim 5, wherein the operation of the means, the data detecting means, the timing reproducing means, and the output control means is maintained only by DDTI. 7. Under the assumption that the H generated by the interpolation filter means is input, weighted control is performed using the H, and a predetermined control is performed for a predetermined first time interval. If more than the number of Hs are input, the set of the system reset signal (SRS) and the initial filter coefficient <I
7. The asynchronous data detecting device according to claim 6, further comprising a weighted control unit for generating FCS>. 8. The weighted control means: a second inverting means for inverting the H and supplying the inverted H; and a periodic delay for a predetermined second time interval longer than the predetermined first time interval. 6th generation of reset signal (DRS)
A signal generating / generating means; an accumulating means for performing accumulation using the inversion H to supply an accumulated value (ACV); and setting the ACV to a predetermined threshold value within the predetermined first time interval ( THV) as compared to the ACV
If greater than, the comparing means for generating the SRS; and generating the <IFCS> according to the SRS.
8. An apparatus according to claim 7, further comprising: FCS> generating means.
2. The asynchronous data detection device according to 1. 9. When the SRS is generated by the weighted control unit, the SRS is supplied to the equalization unit, the interpolation filter unit, the data detection unit, the timing recovery unit, and the output control unit, respectively. 9. The method according to claim 8, wherein the operations of the equalization unit, the interpolation filtering unit, the data detection unit, the timing reproduction unit, and the output control unit are reset in response to the SRS. Asynchronous data detection device. 10. An accumulator for adding the H and a delay accumulated value (DACV) obtained in advance to supply the ACV, an adder for delaying the ACV by the 1DDTI, and The asynchronous data detection device according to claim 9, further comprising: a delay unit that supplies the DRS to the adder and, when the DRS is input from the DRS generator, initializes the DRS according to the DRS. 11. The address generator according to claim 11, wherein the <IFCS> generator generates an address signal representing an address used to access the <IFCS> in response to the SRS. 11. The asynchronous data detecting apparatus according to claim 10, further comprising: reading means for reading <IFCS> to generate the <IFCS>. 12. When the <IFCS> is generated by the weighted control unit, the filter coefficient used in the equalization unit is updated after the <IFCS> is input to the equalization unit. The asynchronous data detection device according to claim 11, wherein the device is used for: 13. The method of claim 1, wherein when the SRS is input to a DRS generator, the sixth signal generator generates the DRS and supplies the generated DRS to the delay unit.
3. The asynchronous data detection device according to 2.