JP2833587B2 - Demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD The present invention relates to a demodulation device,
In particular, the present invention relates to a demodulator having a waveform equalizer used for digital microwave communication using a multilevel quadrature amplitude modulation method and for equalizing waveform distortion of a specific frequency component due to superposition of a direct wave and an interference wave on a propagation path.

[0001]

2. Description of the Related Art As a first known example of a conventional demodulator,
FIG. 12 shows a principle configuration diagram of a waveform equalizer of a data communication apparatus according to Japanese Patent Laid-Open No. 6-120774. The waveform equalizer in FIG. 12 inserts a training sequence, which is known data, into transmission data as a control method for equalizing waveform distortion included in a burst-type reception signal of time-division multiple access communication (TDMA communication). Then, among the correlation values obtained by correlating the received data with the known data by the correlation calculator 112, the component having the largest absolute value is detected by the maximum value detector 113, and the main tap setting device 114 detects the waveform and the like. The reciprocal of the correlation value is set only for the tap having the largest absolute value of the correlation value among the tap coefficients of the linear part of the transformer, and waveform equalization is performed after training in a short training sequence. The main tap setting unit 114 sets only the tap coefficient for the component having the largest absolute value of the correlation value, and the other linear part tap coefficients and the decision feedback part tap coefficients are 0.
Is set to

A second known example of a demodulator is disclosed in
FIG. 13 shows a principle configuration diagram of a demodulation system according to JP-A-232774. The demodulation system of FIG. 13 includes an adaptive matched filter (AMF) 1 in a decision feedback equalizer (DFE) 140.
Since the equalization characteristic is inferior to that of the DFE 140 alone for the minimum phase transition type fading, the operation of the AMF 130 is performed when the minimum phase transition type fading is detected from the tap coefficient of the DFE 140. Is stopped so that the equalization effect of the decision feedback equalizer 140 can be sufficiently exhibited.

As an arrangement, an AMF reset circuit 150
, The type of fading is determined from the tap coefficients in the DFE 140, and the minimum phase transition type fading (0 <ρ
When <1, ρ is the fading delay wave amplitude / main wave amplitude ratio), the operation of the AMF 130 is stopped.

[0004] As a third known example of a demodulator, Japanese Patent Laid-Open Publication No.
FIG.
It is shown in FIG. The demodulator of FIG. 14 has a function of detecting a signal disconnection of an input signal at the output of the demodulator 30 by the disconnection detection circuit 50. When the signal disconnection is detected, the adaptive amplitude equalizer 90
Then, the equalizing operation of the transversal equalizer 40 is reset to the initial value. When deep fading occurs in the propagation path and the demodulated signal output from the demodulator 30 is interrupted due to loss of synchronization or the like, the above-described reset operation is performed to facilitate synchronization at the time of re-locking.

[0005]

The conventional demodulator described above has the following problems.

The first problem is that, in digital microwave communication, known data for setting an initial value of a tap coefficient of a waveform equalizer as shown in the above-mentioned first known example of the prior art. That is, it is impossible to insert a training sequence into transmission data and to correlate with a received signal. In addition, when a training sequence is inserted into transmission data, transmission efficiency decreases due to a reduction in data capacity for the training sequence.

The reason is that, in digital microwave communication, a continuous data signal is transmitted instead of transmitting a burst-type signal as shown in the first known example of the prior art. Not inserted. Also, when the training sequence is inserted into the overhead bit of the frame format of the transmission data, a training sequence that is used only at the initial pull-in and is not used in the normal state is inserted for each frame of the continuous data signal. This is because the transmission efficiency is reduced.

The second problem is that after fading that exceeds the equalizing capability of the waveform equalizer occurs on the propagation path and the waveform equalizer enters a diverging state, the fading amount decreases and the signal is synchronized again to make the waveform equalize. There is a large difference between the pull-in characteristic in which the equalizer converges and the equalization characteristic when the fading amount increases, and it takes time to converge.

The reason is that the fading amount is reduced, and the tap coefficient of the waveform equalizer is used as a means for converging the waveform equalizer to bring the signal back into a synchronized state. Since the initial value is reset to the initial value, the equalizer can quickly converge in the re-pulling operation from the distortion-free state, but the fading amount decreases and the equalizer is within the sufficient range of the equalizing capability. However, since the tap coefficients are reset to the initial values in the no-distortion state, the amount of operation for converging the tap coefficients must be increased, and the convergence becomes slower, and the equalization characteristics and the pull-in characteristics of the equalizer become large. There is a difference. Also, it takes time to converge.

As described above, according to the present invention, after fading that exceeds the equalizing capability of the waveform equalizer occurs in the propagation path and the waveform equalizer enters a diverging state, the fading amount decreases and the signal is synchronized again. The purpose of this method is to quickly return the signal transmission state to a normal state by improving the convergence when the waveform equalizer performs re-pulling and obtain high pull-in characteristics, thereby improving the reliability of the transmitted signal. And

[0011]

SUMMARY OF THE INVENTION The present invention provides an amplitude distortion equalizing circuit for equalizing primary amplitude distortion and secondary amplitude distortion on a reception frequency axis, and detecting residual amplitude distortion of the amplitude distortion equalizing circuit. An amplitude distortion detector, a control signal generation circuit that calculates an output result of the amplitude distortion detector and generates a control signal of the amplitude distortion equalization circuit, and a reception in which the amplitude distortion is equalized by the amplitude distortion equalization circuit. A demodulator that inputs a signal and outputs a demodulated signal, a waveform equalizer configured by a decision feedback equalizer that performs waveform equalization on the time axis, and a control signal of the control signal generator is used. A tap coefficient preset circuit for setting a tap coefficient at the time of pull-in of the waveform equalizer, and switching between a preset signal or a reset signal, which is a tap coefficient setting signal output from the tap coefficient preset circuit using an asynchronous signal as a control signal, Tap on waveform equalizer A switching unit for outputting the number setting signal.

The weighting coefficient of the tap generated by the waveform equalizer is used as the tap coefficient of the waveform equalizer when the equalization capability is within the range of the equalization capability of the equalizer. Based on the fading frequency information detected from the control signal, the tap coefficient is set effectively for the pull-in corresponding to the frequency where the fading is occurring, so that the amount of operation up to the tap weighting coefficient convergence at the time of pull-in of the waveform equalizer can be reduced. By reducing the number and speeding up the convergence, a higher pull-in characteristic can be obtained as compared with the conventional waveform equalizer.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a demodulation device according to the present invention.

The amplitude equalizer 9 of the demodulator according to the present invention comprises the above-mentioned adaptive amplitude equalizer 90 of FIG. 14 composed of a secondary amplitude distortion equalizer 1 and a primary amplitude distortion equalizer 2. is there.

In the waveform equalizer 4, the transversal equalizer 40 shown in FIG. 14 is constituted by a decision feedback type waveform equalizer. The received signal 101 is input to the demodulator 3 after being subjected to the equalizing operation of the amplitude characteristics by the respective amplitude distortion equalizing circuits 1 and 2.

The demodulator 3 performs carrier wave synchronization, demodulation, and identification on the received signal subjected to amplitude equalization. The demodulated and identified received signal is input to the waveform equalizer 4, where the waveform is shaped and the intersymbol interference is removed. The signal of the demodulation device from which the waveform shaping and the inter-symbol interference have been removed is output as a signal output 103 to the subsequent signal processing device.

The disconnection detection circuit 10 outputs a disconnection detection signal when the input signal of the demodulator becomes a certain level or less (including the case where the input signal disappears) and the output signal of the demodulator is disconnected.
The signal is output as a signal for reset control of the control signal generation circuit of the amplitude equalizer and the waveform equalizer.

The equalizing operation of the second-order amplitude distortion equalizing circuit 1 and the first-order amplitude distortion equalizing circuit 2 is controlled by an amplitude distortion detector 5 and a control signal generating circuit 6, and the secondary amplitude distortion added to the received signal is controlled. , Operates to minimize the first-order amplitude distortion. The tap coefficient preset circuit 7 receives the fading position information signal G detected by the control signal generating circuit 6 and outputs a tap coefficient control signal for setting the tap coefficient to a constant offset adapted to the signal G to the switch 8. I do.

When the control of the waveform equalizer is in a divergent state, the switch 8 outputs an asynchronous signal k input from the signal processing device.
Thus, the preset signal h and the reset signal j output from the tap coefficient preset circuit 7 are selectively switched to control the setting of the tap coefficient of the waveform equalizer 4.

FIG. 2 is a block diagram showing a detailed configuration of the amplitude equalizer 9.

As shown in FIG. 2, the amplitude equalizer 9 has the amplitude distortion detector 5 and the fc-, fc +, and f0 detectors 51, 52, and 53 whose selection frequencies are set to fc-, fc +, and f0.
The received signal is demultiplexed for each frequency, and the respective levels are detected. Further, the control signal generation circuit 6 outputs the output S (fc) of the fc− detector 51 and the fc + detector 52 of the amplitude distortion detector 5.
−) And S (fc +) are sent to the primary amplitude distortion equalization circuit 2 via the subtraction circuit 61 by the control signal C1 = | S (fc −) − S
(Fc +) |... (1), and controls the first-order amplitude distortion equalization circuit 2 so that this C1 is minimized.

Further, the output S (f0) of the f0 detector 53
And the outputs S (fc−) of the fc−, fc + detectors 51, 52
−) And S (fc +) to the secondary amplitude distortion equalization circuit 1 via the subtraction circuit 1 via the resistors R1 and R2 and the control signal C2 = | (S (fc −) + S (fc +)) / 2− S (f
0) | ... (2)

Then, the secondary amplitude distortion circuit 1 is controlled so that C2 is minimized. The control signal output from the subtraction circuits 61 and 62 is α of the amplitude distortion equalization characteristic S1 (ω) = 1 + 2αcosωγ (3), where α is the above-described C1 for the primary amplitude distortion equalization control signal, It is C2 for the secondary amplitude distortion equalization control signal.

The value of γ determines the secondary amplitude distortion characteristic or the primary amplitude distortion characteristic.

As shown in FIG. 3, the fading position detecting circuit 63 in the control signal generating circuit 6 which is a component of the present invention includes control signals p and q output from the subtracting circuit and a reference value generating circuit which can be set to an arbitrary value. The value of the output of 64 is compared with comparators 65, 66, 6
By comparing in step 7 and outputting a binary value, the frequency position where fading occurs is detected from the control signal of the amplitude distortion equalization circuit.

In this embodiment, the comparators 65, 66 and 6
7 and 3 circuits are provided so as to correspond to the frequencies f0, fc- and fc +, thereby detecting where the fading is located at fc-, f0 and fc +.

FIG. 4 is a block diagram showing a specific embodiment of the tap coefficient preset circuit 7. In the figure, tap coefficient preset circuit 7 includes fc−, f0, f
Storage units 72 and 7 storing in advance setting values to be controlled as tap coefficients when fading is added to the frequency of c +.
3, 74 and the tap coefficient in the undistorted state when the disconnection detection signal of the disconnection detection circuit 10 is input, for example, the center tap is set to “1”.
A memory 75 for initially setting tap coefficients of the waveform equalizing circuit 4 to other taps to '0', an output signal of the fading position detecting circuit 63 of the control signal generating circuit 6, and a disconnection detecting circuit 1
The disconnection detection signal of 0 is used as a switching control signal in the storage units 72 and 7.
3, 74 and a switch 71 for selecting the output of the storage device 75.

FIG. 5 shows the operation of the switch 71 of this embodiment. The output of the storage device 75 is also output to the switch 8 without passing through the switch 71.

The decision feedback equalizer (D) of the waveform equalizer 4
FIG. 6 shows a block diagram of FE). In the decision feedback equalizer of FIG. 6, 441a is a forward equalizer composed of N forward taps, 442a is N-1 delay circuits having a delay time of a transmission symbol length T, and 443a is N multipliers. circuit,
441b is a rear equalizer composed of M rear taps,
2b is M delay circuits having a delay time of the transmission symbol length T, 443b is M multiplier circuits, 444 is a combining circuit,
445 is a main signal determination circuit, 446 is a difference circuit, and 447 is a tap coefficient generation circuit, and the center tap is set to the last tap of the front tap.

The tap coefficient generation circuit 447 includes N + M multiplication circuits 4471 and an integration circuit 4472 which is N + M up-down counters. The output signal of the above-described switch 8 is a control signal for setting an initial value to the up / down counter of the integration circuit 4472.

The tap coefficient generation circuit 447 includes tap inputs XN-1, XN-2,..., X0 and an, of N front taps of the front equalizer and M rear taps of the rear equalizer.
An-1,... an-M and the error signal E are correlated by a multiplication circuit 4471, an up / down counter is operated in accordance with the correlation, and an integration circuit 4472 for outputting a correlation value detects the correlation value. At 443, the tap input is weighted according to the correlation value. This correlation value is called a tap coefficient. The tap coefficient generation circuit 447 calculates tap coefficients cN-1, cN-2,.
A tap coefficient c0 is calculated for the center tap, and tap coefficients d1, d2,... DM are calculated and provided for the rear tap.

At the N forward taps of the forward equalizer, XN-1, XN-2,.
······················································································································. By the same operation, a tap coefficient signal corresponding to the correlation value with the error signal E is output to the synthesis circuit 444.

In the rear tap, the inter-symbol interference is removed and the judgment signal an which has been further judged is input to the delay circuit 44.
2b, the determination signals an and an−
1,... An-M are output to the synthesizing circuit in accordance with the correlation value with the error signal E by the same operation as the forward tap.

The combining circuit 444 outputs an equalized signal from which the intersymbol interference component contained in the input of the decision feedback equalizer has been removed by adding the outputs of the front, center and rear taps. The main signal determination circuit 445 estimates the most probable value by comparing the signal points of the equalized signal and the transmission signal, and outputs the estimated value as a determination signal. The difference circuit 446 takes the difference between the post-equalization signal and the determination signal, and outputs an error signal E that is an equalization residual.

Next, the operation of the embodiment of the present invention will be described.

A case where deep fading exceeding the equalizing capability of the waveform equalizer occurs in the propagation path and the spectrum of the transmission signal shown in FIG. 8A is received by the spectrum shown in FIG. 8B is shown.

At this time, the equalization capability of the amplitude equalizer is also higher, but as described above, since the control signal C1 is controlled to be minimized, as shown in FIG. Performs an operation of giving amplitude characteristics to a received signal and equalizing amplitude distortion. At this time, assuming that a value of + α is given to the primary amplitude distortion equalizing circuit 2 as a control signal, the comparator 67 for detecting the fc + fading of the fading position detecting circuit 63 shown in FIGS. 64 is set to 0, the output signal g3 of the comparator 67
Becomes "1" and the outputs of the other comparators 65 and 66 become "0".
Becomes

The tap coefficient control signal set in the storage units 72, 73 and 74 of the tap coefficient preset circuit 7 stores a value to be controlled and set to a coefficient as shown in FIG. 9, for example.

FIG. 9 shows experimental data obtained by measuring the state of the tap coefficient of the waveform equalizer when a fading notch is added to the received signal. At times t1, t2 and t3 in FIG. 9, the fading notches are fc−, f0,
The state of the tap coefficient of each tap when added to fc + is shown. The control signals for setting the tap coefficient states t1, t2 and t3 are stored in the respective memories 72, 73 and 7 respectively.
4, g1, g2, and g, which are the output signals G of the fading position detection circuit 64 described above.
As shown in FIG. 5, the switch 71 using 3 as the switch control signal transmits the tap coefficient control signal h at the time of fc + from the storage 74 to the waveform equalizer 4 via the switch 8 as the tap coefficient generation circuit 44. Is output.

At this time, the switch 8 operates according to the flow shown in FIG.

Next, the operation of the switch 8 will be described. First, when the waveform equalizer enters a diverging state from the signal processing device located at the subsequent stage of the demodulation device, the asynchronous signal k is input to the switch 8, whereby the signal h whose tap coefficient is selected by the preset circuit 7 is It is output to the tap coefficient generation circuit 447 (FIG. 6) as an initial setting value of the integrator 4472 (FIG. 6).

The tap coefficient generation circuit 447 (FIG. 6) starts an operation to converge from the set initial value. At this time, the fading added to the received signal cannot be detected by the control signal of the amplitude equalizer as being in the minimum area where the interference wave is delayed from the main signal on the time axis or in the non-minimum area where the interference wave is advanced from the main signal. Therefore, if it is in the minimum area, the pull-in operation is established and the tap coefficient converges, but if it is in the non-minimum area, the tap coefficient converges because it exceeds the equalization capability of the waveform equalizer as described later. After a certain period of time, the switch 8 confirms the asynchronous signal k, and the output signal j of the storage unit 75 of the tap coefficient preset circuit 7 which is relatively easy to be pulled in the non-minimum area because there is a high possibility that the state will be a divergent state.
To the integrator 447 of the tap coefficient generation circuit 447 (FIG. 6).
2 (FIG. 6) is output as an initial setting value.

The tap coefficient generation circuit 447 (FIG. 6) starts an operation to converge from the set initial value.

The above operation is repeated until the waveform equalizer periodically converges by having an oscillator or the like as a component inside the switch 8 and no asynchronous signal is input.

Transmission signal A similar operation is performed when the spectrum of FIG. 8A is received with the spectrum of FIG. 8B. In this case, the output signal g1 of the comparator 65 becomes "1", and as shown in FIG. 5, a signal for controlling and setting the tap coefficient when fading is applied to f0 set in the storage 73 of the tap coefficient preset circuit 7. Is selected, and the tap coefficient of the waveform equalizer 4 is set and controlled to the state t2.

Further, when the input of the demodulator is in a no-signal state or a large level drop due to an abnormality on the transmission side or an abnormality on the propagation path, and the waveform equalizer is in a divergent state, the disconnection detection circuit 10 detects disconnection. The signal is output to the switch 71 of the tap coefficient preset circuit 7, and the switch 71 selects and outputs the output of the storage unit 75.

Next, the pull-in characteristic of the waveform equalizer will be described. As shown in FIG. 9, when a notch due to fading is added to the reception spectrum of the demodulation device, the states of the tap coefficients are as shown at t1, t2, and t3. Although the state of FIG. 9 is within the range of the equalization capability, at the time of pull-in, in the conventional waveform equalizer, the initial value of the tap coefficient is set to, for example, the coefficient 0 in a non-distorted state. However, if the initial setting of the coefficients is set to t1, t2, and t3, the equalization can be performed even if a deeper fading notch is added than in FIG. Within the capability range, the amount of operation up to the convergence of the tap coefficient can be reduced and the convergence can be accelerated.

The improvement of the pull-in characteristic of the waveform equalizer by the operation described above will be described with reference to FIGS.

That is, FIGS. 10 and 11 are diagrams showing the pull-in characteristics of the waveform equalizers of the present invention and the prior art, respectively. In both drawings, a hatched portion is called a signature equalization characteristic, and a pull-in characteristic is indicated by a dashed line. The horizontal axis indicates the notch position Δfd obtained by normalizing the shift of the fading notch (drop) frequency from the center of the modulation spectrum by the clock frequency, and the vertical axis indicates the amplitude of the reflected wave (delayed wave) by the amplitude of the main wave. The converted amplitude ratio ρ is taken. Notch depth Dn is Dn = −20 log
(1−ρ) (dB) (4)

Therefore, when ρ = 1, the notch depth Dn becomes maximum (∞). The solid line in FIGS. 10 and 11 indicates the notch position Δ
Error rate P = 1 × 1 using fd and amplitude ratio ρ as parameters
It connects the notch position Δfd of 0-4 and the point (coordinate) of the amplitude ratio ρ.

In the hatched area, P> 1 × 10 −4. Therefore, the smaller the hatched area, the better the equalization ability. Further, the broken line in the figure connects the notch position Δfd at which the equalizer is pulled in and the tap coefficient converges and the amplitude ratio ρ as a parameter to connect the point (coordinate) of the notch position Δfd amplitude ratio ρ at which the equalizer is pulled in. It is. The hatching in FIGS. 10 and 11 indicates the signature characteristic of the demodulation device provided with the decision feedback equalizer in the waveform equalizer.

In the case of 0 <ρ <1, the interference wave exists only at a position delayed in time from the main signal, so that the backward equalizer of the decision feedback equalizer exerts a sufficient effect and is completely equalized. You are.

On the other hand, when ρ <1, since the interference wave exists only at a position temporally ahead of the main signal, the forward equalizer of the decision feedback equalizer operates.

However, since the forward equalizer receives a signal distorted by fading as an input, it does not have a sufficient equalizing ability and has poor signature characteristics when ρ> 1.

The state of ρ> 1 is a state in which the level of the interference wave becomes larger than that of the main signal due to the progress of the fading notch depth, and the main signal and the interference wave are reversed. The dashed line in the figure indicates a state in which the fading notch becomes ρ> 1 and the tap coefficient control of the decision feedback equalizer diverges, and the fading decreases and the control of the tap coefficient control of the equalizer converges. In an area surrounded by a broken line, the equalizer is retracted.

Therefore, the smaller the area surrounded by the broken line, the better the equalizing ability. According to the demodulator of the present invention, if the tap coefficient state of the equalizer that can equalize the notch depth of the broken line is set in advance, the amount of control operation until the tap coefficient of the equalizer converges is reduced and the convergence is reduced. And a good pull-in characteristic as shown in FIG. 10 can be realized as compared with FIG.

In this embodiment, for simplicity, only three types of tap coefficient frequencies are set in the storage unit. However, when the number of storage units is increased and the tap coefficient setting is more finely controlled. As shown in FIG. 9, the state of the tap coefficient when a fading notch is added to each frequency is measured in advance, a signal for setting the tap coefficient in the state is set in the storage, and the control of the tap coefficient preset circuit is performed. Depending on the state of the combination of the output signal of the fading position detection circuit, which is a signal, a tap coefficient corresponding to a more accurate number of main waves can be added to the waveform equalizer.

Further, if the configuration of the tap coefficient preset circuit is constituted by a storage element such as a ROM which can be addressed by a control signal, the circuit scale can be reduced.

Although the amplitude equalizer has been described with reference to the primary and secondary amplitude distortion equalizers, a higher-order amplitude distortion equalizer can be configured.

[0061]

As described above, the effect of the present invention is that the fading amount is reduced after the fading exceeds the equalizing capability of the waveform equalizer in the propagation path and the waveform equalizer enters a divergent state. Synchronize the signal, speed up the convergence when the waveform equalizer re-locks, obtain a higher pull-in characteristic than the conventional waveform equalizer, and also improve the reliability of the transmitted signal. Can be.

The reason is that the frequency at which fading occurs is detected based on a control signal for controlling the Nth-order amplitude distortion equalizing circuit of the amplitude equalizer, and it is effective in advance to pull in the waveform equalizer. By setting appropriate tap coefficients, it is possible to quickly return the signal transmission state to a normal state by reducing the amount of operation until the convergence of the tap weighting coefficients when pulling in the waveform equalizer and speeding up the convergence. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a demodulation device of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of an amplitude equalizer 9 in FIG.

FIG. 3 is a block diagram illustrating an embodiment of a fading position detection circuit 62 in FIG.

FIG. 4 is a block diagram illustrating an embodiment of a tap coefficient preset circuit 7 of FIG.

FIG. 5 is a diagram illustrating an operation of a switch of the tap coefficient preset circuit 7 of FIG. 1;

FIG. 6 is a block diagram of the decision feedback equalizer 4 of FIG.

FIG. 7 is a flowchart showing the operation of the switch of the present invention.

FIG. 8 is a diagram illustrating a reception spectrum when fading occurs.

FIG. 9 shows experimental data obtained by measuring tap coefficients of a waveform equalizer.

FIG. 10 is a diagram illustrating a pull-in characteristic of the waveform equalizer of the present invention.

FIG. 11 is a diagram illustrating a pull-in characteristic of a conventional waveform equalizer.

FIG. 12 is a block diagram of a waveform equalizer according to a first conventional technique.

FIG. 13 is a block diagram of a demodulation system according to a second conventional technique.

FIG. 14 is a block diagram of a demodulator according to a third conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Secondary amplitude distortion equalization circuit 2 Primary amplitude distortion equalization circuit 3 Demodulator 4 Waveform equalizer 41 Equalizer 42 Filter part 43 Judgment part 44, 447 Tap coefficient generation circuit 441a, 441b Front and back equalizer 442a , 442b Delay circuit 443a, 443b, 4471 Multiplication circuit 444 Synthesis circuit 445 Main signal judgment circuit 446 Difference circuit 4472 Integration circuit 5 Amplitude distortion detector 51, 52, 53 Selection filter 6 Control signal generation circuit 7 Tap coefficient preset circuit 72, 73 , 74, 75 storage unit 8, 71 switch 9 amplitude equalizer 10 disconnection detection circuit 61, 62 subtraction circuit 63 fading position detection circuit 64 reference value generation circuit 65, 66, 67 comparator 101 reception signal 102 amplitude equalizer Output signal 103 Demodulator output signal G, g1, g2, g3 Switching control signal h, , J tap coefficient control signal k asynchronous signal q, l amplitude distortion equalization circuit control signal s disconnection detection signal t1, t2, t3 tap coefficient positions

Claims (6)

(57) [Claims] An amplitude distortion equalizing circuit for equalizing amplitude distortion, an amplitude distortion detector for detecting residual amplitude distortion of the amplitude distortion equalizing circuit, and an amplitude distortion detector, A control signal generation circuit that calculates an output result of the distortion detector and generates a control signal of the amplitude distortion equalization circuit, and a reception signal whose amplitude distortion is equalized by the amplitude distortion equalization circuit is input and a demodulation signal is output. A demodulator, a waveform equalizer configured by a decision feedback type equalizer that receives the demodulated signal and performs waveform equalization, and when the waveform equalizer is pulled in based on a control signal of the control signal generator. A tap coefficient preset circuit for setting the tap coefficient of the tap coefficient, and a switch for selecting and switching between a preset signal and a reset signal output from the tap coefficient preset circuit using an asynchronous signal as a control signal, and outputting a tap coefficient setting signal to the waveform equalizer. Have a container A demodulation device. 2. The control signal generating circuit according to claim 1, further comprising means for comparing the control signal of said amplitude distortion equalizing circuit with a preset reference value to control said tap coefficient preset circuit. A demodulator characterized by the above-mentioned. 3. The tap coefficient preset circuit according to claim 1, wherein the tap coefficient preset circuit is a circuit for setting tap coefficients at the time of pull-in of the waveform equalizer, wherein the waveform is adjusted according to a fading frequency added to a received signal of the demodulator. A memory in which a tap coefficient setting signal effective for the pull-in operation of the equalizer is preset and stored, and an output of the memory is selected by a control signal of an output of the control signal generation circuit, and a tap of the waveform equalizer is selected. A demodulation device comprising: means for outputting a coefficient setting signal to the switch. 4. The switch according to claim 1, wherein the tap coefficient setting signal, which is an output signal of the tap coefficient preset circuit, includes a preset signal of an initial setting value having an offset in accordance with a fading frequency, and an offset. A demodulation device having means for switching and selecting a reset signal of an initial setting value which has not been output, and periodically outputting a tap coefficient setting signal to a waveform equalizer in a time division manner by an asynchronous signal of a signal processing device located downstream of the demodulation device. . 5. The demodulation device according to claim 1, wherein the amplitude distortion is a higher-order amplitude distortion equal to or higher than a first-order amplitude distortion on a reception frequency axis. 6. The amplitude distortion detector according to claim 1, wherein the amplitude distortion equalizer output is demultiplexed into a center frequency and two frequencies higher and lower than the center frequency to detect each level. A demodulator characterized by the above-mentioned.