JPH08274818A - Automatic equalizing circuit - Google Patents

Abstract

PURPOSE: To provide an automatic equalizing circuit of partial response (PR) 4-detection system with simple configuration. CONSTITUTION: Comparators C1 and C2 respectively compare an equalizer output yn with reference values v1 and v2 so as to discriminate whether or not the signal yn is '1', '0' or '-1' and comparators C3 -C5 respectively discriminate whether the equalizer output yn is larger than reference values v3 , v4 and v5 . Based on respective outputs a<+> , a<-> , e+1 , e0 , e-1 , a data extraction/equalization error detection block 7 detects deviation from an ideal equalized waveform and outputs tap coefficient correct signals CT+1 , CT0 , CT-1 , CN0 and CN-1 . The respective analog added values of signals (CT+1 , CN+1 ), (CT0 , CN0 ) and (CT-1 , CN-1 ) are respectively calculated by adder circuits 8+1 , 80 and 8-1 and averaged, and based on these respective average values, tap coefficients C+1 , C0 and C-1 are respectively adapted through buffers 9+1 , 90 and 9-1 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to three values (0, +1,-).
The present invention relates to an automatic equalization circuit of PR (Partial Response) 4 detection method for detecting 1), and for example, relates to an automatic equalization circuit suitable for adaptively equalizing a reproduced waveform of a digital VTR.

[0002]

2. Description of the Related Art FIG. 9 shows an eye pattern after equalization by a PR4 detection method, in which a signal at a data discrimination point is +1 and
It converges to either 0 or -1. However, because the waveforms deviate from the levels of +1, 0, and -1 due to noise and deviation of the frequency characteristics, the equalizer is optimized by adaptively calculating the correction amount of the tap coefficient of the equalizer. Maintenance is done.

FIG. 10 shows the principle of a conventional adaptive equalizer for equalizing a binary signal by an analog method.
W. Lucky, The Bell System Technical Journal, Vol. 4
5,) Feb., 1966, pp255-268. The input signal (INPUT) has delay units (T) 21-1, 21-2 and coefficient units 22 _-1 , 22 ₀ , 2 with tap coefficients C _-1 , C ₀ , C _+1.
Waveform interference is reduced by 2 ₊₁ and then output as equalized data a _n via the sampling circuit 23 and the slice circuit 24.

Also, the tap coefficient C_-1, C₀ , C₊₁Adapt
Equalization data a_n Is a D / A converter 25,
Delay device 21-4 and multiplier 26_-1Feedback to
It Then, the equalization error e_n Output of A / D converter 25
Force a_n And the output y of the sampling circuit 23_n Difference (e_n =
y_n -A_n ) Is calculated by the subtractor 30 and the delay unit 21
Through the multiplier 26_-1, 26₀ , 26₊₁Applied to
It Also, equalized data a n is a delay device 21-4, 21-4
Via the multiplier 26₀ , 26₊₁Applied to.
In such a configuration, the multiplier 26_-1, 26₀ , 26₊₁By
And the restored data string {a_n } And the equalization error {e_n }of
By multiplication

[0005]

[Equation 1]

Is calculated. However, k is the number of sampling clocks of 1 or more, and j = -1, 0, +1. Then, the filters 27 _-1 , 27 ₀ , 27 ₊₁ and the slice circuits 28 _-1 , 2
8 ₀ , 28 ₊₁ and sampling circuits 29 _-1 , 29 ₀ , 2
Via 9 _{+1 the} coefficient C _i is decreased by Δ if the sign of the multiplication result of the multipliers 26 _-1 , 26 ₀ , 26 ₊₁ is positive, and if it is negative the tap coefficient C _i is increased by Δ. This process is repeated many times to obtain the desired tap coefficient C _j . In recent years, such calculation is generally performed by digital calculation.

[0007]

However, in the case of processing by digital operation in the above-mentioned conventional equalizer,
When the bit rate becomes high, there is a problem that high-speed digital calculation must be performed and the cost becomes high. Also,
3 value is PR4 detection method (0, + 1, -1) and detects the multiplier 26 _-1, 26 _0, 26 using an analog multiplier as a ₊₁ if the adjustment is disadvantageously complicated.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide a PR4 detection type automatic equalization circuit having a simple structure.

[0009]

In order to achieve the above object, the present invention detects an equivalent error amount by an analog comparison circuit and extracts it as a binary discrimination signal, and a restored data string of 0, +1 and -1. And the binary discrimination signal of the equivalent error amount are calculated by a simple logic circuit and output as two logic outputs, and the tap coefficient of the equalizer is controlled based on the analog average value of the two logic outputs. I am trying to do it.

That is, according to the present invention, three values (0, +
In an automatic equalization circuit of partial response 4 detection method for detecting (1, -1), an equalizer that equalizes a ternary (0, +1, -1) analog signal with a variable tap coefficient; A first discriminating circuit for discriminating between 0, +1 and -1 of the signal equalized by the equalizer, and the signal equalized by the equalizer and 0, +1, -1, respectively, and comparing Three second discriminating circuits for outputting a discriminating signal, and the three second discriminating circuits
One of the binary discrimination signals discriminated by the discrimination circuit is selected, the signal is multiplied by the time-series signal discriminated by the first discrimination circuit, and the multiplication result is output as two logic outputs. An automatic equalization circuit having a multiplication circuit and tap coefficient control means for controlling a tap coefficient of the equalizer based on an average value of two logic outputs outputted by the multiplication means is provided. It

According to the present invention, three values (0, +1,-)
In the partial response 4 detection type automatic equalization circuit for detecting 1), an equalizer for equalizing a ternary (0, + 1, -1) analog signal with a variable tap coefficient, and an equalizer A first discriminating circuit for discriminating 0, +1, -1 of the equalized signal; and a signal equalized by the equalizer and 0
And a detection circuit for extracting the larger of the signal equalized by the equalizer and its inverted signal, and the signal extracted by the detection circuit. And +1 are compared, and a third discrimination circuit that outputs a binary discrimination signal and one of the binary discrimination signals discriminated by the second and third discrimination circuits are selected, and that signal and the A multiplication circuit that multiplies the time-series signals determined by the first determination circuit and outputs the multiplication result as two logic outputs, and the above based on the average value of the two logic outputs output by the multiplication means. An automatic equalization circuit is provided, which comprises: a tap coefficient control means for controlling a tap coefficient of the rectifier.

[0012]

In the present invention, the equivalent error amount is detected by the analog comparison circuit and is taken out as a binary discrimination signal, and 0, +1,
-1 The restored data string and the binary discrimination signal of the equivalent error are multiplied by a simple logic circuit to output as two logic outputs, and the equalizer is based on the analog average value of the two logic outputs. Since the tap coefficient of is controlled, the cost can be reduced even when the bit rate is high. Further, since the multiplication logic of the restored data string and the detection result of the equivalent error amount is multiplication of 0, +1 and -1, it can be realized with a small number of gates, and complicated adjustment is unnecessary.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of an automatic equalization circuit according to the present invention, FIG. 2 is a block diagram showing in detail the data extraction / equalization error detection block of FIG. 1, and FIG. 3 is an equalization error e _k and FIG. 4 is an explanatory diagram showing the relationship between the equalized data a _kj and e _k · a _kj , and FIG. 4 is an explanatory diagram showing the operation of the selector of FIG.

In FIG. 1, the magnetic information recorded on the magnetic tape T is reproduced into an analog electric signal by the reproducing head 1. The analog electric signal is amplified by the head amplifier 2 and then transferred to the 3-tap transversal filter 3. Is applied. This filter 3 includes delay devices DL ₁ and DL ₂
And coefficient units 3 ₋₁ , 3 _{0 of} tap coefficients C ₋₁ , C ₀ , C ₊₁ ,
3 ₊₁ and an adder 4 are provided, and tap coefficients C are applied to the input signals at the current sampling point and the sampling points before and after the current sampling point.
Waveform interference is reduced by weighting by _-1 , C ₀ , and C ₊₁ . The output signal of the filter 3 is so-called “1 + D” processed by the delay device DL ₃ and the adder 5, and the equalized signal y is obtained.
It is applied to the comparators C1 to C5 as _n .

[0015] The comparator C1 to C5, as an example, respectively as a reference value v ₁ to v ₅

[0016]

## EQU2 ## v ₁ = + 0.5 v ₂ = -0.5 v ₃ = + 1 v ₄ = 0 v ₅ = -1

Is being applied. Comparators C1 and C
2 are equalizer output y _n and reference value v ₁ (= + 0.
5) and v ₂ (= −0.5) are compared to obtain the signal y
It is determined whether _n is 1, 0, or -1, and the determination signal a
^+, A ^- to output. in this case,

[0018]

## EQU3 ## For ^{_{y n = 1, a + =}} 1, a - = 0 For ^{_{y n = 0, a + =}} 0, a - = For ^{_{0 y n = -1, a +}} = 0, a ^- = 1

It becomes The signals a ⁺ and a ^- are PL
The clock is applied to the L circuit 6 and the clock is generated by the PLL circuit 6.
k is generated.

Furthermore, in order to detect the equalization error,
In the parator C3, the equalizer output yn is the reference value v₃ (= 1)
It is judged whether it is larger or smaller (the judgment signal e₊₁), Again
Data C4 is equalizer output y_n Is the reference value v_Four Greater than (= 0)
Whether it is small (determination signal e₀ ), The comparator C5 is an equalizer
Output y_n Is the reference value v_Five Judge whether it is larger or smaller than (= -1)
(Determination signal e_-1). Then, data extraction / equalization error
As shown in detail in FIG.
Each output a of the data C1 to C5⁺ , A^- , E₊₁, E 0, e_-1
And the clock from the PLL circuit 6
A_n And extract the ideal equalized waveform.
By detecting this, 6 types of tap coefficient correction signals CT₊₁, CT
₀ , CT_-1, CN₊₁, CN₀ , CN_-1Is output.

Then, this signal (CT₊₁, CN₊₁),
(CT₀ , CN₀ ), (CT_-1, CN -₁) Each analog
The addition value is the addition circuit 8₊₁, 8₀ , 8_-1Calculated by
Buffered and averaged, and the buffer 9
₊₁, 9₀ , 9_-1Via tap coefficient C₊₁, C
₀ , C_-1Is adapted.

Next, referring to FIG. 2, data extraction / etc.
The digitization error detection block 7 will be described in detail. First,
Output a of comparator C1⁺ Is DFF
) 701 (output AP₊₁), DFF702 (same AP₀ )
And DFF703 (same AP_-1) Through the OR gate
704 and the output a of the comparator C2 -
Is DFF711 (the same AN₊₁), DFF712 (the same AN
₀ ) And DFF713 (the same AN_-1) Through OR
Applied to the port 704. And of the OR gate 704
The output signal is the output data a of this equalization circuit._n Output as
Be done.

[0023] In addition, each output AP ₊₁ of these DFF701~703, AP _0, AP _-1 and DFF711~713
The respective outputs AN ₊₁ , AN ₀ , AN _-1 are applied to the selector 750. Further, the output e _{+1 of the} comparator C3 is DF
The output e _{0 of the} comparator C4 passes through the F721 and 722 (E _{0 +1} ) and the DFF 731 and 732 (E ₀ ).
The output e _{−1 of the} comparator C5 is output via the DFF74
It is applied to the selector 750 via _1, 742 (the same E ₋₁ ). The selector 750 uses AP ₊₁ and AP as shown below.
_{0, AP -1, AN +1,} AN 0, AN -1 and E _+1, E _0, E
_-1 multiplication is performed and six types of signals (CT
₊₁ , CN ₊₁ ), (CT ₀ , CN ₀ ), (CT _-1 , C)
N _-1 ) is output.

This selector 750 is configured to calculate e _k · a _k- j from the data string {a _n } and the equalization error {e _n }. Here, the PR4 detection method is ternary (0,
+1, −1) is detected, the equalizer output y _n is

[0025]

## EQU00004 ## In the case of y _n > 0.5 and −0.5> y _n , a _n = 1 and in the case of −0.5 <y _n <0.5, a _n = 0.

The correspondence is as follows. For this reason, even if the data a _n is “1”, there are both cases where y _n is positive and where y _n is negative. Therefore, it is necessary to distinguish both and calculate e _k · a _kj .

Since only the code needs to be considered for e _k , 1 may be considered as +1 and 0 may be considered as −1. Therefore, e _k · a _kj can be represented by the following, as shown in FIG. 3, and takes three values of 1, 0, −1. This is 2
Corresponding to analog addition of two logic outputs CT and CN,

[0028]

When e _k · a _kj = 1 CT = CN = 1, (CT + CN) / 2 = 1 When e _k · a _kj = 0 CT = 1, CN = 0, (CT + CN) / 2 = 1 In the case of / 2 e _k · a _kj = -1, CT = CN = 0, (CT + CN) / 2 = 0.

For example, e_k ・ A_k Will be described. Equalization
Error e_k As shown in FIG.₊₁, E 0, E_-1Using
Data a_k As AP₀ , AN₀ , The data AP
₀ , AN₀ The combination of

[0030]

(6) (1) AP ₀ = 1 (2) AP ₀ = AN ₀ = 0 (3) AN ₀ = 1 There are only three ways.

(1) When AP ₀ = 1 Since the equalizer output y ₀ should have been in the vicinity of "+1", E ₊₁ is selected as the error signal. In this case, if y ₀ is larger than the desired level (large as P-P value), E ₊₁ = + 1. At this time, as shown in FIG.

[0032]

## _EQU00007 ## e _k = 1, a _kj = 1, y _kj > 0.5

Corresponding to, CT ₀ = CN ₀ = 1 is output. Conversely, if y ₀ is less than the desired level, then E ₊₁ = 0
Which is shown in FIG. 3 at this time.

[0034]

## _EQU8 ## Corresponding to e _k = -1, a _kj = 1 and y _kj > 0.5, CT ₀ = CN ₀ = 0 is output.

[0035]

(2) When AP ₀ = AN ₀ = 0 Since y ₀ = 0 as described above, CT = 1, CN =
Set to 0. This corresponds to e _k = -1, a _kj = 0 e _k = 1 and a _kj = 0 shown in FIG. (3) When AN ₀ = 1 Since the equalizer output y ₀ should have been in the vicinity of “−1”, E ₋₁ is selected as the error signal. In this case, if y ₀ is larger than “−1” (that is, the PP value is small), E ₋₁ = 1 and CT ₀ = CN ₀ =
0 is output (corresponding to e _k = 1 and a _kj = 1 and y _kj <0.5 shown in FIG. 3). Conversely, y ₀ is smaller than “−1” (that is, P−
If P value is large), CT ₀ = 1 and CN ₀ = 0
_Is output (corresponding to e _k = −1, a _kj = 1 and y _kj <0.5 shown in FIG. 3). Therefore, if the PP _value of y ₀ is greater than ± 1, CT ₀ = CN ₀ = 1 is output, while if the PP _value of y ₀ is less than ± 1, CT ₀ = CN ₀ = 0 is output, and the tap coefficient C ₀ is adaptively controlled based on the analog addition value of CT ₀ and CN ₀ .

[0036]

Next, the case of e _k · a _{k + 1} will be described. First, as e _k , if (1) AP ₀ = 1 then E ₊₁ and (2) if AP ₀ = AN ₀ = 0 then E ₀ (3) If AN ₀ = 1 then use E ₋₁ . Further, AP ₊₁ and AN ₊₁ are used as a _{k + 1. In} this case, CT ₊₁ and CN ₊₁ are (1) AP ₊₁ = 1 and e _k = 1 and CT ₊₁ = CN ₊₁ = 1 (2) AP ₊₁ = 1, e _k = 0, CT ₊₁ = CN ₊₁ = 0 (3) AN ₊₁ = 1, e _k = 1, CT ₊₁ = CN ₊₁ = 0 (4 ) AN ₊₁ = 1, e _k = 0, CT ₊₁ = CN ₊₁ = 1 (5) AP ₊₁ = AN ₊₁ = 0, e _k = 0,1, CT ₊₁ =
1, CN ₊₁ = 0.

Next, the case of e _k · a _k-1 will be explained. Except that AP _-1 and AN _-1 are used as a _k-1 ,
Similar to the case of _k · a _{k + 1} , CT ₋₁ and CN ₋₁ are output.
To summarize the above processing, the CT and CN selected by the selector 750 are averaged for a long time, and the tap coefficients C _{+ 1} , _C0 , C- ₁ are adapted using the result.

[0038]

In the embodiment shown in FIG. 1, when the inverted signal is represented by (/), (1) (/) (CT ₀ + CN ₀ ) is larger than 1/2 → C ₀
(2) (/) (CT ₀ + CN ₀ ) is smaller than 1/2 → C ₀
(3) (/) (CT ₊₁ + CN ₊₁ ) is greater than 1/2 → C ₊₁
(4) (/) (CT ₊₁ + CN ₊₁ ) is smaller than 1/2 → C ₊₁
(5) (/) (CT _-1 + CN _-1 ) is greater than 1/2 → C _-1
(6) (/) (CT _-1 + CN _-1 ) is smaller than 1/2 → C ₊₁
By controlling so that the optimum tap coefficient C ₊₁ ,
C ₀ and C _-1 are obtained.

Next, a second embodiment will be described with reference to FIGS. 5 is a block diagram showing only the tap coefficient adaptation circuit of the second embodiment, FIG. 6 is a circuit diagram showing in detail the MAX circuit of FIG. 5, and FIG.
FIG. 8 is a block diagram showing the equalization error detection block in detail, and FIG. 8 is an explanatory diagram showing the operation of the selector shown in FIG.

In this second embodiment, as shown in FIG.
The comparator C5 shown in FIG. 1 is omitted. And
Instead rotation signal from the equalizer output y _n by the amplifier 11 to y _n and the inverted signal (/) y _n are obtained, then the forward signal y _n and the inverted signal by the MAX circuit 12 as shown in detail in FIG. 6 Of (/) y _n , the larger signal | y _n | is obtained, and this signal | y _n |
₃ = + 1 is compared. Here, this signal | y _n |
Since the eye pattern shown in FIG. 9 is folded in the positive direction from the 0 level, both the deviation from + l and the deviation from -1 are detected by the comparator C4 (determination signal e _{(+ 1, -1)} ), Therefore, is substantially equivalent to the circuit shown in FIG.

In the data extraction / equalization error detection block 7a shown in detail in FIG. 7, first, the output a ^{+ of the} comparator C1 is the DFF (flip-flop) 701 (output AP) as in the first embodiment shown in FIG. ₊₁ ), DFF702
O through the same AP ₀ and DFF 703 (the same AP _-1 ).
It is applied to the R gate 704, and the output a _{− of the} comparator C2 is DFF711 (AN ₊₁ ) and DFF712.
O through the same (AN ₀ ) and the DFF 713 (the same AN ₋₁ )
Is applied to the R gate 704, the output signal of the OR gate 704 is output as output data a _n of the equalizer.

Further, each output AP ₊₁ of these DFF701~703, AP _0, AP _-1 and DFF711~713
The respective outputs AN ₊₁ , AN ₀ , AN _-1 are applied to the selector 750. In the second embodiment, the output e _{0 of the} comparator C3 is output via DFFs 731 and 732 (E ₀ ) and the output e _{(+ 1, -1) of the} comparator C4 is D
It is applied to the selector 750a via the FFs 751 and 752 (the same E _{(+ 1, -1)} ).

In such a configuration, the selector 750a is
The multiplication as shown in FIG. 8 is performed. Difference from the first embodiment
Explaining only e_k ・ A_kj The calculation of AN₀ = 1 or
Is AP₀ E when = 1_{(+ 1, -1)} , But E
_{(+ 1, -1)} Has the opposite polarity. In addition, in FIG.
Signal e which is the inverted output of the transmitter C4_-1And its forward rotation signal e
+₁Is used, the operation is the same as that of the first embodiment.

[0044]

As described above, according to the present invention, the equivalent error amount is detected by the analog comparison circuit, extracted as a binary discrimination signal, and the restored data sequence of 0, +1 and -1 and the equivalent error amount. Since the multiplication of the binary discrimination result of is calculated by a simple logic circuit and output as two logic outputs, and the tap coefficient of the equalizer is controlled based on the analog average value of the two logic outputs, it is easy. PR of various configurations
It is possible to realize a 4-detection type automatic equalization circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic equalization circuit according to the present invention.

FIG. 2 is a block diagram showing in detail a data extraction / equalization error detection block of FIG.

FIG. 3 shows equalization error e _k and equalized data a _kj and e _k
It is explanatory drawing which shows the relationship of _akj .

FIG. 4 is an explanatory diagram showing an operation of the selector of FIG.

FIG. 5 is a block diagram showing a tap coefficient adaptation circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing the MAX circuit of FIG. 5 in detail.

7 is a block diagram showing in detail the data extraction / equalization error detection block of FIG. 6;

8 is an explanatory diagram showing the operation of the selector shown in FIG. 7. FIG.

FIG. 9 is an explanatory diagram showing an eye pattern after equalization by a PR4 detection method.

FIG. 10 is a block diagram showing an example of a conventional automatic equalization circuit.

[Explanation of symbols]

C _-1 , C ₀ , C ₊₁ tap coefficient 3 transversal filter (coefficient unit 3 _-1 , 3 ₀ , 3
₊₁ , adder 4, 5 and delay device DL _{1 to} DL ₃ constitute an equalizer) 3 _-1 , 3 ₀ , 3 ₊₁ coefficient device 4,5 adder DL _{1 to} DL ₃ delay device C1, C2 Comparator (first discriminating circuit) C3 to C5 Comparator (second discriminating circuit) 7,7a Data extraction / equalization error detection block (multiplication circuit) 8 ₊₁ , 8 ₀ , 8 _-1 Adder circuit (buffer 9) ₊₁ , 9 ₀ , 9
_-1 constitutes the tap coefficient control means together with the tap coefficient control means) 9 ₊₁ , 9 ₀ , 9 _-1 buffer 11 amplifier (constitutes the detection circuit together with the MAX circuit 12) 12 MAX circuit C3 comparator (second discrimination) Circuit) C4 comparator (third discrimination circuit)

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 25/497 9199-5K H04L 25/497

Claims (2)

[Claims] 1. A partial response 4-detection automatic equalization circuit for detecting ternary value (0, + 1, −1), wherein an ternary (0, + 1, −1) analog signal is changed with a variable tap coefficient. An equalizer for equalizing, a first discriminating circuit for discriminating between 0, +1, -1 of the signal equalized by the equalizer, and a signal equalized by the equalizer, 0, +1,- Comparing 1 with 1 and outputting a binary discrimination signal
Discriminating circuit, each of the binary discriminating signals discriminated by the three second discriminating circuits and the time-series signal discriminated by the first discriminating circuit are multiplied, and the multiplication result is output as two logic outputs. And a tap coefficient control means for controlling the tap coefficient of the equalizer based on the average value of the two logic outputs output by the multiplying means. circuit. 2. In a partial response 4-detection automatic equalization circuit for detecting ternary value (0, + 1, −1), an analog signal of ternary value (0, + 1, −1) is equalized with a variable tap coefficient. An equalizer for equalizing, a first discriminating circuit for discriminating between 0, +1 and −1 of the signal equalized by the equalizer, and comparing the signal equalized by the equalizer with 0, A second discriminating circuit for outputting a binary discriminating signal, a detecting circuit for taking out the signal equalized by the equalizer and its inverted signal, whichever is larger, and comparing the signal taken out by the detecting circuit with +1. Then
A third discriminating circuit for outputting a binary discriminating signal, each of the binary discriminating signals discriminated by the second and third discriminating circuits, and a time-series signal discriminated by the first discriminating circuit. And a tap coefficient control means for controlling the tap coefficient of the equalizer based on the average value of the two logic outputs output by the multiplication means. An automatic equalization circuit having: